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1. 发明申请

US20040268143A1 Trusted input for mobile platform transactions 审中-公开
标题翻译：用于移动平台交易的可信输入
公开(公告)号：US20040268143A1
公开(公告)日：2004-12-30
申请号：US10609828
申请日：2003-06-30
发明人： David I. Poisner
IPC分类号： G06F011/30 , H04L009/32 , H04L009/00 , G09G005/00 , G06F013/28 , G06F013/00 , G06F012/16 , G06F012/14 , G06F012/00
CPC分类号： G06F21/83
摘要： According to one embodiment, computer system is disclosed. The computer system includes a central processing unit (CPU), and a chipset coupled to the CPU including protected registers. The computer system also includes a micro-controller coupled to the chipset to perform scans to receive key-matrix data, wherein trusted software accesses the key-matrix data via the protected registers to ensure the authenticity of the data.
摘要翻译：根据一个实施例，公开了一种计算机系统。计算机系统包括中央处理单元（CPU）和耦合到CPU的芯片组，包括受保护的寄存器。计算机系统还包括耦合到芯片组的微控制器以执行扫描以接收键盘数据，其中可信软件通过受保护的寄存器访问密钥矩阵数据，以确保数据的真实性。

2. 发明申请

US20040267986A1 DMA controlled for mixed signal device 失效
标题翻译： DMA控制混合信号装置
公开(公告)号：US20040267986A1
公开(公告)日：2004-12-30
申请号：US10752740
申请日：2004-01-07
发明人： Kafai Leung , Ka Y. Leung
IPC分类号： G06F013/28
CPC分类号： H03M1/1057 , G06F13/28 , H03M1/468
摘要： DMA controller for mixed signal device. A mixed signal integrated circuit with memory control is disclosed. A data conversion circuit is provided that is operable to receive an analog input signal and convert discrete samples thereof at a predetermined sampling rate to a digital representations thereof as a plurality of digital words. A memory stores the digital words generated by the data conversion circuit. A processor is included on the integrated circuit and operable to access the memory to output select ones of the digital words for processing thereof in accordance with a predetermined processing algorithm. A memory access controller controls access to the memory by the data conversion circuit and the processor. The memory access controller is operable to restrict access to the memory by the data conversion circuit without interrupting the generation of digital words therefrom when the processor is accessing the memory, and allowing access to the memory by the data conversion circuitry when the processor is not accessing the memory, such that the data conversion circuit can transfer currently generated digital words and previously generated and non stored digital words for storage in said memory upon gaining access thereto.
摘要翻译： DMA控制器用于混合信号装置。公开了一种具有存储器控制的混合信号集成电路。提供了一种数据转换电路，其可操作以接收模拟输入信号并将其以预定采样率的离散采样转换为其数字表示作为多个数字字。存储器存储由数据转换电路产生的数字字。处理器被包括在集成电路中并且可操作以访问存储器以根据预定的处理算法输出用于处理的数字字的选择数字字。存储器访问控制器通过数据转换电路和处理器控制对存储器的访问。存储器访问控制器可操作以在处理器访问存储器时限制对数据转换电路对存储器的访问，而不会在处理器访问存储器时中断数字字的产生，并且当处理器未访问时允许数据转换电路访问存储器存储器，使得数据转换电路可以传送当前生成的数字字和先前生成的和未存储的数字字，以便在访问存储器时存储在所述存储器中。

3. 发明申请

US20040267970A1 Parallel port with direct memory access capabilities 失效
标题翻译：具有直接内存访问功能的并行端口
公开(公告)号：US20040267970A1
公开(公告)日：2004-12-30
申请号：US10894601
申请日：2004-07-20
发明人： James J. Jirgal
IPC分类号： G06F013/28
CPC分类号： G06F13/28 , G06F13/4269 , G06F2213/0004
摘要： The parallel or printer port in a personal computer can receive data from the memory under the control of the direct memory access (DMA) controller, releasing processor resources. The processor enables the parallel port, which then indicates to the DMA controller the desire to transfer data. A state machine in the parallel port, along with the associated circuitry, responds to the transfer of the data to the parallel port and then controls the transfer of the data to the attached device, usually a printer. The state machine causes an interrupt to the processor when the transfer is complete or on receipt of errors from the external device. The state machine also communicates with the DMA controller to repeat the transfer process until the transfer is complete or an error occurs. Various DMA channels and parallel port locations can be used. Direct transfers by the processor are blocked during DMA controller handled transfers.
摘要翻译：个人计算机中的并行或打印机端口可以在直接存储器访问（DMA）控制器的控制下从存储器接收数据，释放处理器资源。处理器启用并行端口，然后并行端口向DMA控制器指示传输数据的愿望。并行端口中的状态机连同相关的电路响应数据传输到并行端口，然后控制数据传输到连接的设备，通常是打印机。当传输完成或收到外部设备的错误时，状态机会导致处理器中断。状态机还与DMA控制器通信以重复传输过程，直到传输完成或发生错误。可以使用各种DMA通道和并行端口位置。在DMA控制器处理传输期间，处理器的直接传输将被阻止。

4. 发明申请

US20040243738A1 Method for asynchronous DMA command completion notification 有权
标题翻译：异步DMA命令完成通知的方法
公开(公告)号：US20040243738A1
公开(公告)日：2004-12-02
申请号：US10448237
申请日：2003-05-29
申请人： International Business Machines Corporation , Sony Computer Entertainment Inc.
发明人： Michael Norman Day , Harm Peter Hofstee , Charles Ray Johns , Peichum Peter Liu , Thuong Quang Truong , Takeshi Yamazaki
IPC分类号： G06F013/28
CPC分类号： G06F13/28
摘要： The present invention provides for asynchronous DMA command completion notification in a computer system. A command tag, associated with a plurality DMA command is generated. A DMA data movement command having the command tag is grouped with another DMA data movement command having the command tag. DMA commands belonging to the same tag group are monitored to see whether all DMA commands of the same tag group are completed.
摘要翻译：本发明在计算机系统中提供异步DMA命令完成通知。生成与多个DMA命令相关联的命令标签。具有命令标签的DMA数据移动命令与具有命令标签的另一DMA数据移动命令分组。监视属于同一标签组的DMA命令，以查看相同标签组的所有DMA命令是否完成。

5. 发明申请

US20040236877A1 Switch/network adapter port incorporating shared memory resources selectively accessible by a direct execution logic element and one or more dense logic devices in a fully buffered dual in-line memory module format (FB-DIMM) 审中-公开
标题翻译：交换机/网络适配器端口包含可由直接执行逻辑元件和一个或多个密集逻辑设备以完全缓冲的双列直插存储器模块格式（FB-DIMM）选择性地访问的共享存储器资源，
公开(公告)号：US20040236877A1
公开(公告)日：2004-11-25
申请号：US10869199
申请日：2004-06-16
发明人： Lee A. Burton
IPC分类号： G06F013/28
CPC分类号： G06F13/385 , G06F13/1668
摘要： An enhanced switch/network adapter port incorporating shared memory resources (nullSNAPMnullnull) selectively accessible by a direct execution logic element and one or more dense logic devices in a fully buffered dual in-line memory module (nullFB-DIMMnull) format for clustered computing systems employing direct execution logic such as multi-adaptive processor elements (nullMAPnullnull, all trademarks of SRC Computers, Inc.). Functionally, the SNAPM modules incorporate and properly allocate memory resources so that the memory appears to the associated dense logic device(s) (e.g. a microprocessor) to be functionally like any other system memory such that no time penalties are incurred when accessing it. Through the use of a programmable access coordination mechanism, the control of this memory can be handed off to the SNAPM memory controller and, once in control, the controller can move data between the shared memory resources and the computer network such that the transfer is performed at the maximum rate that the memory devices themselves can sustain. This provides the highest performance link to the other network devices such as MAPnull elements, common memory boards and the like.
摘要翻译：包括可由直接执行逻辑元件和完全缓冲双列直插存储器模块（“FB-DIMM”）中的一个或多个密集逻辑器件可选择地访问的共享存储器资源（“SNAPM TM”）的增强型交换机/网络适配器端口，）格式用于使用诸如多自适应处理器元件（“MAP”，SRC Computers，Inc.的所有商标）的直接执行逻辑的集群计算系统。在功能上，SNAPM模块并入并正确地分配存储器资源，使得相关联的密集逻辑设备（例如微处理器）的存储器在功能上与任何其他系统存储器一样，使得在访问时不会引起时间惩罚。通过使用可编程访问协调机制，可以将该存储器的控制权交给SNAPM存储器控制器，一旦控制，控制器可以在共享存储器资源和计算机网络之间移动数据，从而执行传输以存储器件本身可以承受的最大速率。这提供了与其他网络设备（例如MAP（R）），公共存储器板等的最高性能链接。

6. 发明申请

US20040230718A1 System including a host connected to a plurality of memory modules via a serial memory interconnet 有权
标题翻译：系统包括通过串行存储器互联连接到多个存储器模块的主机
公开(公告)号：US20040230718A1
公开(公告)日：2004-11-18
申请号：US10842296
申请日：2004-05-10
申请人： Advanced Micro Devices, Inc.
发明人： R. Stephen Polzin , Frederick D. Weber , Gerald R. Talbot , Larry D. Hewitt , Richard W. Reeves , Shwetal A. Patel , Ross V. La Fetra , Dale E. Gulick , Mark D. Hummel , Paul C. Miranda
IPC分类号： G06F013/28
CPC分类号： G06F13/4243 , G06F12/0215 , G06F12/0862 , G06F13/1626 , G06F2212/6022
摘要： A system including a host coupled to a serially connected chain of memory modules. In one embodiment, each of the memory modules includes a memory control hub for controlling access to a plurality of memory chips on the memory module. The memory modules are coupled serially in a chain to the host via a plurality of memory links. Each memory link may include an uplink for conveying transactions toward the host and a downlink for conveying transactions originating at the host to a next memory module in the chain. The uplink and the downlink may convey transactions using packets that include control and configuration packets and memory access packets. The memory control hub may convey a transaction received on a first downlink of a first memory link on a second downlink of a second memory link independent of decoding the transaction.
摘要翻译：一种系统，包括耦合到串行连接的存储器模块链的主机。在一个实施例中，每个存储器模块包括用于控制对存储器模块上的多个存储器芯片的访问的存储器控制集线器。存储器模块通过多个存储器链路串联地连接到主机。每个存储器链路可以包括用于向主机传送事务的上行链路和用于将在主机处发起的事务传送到链路中的下一个存储器模块的下行链路。上行链路和下行链路可以使用包括控制和配置分组和存储器访问分组的分组来传送事务。存储器控制集线器可以在第二存储器链路的第二下行链路上传送在第一存储器链路的第一下行链路上接收的事务，而与解码事务无关。

7. 发明申请

US20040215846A1 Method and system for efficient access to remote I/O functions in embedded control environments 失效
标题翻译：在嵌入式控制环境中有效访问远程I / O功能的方法和系统
公开(公告)号：US20040215846A1
公开(公告)日：2004-10-28
申请号：US10713822
申请日：2003-11-14
申请人： International Business Machines Corporation
发明人： Friedemann Baitinger , Gerald Kreissig , Juergen Saalmueller , Frank Scholz
IPC分类号： G06F013/28
CPC分类号： G06F13/385 , G06F13/102
摘要： A method for accessing I/O devices in embedded control environments is provided, wherein said I/O devices are remotely attached to an embedded microprocessor. By mapping said I/O devices' resources to said microprocessor's address or memory address space, existing device drivers can be reused and the time-to-market capability is greatly improved.

8. 发明申请

US20040193789A1 Associative memory device and method based on wave propagation 有权
标题翻译：基于波传播的关联存储器件和方法
公开(公告)号：US20040193789A1
公开(公告)日：2004-09-30
申请号：US10648855
申请日：2003-08-26
发明人： Paul Rudolf
IPC分类号： G06F013/28 , G06F013/00 , G06F012/16 , G06F012/14 , G06F012/00 , G11C015/00
CPC分类号： G06K9/6247 , G06N3/063
摘要： An associative, or content-addressable, memory device (101) and method based on waves is described. In this invention, arbitrary inputs are written as patterns which are interpreted as values of complex waves, discretized or analog, on one or more buffers (102,104). Information is transported via wave propagation from the buffers (102,104) to a cortex (103) or to multiple cortices, where the patterns are (1) associated using a mathematical operation for storage purposes or (2) de-associated through the corresponding inverse operation for retrieval purposes. The present associative memory is shown to emulate important behavioral properties of the human brain, including higher-brain functions such as learning from experience, forming generalizations or abstractions, and autonomous operation.
摘要翻译：描述了一种关联或内容寻址的存储设备（101）和基于波的方法。在本发明中，任意输入被写为在一个或多个缓冲器（102,104）上解释为复数波，离散化或模拟的值的图案。信息通过波形传播从缓冲器（102,104）传输到皮层（103）或多个皮质，其中图案（1）使用数学运算与存储目的相关联，或（2）通过相应的反向操作去相关联用于检索目的。目前的联想记忆被证明可以模仿人类大脑的重要行为特征，包括高级脑功能，如从经验中学习，形成概括或抽象，以及自主操作。

9. 发明申请

US20040183804A1 METHOD FOR A DISPLAY CONTROLLER TO ACCESS DATA STORED IN A SYSTEM MEMORY OF A COMPUTER DEVICE 有权
标题翻译：用于访问存储在计算机设备的系统存储器中的数据的显示控制器的方法
公开(公告)号：US20040183804A1
公开(公告)日：2004-09-23
申请号：US10708662
申请日：2004-03-18
发明人： Frank Lin , Victor Wu , Jacky Tsai , Hsiang-Yi Huang , Vincent Chang , Michael Liu , Heng-Chen Ho
IPC分类号： G06F012/00 , G06F012/16 , G06F013/00 , G06F013/28 , G09G005/39 , G06F012/14
CPC分类号： G06F13/1642 , G06F3/14 , G06F13/1626
摘要： A method for a display controller to access data stored in a system memory of a computer device is disclosed. The method includes using a memory controller to set a block capacity value; using the memory controller to divide a plurality of read requests corresponding to a predetermined request sequence into a plurality of request groups, wherein a total amount of data required by read requests grouped in each request group is less than the block capacity value; and using the memory controller to adjust a request sequence corresponding to read requests grouped in each request group for retrieving data stored at different N pages so that a memory device only performs Nnull1 page switching operations.
摘要翻译：公开了一种用于显示控制器访问存储在计算机设备的系统存储器中的数据的方法。该方法包括使用存储器控制器来设置块容量值; 使用存储器控制器将对应于预定请求序列的多个读取请求划分为多个请求组，其中分组在每个请求组中的读取请求所需的总数据量小于块容量值; 并且使用存储器控制器来调整与分组在每个请求组中的读取请求相对应的请求序列，用于检索存储在不同N页面的数据，使得存储器设备仅执行N-1个页面切换操作。

10. 发明申请

US20040172502A1 Composite EMI shield 有权
标题翻译：复合EMI屏蔽
公开(公告)号：US20040172502A1
公开(公告)日：2004-09-02
申请号：US10777331
申请日：2004-02-12
发明人： William G. Lionetta , Louis M. Yantosca JR. , Daniel S. Ventura , Christopher L. Severance , Douglas Nobbs , Robert E. Stiffler , David C. Rich
IPC分类号： G06F012/00 , G06F012/16 , G06F012/14 , G06F013/00 , G06F013/28
CPC分类号： H05K9/0032
摘要： An EMI shield having at least one compartment for enclosing circuitry of an electronic device. The shield includes a first member formed of a first material such as a thin metal sheet or screen, or a metal-plated fabric or other electrically-conductive mesh, and a second member formed of a second material different than the first material which second material is an admixture of a plastic or other polymeric component and an electrically-conductive particulate filler component. The second member is integrally joined to the first member, and has at least one wall which extends from the first member and which together with the first member defines at least a portion of the compartment.
摘要翻译：一种具有至少一个用于封闭电子设备的电路的隔间的EMI屏蔽。屏蔽包括由诸如薄金属片或屏幕的第一材料或金属镀层织物或其它导电网形成的第一构件，以及由不同于第一材料的第二材料形成的第二构件，第二材料是塑料或其它聚合物组分和导电颗粒填料组分的混合物。第二构件与第一构件一体地接合，并且具有至少一个从第一构件延伸的壁，并且与第一构件一起限定隔室的至少一部分。

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