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1. 发明授权

US07548996B2 Data streamer 有权
标题翻译：数据流
公开(公告)号：US07548996B2
公开(公告)日：2009-06-16
申请号：US11224738
申请日：2005-09-12
申请人： David Baker , Christopher Basoglu , Benjamin Cutler , Gregorio Gervasio , Woobin Lee , Yatin Mundkur , Toru Nojiri , John O'Donnell , John Poole, legal representative , Ashok Raman , Eric Rehm , Radhika Thekkath
发明人： David Poole
IPC分类号： G06F13/28
CPC分类号： G06F13/30 , G06F13/1605
摘要： In an information processing system which has plurality of modules including a processor, a main memory and a plurality of I/O devices, a data transfer switch for performing data transfer operations between the processor, main memory and I/O devices comprises a request bus which has a request bus arbiter for receiving read and write requests from each one of the plurality of modules. A processor memory bus is configured to receive address and data information from a predetermined number of modules, including the processor. The processor memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules which are coupled to the processor memory bus.An internal memory bus is configured to receive address and data information from a predetermined number of modules, including the memory and the I/O devices. The internal memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules coupled to the internal memory bus. A transceiver system is coupled to the processor memory bus and the internal memory bus for transferring data between the processor memory bus and the internal memory bus.
摘要翻译：在具有处理器，主存储器和多个I / O设备的多个模块的信息处理系统中，用于在处理器，主存储器和I / O设备之间执行数据传送操作的数据传送开关包括请求总线其具有用于从多个模块中的每一个接收读取和写入请求的请求总线仲裁器。处理器存储器总线被配置为从包括处理器的预定数量的模块接收地址和数据信息。处理器存储器总线具有用于从耦合到处理器存储器总线的预定数量的模块中的每一个接收数据读取和写入请求的数据总线仲裁器。内部存储器总线被配置为从包括存储器和I / O设备的预定数量的模块接收地址和数据信息。内部存储器总线具有用于从耦合到内部存储器总线的预定数量的模块中的每一个接收数据读取和写入请求的数据总线仲裁器。收发器系统耦合到处理器存储器总线和内部存储器总线，用于在处理器存储器总线和内部存储器总线之间传送数据。

2. 发明申请

US20080141224A1 DEBUG INFORMATION COLLECTION METHOD AND DEBUG INFORMATION COLLECTION SYSTEM 审中-公开
标题翻译：调试信息采集方法和调试信息采集系统
公开(公告)号：US20080141224A1
公开(公告)日：2008-06-12
申请号：US11947221
申请日：2007-11-29
申请人： Shinichiro Kawasaki , Toru Nojiri
发明人： Shinichiro Kawasaki , Toru Nojiri
IPC分类号： G06F11/36
CPC分类号： G06F11/362
摘要： In a software distribution unit, a binary-code analysis unit determines a total set of insertion positions at which probes can be inserted into software. A binary-code change unit determines the population of insertion positions of probes to be inserted into the software and the number of insertion positions of probes to be inserted on a device basis. Then, the binary-code change unit selects, from the population, insertion positions of probes as many as the determined number of insertion positions and inserts the probes into the software at the selected insertion positions. A software distribution unit distributes, to the device, the software into which the probes are inserted. As a result, it is possible to reduce both a load on the device side and a load on the software developer side at the same time and to acquire uniform debug information without deviations.
摘要翻译：在软件分发单元中，二进制代码分析单元确定可以将探针插入到软件中的插入位置的总组。二进制代码改变单元确定要插入到软件中的探针的插入位置的数量和要在设备基础上插入的探针的插入位置的数量。然后，二进制代码改变单元从群体中选择探测器的插入位置与所确定的插入位置数量一样多，并将探针插入到所选插入位置的软件中。软件分发单元向设备分发插入探针的软件。结果，可以同时减少设备侧的负载和软件开发者侧的负载，并且可以在没有偏差的情况下获取统一的调试信息。

3. 发明申请

US20080086729A1 DATA PROCESSOR 有权
标题翻译：数据处理器
公开(公告)号：US20080086729A1
公开(公告)日：2008-04-10
申请号：US11869565
申请日：2007-10-09
申请人： Yuki Kondoh , Takashi Matsumoto , Keisuke Toyama , Toru Nojiri
发明人： Yuki Kondoh , Takashi Matsumoto , Keisuke Toyama , Toru Nojiri
IPC分类号： G06F9/455 , G06F9/50
CPC分类号： G06F9/5077 , G06F9/45558 , G06F2009/45583
摘要： A data processor includes: a central processing unit (CPU), in which a plurality of virtual machines (101), each running an application program under controls of different operating systems, and a virtual machine manager (190) for controlling the plurality of virtual machines are selectively arranged according to information set in mode registers (140, 150, 151); and a resource access management module (110) for managing access to hardware resource available for the plurality of virtual machines. The resource access management module accepts, as inputs, the information set in the mode registers and access control information of the central processing unit to the hardware resource, compares the information thus input with information set in a control register, and controls whether or not to permit access to the hardware resource in response to the access control information. As a result, redesign involved in changes in system specifications can be reduced, and a malfunction owing to resource contention can be prevented. The invention contributes to increase of security.
摘要翻译：数据处理器包括：中央处理单元（CPU），其中在不同操作系统的控制下运行应用程序的多个虚拟机（101）和用于控制多个虚拟机的虚拟机器管理器（190）根据在模式寄存器（140,150,151）中设置的信息来选择性地布置机器; 以及用于管理对可用于所述多个虚拟机的硬件资源的访问的资源访问管理模块（110）。资源访问管理模块将在模式寄存器中设置的信息和中央处理单元的访问控制信息作为输入接受到硬件资源，将由此输入的信息与设置在控制寄存器中的信息进行比较，并且控制是否响应于访问控制信息允许访问硬件资源。因此，可以减少涉及系统规格变化的重新设计，并且可以防止由于资源争用引起的故障。本发明有助于提高安全性。

4. 发明授权

US06434649B1 Data streamer 有权
标题翻译：数据流
公开(公告)号：US06434649B1
公开(公告)日：2002-08-13
申请号：US09173297
申请日：1998-10-14
申请人： David Baker , Christopher Basoglu , Benjamin Cutler , Gregorio Gervasio , Woobin Lee , Yatin Mundkur , Toru Nojiri , John O'Donnell , David Poole , Ashok Raman , Eric Rehm , Radhika Thekkath
发明人： David Baker , Christopher Basoglu , Benjamin Cutler , Gregorio Gervasio , Woobin Lee , Yatin Mundkur , Toru Nojiri , John O'Donnell , David Poole , Ashok Raman , Eric Rehm , Radhika Thekkath
IPC分类号： G06F1300
CPC分类号： G06F13/30 , G06F13/1605
摘要： In an information processing system which has plurality of modules including a processor, a main memory and a plurality of I/O devices, a data transfer switch for performing data transfer operations between the processor, main memory and I/O devices comprises a request bus which has a request bus arbiter for receiving read and write requests from each one of the plurality of modules. A processor memory bus is configured to receive address and data information from a predetermined number of modules, including the processor. The processor memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules which are coupled to the processor memory bus. An internal memory bus is configured to receive address and data information from a predetermined number of modules, including the memory and the I/O devices. The internal memory bus has a data bus arbiter for receiving data read and write requests from each one of the predetermined number of modules coupled to the internal memory bus. A transceiver system is coupled to the processor memory bus and the internal memory bus for transferring data between the processor memory bus and the internal memory bus.
摘要翻译：在具有处理器，主存储器和多个I / O设备的多个模块的信息处理系统中，用于在处理器，主存储器和I / O设备之间执行数据传送操作的数据传送开关包括请求总线其具有用于从多个模块中的每一个接收读取和写入请求的请求总线仲裁器。处理器存储器总线被配置为从包括处理器的预定数量的模块接收地址和数据信息。处理器存储器总线具有用于从耦合到处理器存储器总线的预定数量的模块中的每一个接收数据读取和写入请求的数据总线仲裁器。内部存储器总线被配置为从预定数量接收地址和数据信息的模块，包括内存和I / O设备。内部存储器总线具有用于从耦合到内部存储器总线的预定数量的模块中的每一个接收数据读取和写入请求的数据总线仲裁器。收发器系统耦合到处理器存储器总线和内部存储器总线，用于在处理器存储器总线和内部存储器总线之间传送数据。

5. 发明授权

US07457890B2 Integrated multimedia system 有权
标题翻译：集成多媒体系统
公开(公告)号：US07457890B2
公开(公告)日：2008-11-25
申请号：US11589695
申请日：2006-10-30
申请人： David Baker , Christopher Basoglu , Benjamin Cutler , Richard Deeley , Gregorio Gervasio , Atsuo Kawaguchi , Keiji Kojima , Woobin Lee , Takeshi Miyazaki , Yatin Mundkur , Vinay Naik , Kiyokazu Nishioka , Toru Nojiri , John O'Donnell , Sarang Padalkar
发明人： David Baker , Christopher Basoglu , Benjamin Cutler , Richard Deeley , Gregorio Gervasio , Atsuo Kawaguchi , Keiji Kojima , Woobin Lee , Takeshi Miyazaki , Yatin Mundkur , Vinay Naik , Kiyokazu Nishioka , Toru Nojiri , John O'Donnell , Sarang Padalkar
IPC分类号： G06F3/00 , G06F15/76 , G06F1/00 , G06F15/16 , G06F13/14
CPC分类号： G06F13/102 , G06F13/124 , G06T15/005
摘要： An integrated multimedia system having a multimedia processor is disposed in an integrated circuit having a first host processor system coupled to the multimedia processor and a second local processor disposed within the multimedia processor for controlling the operation of the multimedia processor. A data transfer switch is coupled to the second processor for transferring data to various modules of the processor, at least one of which is a data cache. The data transfer switch transfers data in either direction between the cache and a module within the processor. A data streamer schedules simultaneous data transfers among the various-modules disposed within the multimedia processor in accordance with corresponding channel allocations. An interface unit is coupled to the data streamer and has a plurality of input/output (I/O) device driver units. A plurality of external I/O devices are coupled to the plurality of I/O device driver units via a multiplexer.
摘要翻译：具有多媒体处理器的集成多媒体系统被布置在具有耦合到多媒体处理器的第一主处理器系统的集成电路中，以及设置在多媒体处理器内的用于控制多媒体处理器的操作的第二本地处理器。数据传输开关耦合到第二处理器，用于将数据传送到处理器的各个模块，其中至少一个是数据高速缓存。数据传输交换机在缓存和处理器内的模块之间的任一方向上传输数据。数据流器根据相应的信道分配来调度在多媒体处理器内布置的各个模块之间的同时数据传输。接口单元耦合到数据流器并且具有多个输入/输出（I / O）设备驱动器单元。多个外部I / O设备经由多路复用器耦合到多个I / O设备驱动器单元。

6. 发明授权

US06965981B2 Processor including a plurality of computing devices 失效
标题翻译：处理器包括多个计算设备
公开(公告)号：US06965981B2
公开(公告)日：2005-11-15
申请号：US10053683
申请日：2002-01-24
申请人： Kiyokazu Nishioka , Kazuhiko Tanaka , Yoshifumi Fujikawa , Toru Nojiri , Keiji Kojima , Koichi Terada , Yoshiki Kurokawa , Koji Hosoki
发明人： Kiyokazu Nishioka , Kazuhiko Tanaka , Yoshifumi Fujikawa , Toru Nojiri , Keiji Kojima , Koichi Terada , Yoshiki Kurokawa , Koji Hosoki
IPC分类号： G06F9/318 , G06F9/38 , G06F15/00
CPC分类号： G06F9/3891 , G06F9/30036 , G06F9/30112 , G06F9/30167 , G06F9/30178 , G06F9/30181 , G06F9/30189 , G06F9/32 , G06F9/3802 , G06F9/3816 , G06F9/3822 , G06F9/3836 , G06F9/3853 , G06F9/3885 , G06F9/3887
摘要： As far as multimedia processing is concerned, a plurality of computations of a same type are often executed concurrently and hence a plurality of computing units having a same function are used and mode information for controlling the plurality of units by an instruction unit for one computing unit is prepared in each instruction to execute a plurality of computations with a single instruction.
摘要翻译：就多媒体处理而言，通常同时执行同一类型的多个计算，因此使用具有相同功能的多个计算单元和用于通过一个计算单元的指令单元来控制多个单元的模式信息在每个指令中准备以执行具有单个指令的多个计算。

7. 发明授权

US07818620B2 Program failure analysis system, failure analysis method, and emulator device 失效
标题翻译：程序故障分析系统，故障分析方法和仿真器
公开(公告)号：US07818620B2
公开(公告)日：2010-10-19
申请号：US11832040
申请日：2007-08-01
申请人： Takehiko Nagano , Toru Nojiri , Tomohiko Shigeoka
发明人： Takehiko Nagano , Toru Nojiri , Tomohiko Shigeoka
IPC分类号： G06F11/00
CPC分类号： G06F11/261 , G06F11/3652
摘要： A CPU forced stop signal is used as means for stopping execution of a program executed on a ROM by a CPU of a target system. A time required for stopping the CPU from the issuance of the CPU forced stop signal between an ICE device and the CPU is considered and set, and a CPU forced stop signal issuance position which is prior to a stop target position is determined. Based on a real-time tracing function of the CPU, at an issuance position and timing of the CPU forced stop signal on the execution of the program, the CPU forced stop signal is issued, the CPU is stopped, and the event is acquired. By this means, an arbitrary number of events of the program can be acquired regardless of the number of breakpoint registers.
摘要翻译： CPU强制停止信号被用作由目标系统的CPU停止在ROM上执行的程序的执行的装置。考虑并设置在ICE装置和CPU之间停止CPU发出CPU强制停止信号所需的时间，并确定停止目标位置之前的CPU强制停止信号发出位置。基于CPU的实时跟踪功能，在执行程序时CPU强制停止信号的发行位置和定时，发出CPU强制停止信号，CPU停止，并获取事件。通过这种方式，可以获取程序的任意数量的事件，而不管断点寄存器的数量。

8. 发明授权

US07272670B2 Integrated multimedia system 有权
标题翻译：集成多媒体系统
公开(公告)号：US07272670B2
公开(公告)日：2007-09-18
申请号：US09777003
申请日：2001-02-05
申请人： David Baker , Christopher Basoglu , Benjamin Cutler , Richard Deeley , Gregorio Gervasio , Atsuo Kawaguchi , Keiji Kojima , Woobin Lee , Takeshi Miyazaki , Yatin Mundkur , Vinay Naik , Kiyokazu Nishioka , Toru Nojiri , John O'Donnell , Sarang Padalkar
发明人： David Baker , Christopher Basoglu , Benjamin Cutler , Richard Deeley , Gregorio Gervasio , Atsuo Kawaguchi , Keiji Kojima , Woobin Lee , Takeshi Miyazaki , Yatin Mundkur , Vinay Naik , Kiyokazu Nishioka , Toru Nojiri , John O'Donnell , Sarang Padalkar
IPC分类号： G06F3/00 , G06F15/76 , G06F1/00 , G06F15/16 , G06F13/14
CPC分类号： G06F13/102 , G06F13/124 , G06T15/005
摘要： An integrated multimedia system has a multimedia processor disposed in an integrated circuit. A processor is disposed within the multimedia processor which controls the operation of the multimedia processor. A data transfer switch is disposed within the multimedia processor and coupled to the processor which transfers data to various modules of the multimedia processor. A fixed function unit is disposed within the multimedia processor, coupled to the processor and the data transfer switch. A data streamer is coupled to the data transfer switch, and configured to schedule simultaneous data transfers among a plurality of modules disposed within the multimedia processor in accordance with the corresponding channel allocations. As interface unit is coupled to the data streamer and has a plurality of I/O device driver units. A multiplexer coupled to the interface unit provides access between a selected number of I/O device driver units and external I/O devices via output pins.
摘要翻译：集成多媒体系统具有设置在集成电路中的多媒体处理器。处理器被布置在控制多媒体处理器的操作的多媒体处理器内。数据传输交换机设置在多媒体处理器内并且耦合到处理器，该处理器将数据传送到多媒体处理器的各个模块。固定功能单元设置在多媒体处理器内，耦合到处理器和数据传输开关。数据流器耦合到数据传输交换机，并且被配置为根据相应的信道分配来调度在多媒体处理器内设置的多个模块之间的同时数据传输。由于接口单元耦合到数据流器并且具有多个I / O设备驱动器单元。耦合到接口单元的多路复用器通过输出引脚提供所选数量的I / O设备驱动器单元和外部I / O设备之间的访问。

9. 发明申请

US20070130401A1 Integrated multimedia system 有权
标题翻译：集成多媒体系统
公开(公告)号：US20070130401A1
公开(公告)日：2007-06-07
申请号：US11589695
申请日：2006-10-30
申请人： David Baker , Christopher Basoglu , Benjamin Cutler , Richard Deeley , Gregorio Gervasio , Atsuo Kawaguchi , Keiji Kojima , Woobin Lee , Takeshi Miyazaki , Yatin Mundkur , Vinay Naik , Kiyokazu Nishioka , Kiyokazu Nishioka , Toru Nojiri , John O'Donnell , Sarang Padalkar
发明人： David Baker , Christopher Basoglu , Benjamin Cutler , Richard Deeley , Gregorio Gervasio , Atsuo Kawaguchi , Keiji Kojima , Woobin Lee , Takeshi Miyazaki , Yatin Mundkur , Vinay Naik , Kiyokazu Nishioka , Kiyokazu Nishioka , Toru Nojiri , John O'Donnell , Sarang Padalkar
IPC分类号： G06F13/38
CPC分类号： G06F13/102 , G06F13/124 , G06T15/005
摘要： An integrated multimedia system having a multimedia processor is disposed in an integrated circuit having a first host processor system coupled to the multimedia processor and a second local processor disposed within the multimedia processor for controlling the operation of the multimedia processor. A data transfer switch is coupled to the second processor for transferring data to various modules of the processor, at least one of which is a data cache. The data transfer switch transfers data in either direction between the cache and a module within the processor. A data streamer schedules simultaneous data transfers among the various-modules disposed within the multimedia processor in accordance with corresponding channel allocations. An interface unit is coupled to the data streamer and has a plurality of input/output (I/O) device driver units. A plurality of external I/O devices are coupled to the plurality of I/O device driver units via a multiplexer.
摘要翻译：具有多媒体处理器的集成多媒体系统被布置在具有耦合到多媒体处理器的第一主处理器系统的集成电路中，以及设置在多媒体处理器内的用于控制多媒体处理器的操作的第二本地处理器。数据传输开关耦合到第二处理器，用于将数据传送到处理器的各个模块，其中至少一个是数据高速缓存。数据传输交换机在缓存和处理器内的模块之间的任一方向上传输数据。数据流器根据相应的信道分配来调度在多媒体处理器内布置的各个模块之间的同时数据传输。接口单元耦合到数据流器并且具有多个输入/输出（I / O）设备驱动器单元。多个外部I / O设备经由多路复用器耦合到多个I / O设备驱动器单元。

10. 发明授权

US07103733B2 Computer system obtaining information on capacity and usage of an area used by a computer and notifying the computer the status thereof 有权
标题翻译：计算机系统获取计算机使用的区域的容量和使用信息，并通知计算机的状态
公开(公告)号：US07103733B2
公开(公告)日：2006-09-05
申请号：US10302153
申请日：2002-11-21
申请人： Masayasu Asano , Yasunori Kaneda , Toru Nojiri
发明人： Masayasu Asano , Yasunori Kaneda , Toru Nojiri
IPC分类号： G06F12/00
CPC分类号： G06F11/3442 , G06F3/0605 , G06F3/0653 , G06F11/3433 , G06F11/3485 , G06F2206/1012
摘要： A computer system includes a plurality of computers and at least one storage connected to the plurality of computers. The storage includes a device that obtains information concerning areas within the storage that are used by the respective plurality of computers, a device that obtains information concerning a capacity within each of the areas that is used by each of the plurality of computers to store-data, and a device that notifies at least one of the plurality of computers of a status of the areas within the at least one storage. The computer system utilizes and manage the storage, without having each of the computers utilize and manage the storages with regard to storage capacity.
摘要翻译：计算机系统包括多个计算机和连接到多个计算机的至少一个存储器。所述存储装置包括：获取关于所述存储器中由所述各个计算机使用的区域的信息的装置;获取与所述多个计算机中的每一个使用的每个所述区域内的容量相关的存储数据的信息的装置以及将所述多个计算机中的至少一个通知所述至少一个存储器内的区域的状态的设备。计算机系统利用和管理存储器，而不必使每个计算机利用和管理关于存储容量的存储器。

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