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61. 再颁专利

USRE37539E1 Sealed stacked arrangement of semiconductor devices 有权
标题翻译：密封堆叠布置的半导体器件
公开(公告)号：USRE37539E1
公开(公告)日：2002-02-05
申请号：US09471000
申请日：1999-12-23
申请人： Satoshi Oguchi , Masamichi Ishihara , Kazuya Ito , Gen Murakami , Ichiro Anjoh , Toshiyuki Sakuta , Yasunori Yamaguchi , Yasuhiro Kasama , Tetsu Udagawa , Eiji Momose , Youichi Matsuno , Hiroshi Satoh , Atsusi Nozoe
发明人： Satoshi Oguchi , Masamichi Ishihara , Kazuya Ito , Gen Murakami , Ichiro Anjoh , Toshiyuki Sakuta , Yasunori Yamaguchi , Yasuhiro Kasama , Tetsu Udagawa , Eiji Momose , Youichi Matsuno , Hiroshi Satoh , Atsusi Nozoe
IPC分类号： H01L2328
CPC分类号： H01L24/06 , G11C5/00 , G11C5/02 , G11C5/06 , H01L23/4951 , H01L23/49537 , H01L23/49575 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/0652 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/06136 , H01L2224/32245 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/4554 , H01L2224/4569 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/4826 , H01L2224/49171 , H01L2224/49175 , H01L2224/73215 , H01L2224/73265 , H01L2225/1029 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01043 , H01L2924/01047 , H01L2924/01055 , H01L2924/01073 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A pair of DRAM chips 1A and 1B are mounted opposedly to each other with wiring means such as lead frames put therebetween, the lead frames being substantially integral with external terminals 3B. Then, these DRAM chips and lead frames are connected together by the conventional wire bonding method. Plural pairs of the thus-connected DRAM chips and lead frames are stacked and corresponding leads of the lead frames are connected in common to form a laminate. The plural DRAM chips thus mounted are activated selectively in accordance with a predetermined chip selection signal. Additionally, partial DRAM chips capable of partially functioning normally are combined together by utilizing the above chip mounting method to constitute a single DRAM package.
摘要翻译：一对DRAM芯片1A和1B通过诸如引线框架之间的布线装置彼此相对地安装，引线框架与外部端子3B基本上成一体。然后，这些DRAM芯片和引线框架通过常规的引线键合方法连接在一起。堆叠这样连接的DRAM芯片和引线框架的多对，引线框架的相应引线共同连接以形成层叠体。这样安装的多个DRAM芯片根据预定的芯片选择信号选择性地被激活。此外，通过利用上述芯片安装方法，能够正常部分正常工作的部分DRAM芯片组合在一起，以构成单个DRAM封装。

62. 发明授权

US5583375A Semiconductor device with lead structure within the planar area of the device 失效
标题翻译：具有引线结构的半导体器件在器件的平面区域内
公开(公告)号：US5583375A
公开(公告)日：1996-12-10
申请号：US990633
申请日：1992-12-14
申请人： Kunihiro Tsubosaki , Michio Tanimoto , Kunihiko Nishi , Masahiro Ichitani , Shunji Koike , Kazunari Suzuki , Ryosuke Kimoto , Ichiro Anjoh , Taisei Jin , Akihiko Iwaya , Gen Murakami , Masamichi Ishihara , Junichi Arita
发明人： Kunihiro Tsubosaki , Michio Tanimoto , Kunihiko Nishi , Masahiro Ichitani , Shunji Koike , Kazunari Suzuki , Ryosuke Kimoto , Ichiro Anjoh , Taisei Jin , Akihiko Iwaya , Gen Murakami , Masamichi Ishihara , Junichi Arita
IPC分类号： H01L23/31 , H01L23/495 , H01L25/10 , H01L23/48
CPC分类号： H01L24/06 , H01L23/3107 , H01L23/3121 , H01L23/4951 , H01L24/05 , H01L24/49 , H01L25/105 , H01L2224/0401 , H01L2224/04042 , H01L2224/05554 , H01L2224/05624 , H01L2224/06136 , H01L2224/32245 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48253 , H01L2224/4826 , H01L2224/48465 , H01L2224/48624 , H01L2224/48724 , H01L2224/49113 , H01L2224/49171 , H01L2224/73215 , H01L2224/85424 , H01L2225/1029 , H01L24/45 , H01L24/48 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/07802 , H01L2924/1305 , H01L2924/181 , H01L2924/351 , Y10T29/49121
摘要： A semiconductor device having inner leads secured via insulating adhesive films to the principal surface of a semiconductor chip and electrically connected to the respective external terminals of the semiconductor chip. The semiconductor device that can be about the size of the chip is so configured that an outer lead is continuously extended from each inner lead up to the rear surface opposite to the principal surface of the semiconductor chip in order to hold the leads and an external device in conduction.
摘要翻译：一种半导体器件，其具有通过绝缘粘合剂膜固定到半导体芯片的主表面并与半导体芯片的各个外部端子电连接的内部引线。可以关于芯片尺寸的半导体器件被配置为使得外引线从每个内引线连续地延伸到与半导体芯片的主表面相对的后表面，以便保持引线和外部器件导通。

63. 发明授权

US5466888A Packaged semiconductor device having stress absorbing film 失效
公开(公告)号：US5466888A
公开(公告)日：1995-11-14
申请号：US384836
申请日：1995-02-07
申请人： Lim T. Beng , Chai T. Chong , Masazumi Amagai , Ichiro Anjoh , Junichi Arita , Kunihiro Tsubosaki , Masahiro Ichitani , Darvin Edwards
发明人： Lim T. Beng , Chai T. Chong , Masazumi Amagai , Ichiro Anjoh , Junichi Arita , Kunihiro Tsubosaki , Masahiro Ichitani , Darvin Edwards
IPC分类号： H01L23/31 , H01L23/495 , H01L23/28
CPC分类号： H01L24/06 , H01L23/3107 , H01L23/4951 , H01L23/49555 , H01L24/05 , H01L24/29 , H01L2224/04042 , H01L2224/05554 , H01L2224/05556 , H01L2224/06136 , H01L2224/32245 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/4569 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/48599 , H01L2224/48647 , H01L2224/48655 , H01L2224/4866 , H01L2224/48799 , H01L2224/48847 , H01L2224/48855 , H01L2224/4886 , H01L2224/73215 , H01L2224/83101 , H01L2224/85207 , H01L2224/85447 , H01L2224/85455 , H01L2224/8546 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01058 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/10253 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/3025 , H01L2924/351
摘要： A packaged semiconductor device has a semiconductor chip and leads formed over the chip with an electrically insulating film interposed therebetween and a packaging material for sealing the chip and the inner lead portions of the leads. The electrically insulating film has such an area as to provide a peripheral portion not covered by parts of the inner lead portions of the leads for strengthening adherence of the electrically insulating film to the packaging material and to the chip. The electrically insulating film has a thickness substantially in a range from 80 .mu.m to 200 .mu.m for absorbing stress which may be produced in the packaged semiconductor device when subjected to variations of the ambient temperature. A stress absorption film may be formed between the electrically insulating film and the semiconductor chip for absorbing stress which may be produced in the packaged semiconductor device when subjected to variations of the ambient temperature.

64. 发明授权

US5406028A Packaged semiconductor device having stress absorbing film 失效
标题翻译：具有应力吸收膜的封装半导体器件
公开(公告)号：US5406028A
公开(公告)日：1995-04-11
申请号：US198389
申请日：1994-02-18
申请人： Lim T. Beng , Chai T. Chong , Masazumi Amagai , Ichiro Anjoh , Junichi Arita , Kunihiro Tsubosaki , Masahiro Ichitani , Darvin Edwards
发明人： Lim T. Beng , Chai T. Chong , Masazumi Amagai , Ichiro Anjoh , Junichi Arita , Kunihiro Tsubosaki , Masahiro Ichitani , Darvin Edwards
IPC分类号： H01L23/31 , H01L23/495 , H01L23/28
CPC分类号： H01L24/06 , H01L23/3107 , H01L23/4951 , H01L23/49555 , H01L24/05 , H01L24/29 , H01L2224/04042 , H01L2224/05554 , H01L2224/05556 , H01L2224/06136 , H01L2224/32245 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/4569 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/48599 , H01L2224/48647 , H01L2224/48655 , H01L2224/4866 , H01L2224/48799 , H01L2224/48847 , H01L2224/48855 , H01L2224/4886 , H01L2224/73215 , H01L2224/83101 , H01L2224/85207 , H01L2224/85447 , H01L2224/85455 , H01L2224/8546 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01058 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/10253 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/3025 , H01L2924/351
摘要： A packaged semiconductor device has a semiconductor chip and leads formed over the chip with an electrically insulating film interposed therebetween and a packaging material for sealing the chip and the inner lead portions of the leads. The electrically insulating film has such an area as to provide a peripheral portion not covered by parts of the inner lead portions of the leads for strengthening adherence of the electrically insulating film to the packaging material and to the chip. The electrically insulating film has a thickness substantially in a range from 80 .mu.m to 200 .mu.m for absorbing stress which may be produced in the packaged semiconductor device when subjected to variations of the ambient temperature. A stress absorption film may be formed between the electrically insulating film and the semiconductor chip for absorbing stress which may be produced in the packaged semiconductor device when subjected to variations of the ambient temperature.
摘要翻译：封装的半导体器件具有半导体芯片和在芯片上形成的引线，其间插入有电绝缘膜，以及用于密封芯片和引线的内引线部分的封装材料。电绝缘膜具有这样的区域：提供不被引线的内引线部分的部分覆盖的周边部分，用于加强电绝缘膜对包装材料和芯片的粘附。电绝缘膜的厚度基本上在80μm至200μm的范围内，用于吸收当经受环境温度变化时在封装半导体器件中产生的应力。可以在电绝缘膜和半导体芯片之间形成应力吸收膜，用于吸收当经受环境温度变化时在封装半导体器件中产生的应力。

65. 发明申请

US20090020873A1 SEMICONDUCTOR APPARATUS, AND METHOD OF MANUFACTURING SEMICONDUCTOR APPARATUS 有权
标题翻译：半导体装置和制造半导体装置的方法
公开(公告)号：US20090020873A1
公开(公告)日：2009-01-22
申请号：US12173245
申请日：2008-07-15
申请人： Mitsuhisa Watanabe , Ichiro Anjoh
发明人： Mitsuhisa Watanabe , Ichiro Anjoh
IPC分类号： H01L23/48 , H01L21/56
CPC分类号： H01L21/561 , H01L21/6835 , H01L21/6836 , H01L23/13 , H01L23/3128 , H01L23/49816 , H01L23/544 , H01L24/06 , H01L24/16 , H01L24/17 , H01L24/27 , H01L24/90 , H01L24/94 , H01L2221/68327 , H01L2221/68381 , H01L2223/54486 , H01L2224/0401 , H01L2224/04042 , H01L2224/06136 , H01L2224/1134 , H01L2224/13099 , H01L2224/1601 , H01L2224/16225 , H01L2224/16237 , H01L2224/274 , H01L2224/32225 , H01L2224/73204 , H01L2224/75 , H01L2224/81193 , H01L2224/83191 , H01L2224/83194 , H01L2224/83856 , H01L2224/90 , H01L2924/00013 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/01068 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/181 , H01L2924/19041 , H01L2924/3025 , H01L2924/351 , H01L2924/00014 , H01L2924/3512 , H01L2924/00
摘要： A semiconductor apparatus includes a semiconductor chip in which a plurality of electrode pads are provided on a main surface, and a plurality of bump electrodes are provided on the electrode pads of the semiconductor chip. The semiconductor apparatus also includes a wired board which is allocated in a side of the main surface of the semiconductor chip, and is positioned in a central area of the main surface of the semiconductor chip so as to be separated from an edge part of the semiconductor chip by at least 50 μm or more. The semiconductor apparatus also includes a plurality of external terminals which are provided on the wired board, and which are electrically connected to a plurality of bump electrodes through wirings of the wired board, and sealing part which is provided between the semiconductor chip and the wired board, is made of underfill material that covers a connection part between the bump electrode and the wiring.
摘要翻译：半导体装置包括半导体芯片，其中多个电极焊盘设置在主表面上，并且多个凸起电极设置在半导体芯片的电极焊盘上。半导体装置还包括布线基板，其分配在半导体芯片的主表面的一侧，并且位于半导体芯片的主表面的中心区域中，以与半导体芯片的边缘部分分离芯片至少有50个以上。半导体装置还包括设置在布线板上的多个外部端子，并且通过布线板的布线与多个凸起电极电连接，以及设置在半导体芯片和布线板之间的密封部由底部填充材料制成，其覆盖凸起电极和布线之间的连接部分。

66. 发明申请

US20050189639A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20050189639A1
公开(公告)日：2005-09-01
申请号：US11025634
申请日：2004-12-28
申请人： Hisashi Tanie , Nae Hisano , Hiroyuki Ohta , Hiroaki Ikeda , Ichiro Anjoh , Mitsuaki Katagiri , Yuji Watanabe
发明人： Hisashi Tanie , Nae Hisano , Hiroyuki Ohta , Hiroaki Ikeda , Ichiro Anjoh , Mitsuaki Katagiri , Yuji Watanabe
IPC分类号： H01L25/18 , H01L23/48 , H01L25/065 , H01L25/07 , H01L25/10
CPC分类号： H01L25/0657 , H01L23/481 , H01L24/48 , H01L2224/05573 , H01L2224/05647 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48472 , H01L2224/73204 , H01L2225/06513 , H01L2225/0652 , H01L2225/06541 , H01L2225/06589 , H01L2225/06593 , H01L2924/00014 , H01L2924/01019 , H01L2924/01079 , H01L2924/01087 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/15312 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device capable of reducing a temperature increase during operation thereof is provided. In the semiconductor device, an interface chip is stacked on a plurality of stacked semiconductor elements. Both an “Si” interposer and a resin interposer are arranged under the plural semiconductor elements. The Si interposer is arranged between the resin interposer and the plural semiconductor elements. The Si interposer owns a thickness which is thicker than a thickness of a semiconductor element, and also has a linear expansion coefficient which is smaller than a linear expansion coefficient of the resin interposer, and further, is larger than, or equal to linear expansion coefficients of the plural semiconductor elements.
摘要翻译：提供一种能够在其操作期间降低温度升高的半导体器件。在半导体装置中，在多个层叠的半导体元件上层叠有接口芯片。 “Si”插入件和树脂插入器都布置在多个半导体元件下方。 Si插入件布置在树脂插入件和多个半导体元件之间。 Si插入件具有比半导体元件的厚度厚的厚度，并且还具有比树脂插入体的线膨胀系数小的线膨胀系数，并且还大于或等于线膨胀系数的多个半导体元件。

67. 发明授权

US6114005A Laminate and multilayer printed circuit board 失效
标题翻译：层压板和多层印刷电路板
公开(公告)号：US6114005A
公开(公告)日：2000-09-05
申请号：US859659
申请日：1997-05-20
申请人： Akira Nagai , Masatsugu Ogata , Shuji Eguchi , Masahiko Ogino , Toshiaki Ishii , Masanori Segawa , Hiroyoshi Kokaku , Ryo Moteki , Ichiro Anjoh
发明人： Akira Nagai , Masatsugu Ogata , Shuji Eguchi , Masahiko Ogino , Toshiaki Ishii , Masanori Segawa , Hiroyoshi Kokaku , Ryo Moteki , Ichiro Anjoh
IPC分类号： B32B27/12 , H01L23/14 , H05K1/03 , B32B5/12
CPC分类号： B32B27/12 , H01L23/145 , H05K1/0373 , H01L2224/48227 , H01L2924/10253 , H01L2924/12044 , H01L2924/15311 , H01L2924/30107 , H01L2924/3025 , H05K2201/015 , H05K2201/0209 , H05K2201/0212 , H05K2201/029 , H05K2201/068 , Y10S428/901 , Y10T428/24132 , Y10T428/254
摘要： A laminate capable of mounting semiconductor elements thereon; comprising an insulating layer which is constituted by a resin portion of sea-island structure and a woven reinforcement. The resin portion of sea-island structure is, for example, such that a resin as islands are dispersed in a resin as a matrix. Thus, the insulating layer exhibits a coefficient of thermal expansion of 3.0.about.10 (ppm/K) in a planar direction thereof and a glass transition temperature of 150.about.300 (.degree.C.). Owing to these physical properties, thermal stresses which the laminate undergoes in packaging the semiconductor elements thereon can be reduced, so that the connections of the laminate with the semiconductor elements can be made highly reliable.
摘要翻译：能够在其上安装半导体元件的层压体; 包括由海岛结构的树脂部分和织造加强件构成的绝缘层。例如，海岛结构的树脂部分使得岛状树脂以树脂为基体分散。因此，绝缘层在其平面方向上的热膨胀系数为3.0D（ppm / K），玻璃化转变温度为150℃（℃）。由于这些物理性质，可以减少层压体在其上封装半导体元件时的热应力，使得层压体与半导体元件的连接可以高度可靠。

68. 发明授权

US07786564B2 Semiconductor device and method for manufacturing semiconductor device 有权
标题翻译：半导体装置及半导体装置的制造方法
公开(公告)号：US07786564B2
公开(公告)日：2010-08-31
申请号：US12175714
申请日：2008-07-18
申请人： Mitsuhisa Watanabe , Ichiro Anjoh
发明人： Mitsuhisa Watanabe , Ichiro Anjoh
IPC分类号： H01L23/13
CPC分类号： H01L24/06 , H01L21/563 , H01L21/6836 , H01L23/3114 , H01L23/49833 , H01L23/4985 , H01L24/83 , H01L24/90 , H01L25/0655 , H01L25/105 , H01L2221/68327 , H01L2224/0401 , H01L2224/04042 , H01L2224/06136 , H01L2224/1134 , H01L2224/13099 , H01L2224/131 , H01L2224/16225 , H01L2224/2919 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/75743 , H01L2224/83191 , H01L2224/83194 , H01L2224/838 , H01L2224/83851 , H01L2225/1023 , H01L2225/107 , H01L2924/00013 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/19041 , H01L2924/30105 , H01L2924/3511 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor device according to the present invention is provided with a semiconductor chip in which a plurality of electrode pads is provided on a principal surface, a plurality of bump electrodes provided on the electrode pads of the semiconductor chip, a square-shaped wiring board which is disposed on a side of the principal surface of the semiconductor chip, and in which at least two sides of an outer circumference that face each other are positioned in an area on the principal surface of the semiconductor chip, a plurality of external terminals which is provided on the wiring board, and which are electrically connected to a plurality of the bump electrodes through a wiring of the wiring board, and sealing material which is provided between the semiconductor chip and the wiring board, and which covers a connection part between the bump electrode and the wiring.
摘要翻译：根据本发明的半导体器件设置有半导体芯片，其中在主表面上设置多个电极焊盘，设置在半导体芯片的电极焊盘上的多个凸块电极，方形布线板，设置在半导体芯片的主表面的一侧，并且其中彼此面对的外周的至少两侧位于半导体芯片的主表面上的区域中，多个外部端子是设置在布线板上，并且通过布线板的布线电连接到多个凸块电极;以及密封材料，其设置在半导体芯片和布线板之间，并且覆盖凸块之间的连接部分电极和接线。

69. 发明授权

US06710610B1 Socket for testing of semiconductor device, and semiconductor device and method of manufacturing the semiconductor device 失效
标题翻译：用于半导体器件测试的插座以及半导体器件及半导体器件的制造方法
公开(公告)号：US06710610B1
公开(公告)日：2004-03-23
申请号：US09407838
申请日：1999-09-29
申请人： Naotaka Tanaka , Hiroyuki Ohta , Ichiro Anjoh , Hideo Arima , Akio Hasebe , Kenichi Yamamoto
发明人： Naotaka Tanaka , Hiroyuki Ohta , Ichiro Anjoh , Hideo Arima , Akio Hasebe , Kenichi Yamamoto
IPC分类号： G01R3102
CPC分类号： G01R1/0441 , H05K3/326
摘要： Electrode pads are formed on a tape circuit to correspond to positions of solder bumps on an IC. A plurality of pins formed on a periphery of the tape circuit provide electrical connection between the tape circuit and a mother socket. An elastomer sheet is provided between a portion of the tape circuit, on which the electrode pads are formed and the IC is mounted, and the mother socket, and a side surface of the sheet, which contacts with the tape circuit, is formed with cut grooves in lattice fashion such that respective centers of the electrode pads substantially coincide with intersections of the grooves. Thus portions defined by the grooves on the sheet are made independent from one another to enable accommodating pushing forces from the solder bumps, so that, even if dispersion in height generates between the solder bumps, the respective portions defined by the grooves are hardly influenced by one another, and so accommodate the pushing forces from the solder bumps to permit the solder bumps and the electrode pads to surely contact with each other.
摘要翻译：电极焊盘形成在磁带电路上以对应于IC上的焊料凸块的位置。形成在磁带电路的周边上的多个引脚在磁带电路和母插座之间提供电连接。弹性体片材设置在带状电路的形成有电极垫的部分和安装有IC的部分之间，并且母带和与带电路接触的片材的侧表面形成有切口凹槽以格子方式使得电极垫的各个中心基本上与凹槽的交叉重合。因此，由片上的凹槽限定的部分彼此独立，以便能够容纳来自焊料凸块的推力，使得即使在焊料凸块之间产生高度分散，由凹槽限定的各个部分几乎不受并且因此容纳来自焊料凸块的推力，以允许焊料凸块和电极焊盘彼此牢固地接触。

70. 发明授权

US5677045A Laminate and multilayer printed circuit board 失效
标题翻译：层压板和多层印刷电路板
公开(公告)号：US5677045A
公开(公告)日：1997-10-14
申请号：US430553
申请日：1995-04-28
申请人： Akira Nagai , Masatsugu Ogata , Shuji Eguchi , Masahiko Ogino , Toshiaki Ishii , Masanori Segawa , Hiroyoshi Kokaku , Ryo Moteki , Ichiro Anjoh
发明人： Akira Nagai , Masatsugu Ogata , Shuji Eguchi , Masahiko Ogino , Toshiaki Ishii , Masanori Segawa , Hiroyoshi Kokaku , Ryo Moteki , Ichiro Anjoh
IPC分类号： B32B27/12 , H01L23/14 , H05K1/03 , B32B7/00 , B32B3/02 , B32B5/12 , B32B5/16
CPC分类号： B32B27/12 , H01L23/145 , H05K1/0373 , H01L2224/48227 , H01L2924/10253 , H01L2924/12044 , H01L2924/15311 , H01L2924/30107 , H01L2924/3025 , H05K2201/015 , H05K2201/0209 , H05K2201/0212 , H05K2201/029 , H05K2201/068 , Y10S428/901 , Y10T428/23986 , Y10T428/24132 , Y10T428/254 , Y10T442/20 , Y10T442/209 , Y10T442/2123 , Y10T442/3854 , Y10T442/3919
摘要： A laminate capable of mounting semiconductor elements thereon; comprising an insulating layer which is constituted by a resin portion of sea-island structure and a woven reinforcement. The resin portion of sea-island structure is, for example, such that a resin as islands are dispersed in a resin as a matrix. Thus, the insulating layer exhibits a coefficient of thermal expansion of 3.0.about.10 (ppm/K) in a planar direction thereof and a glass transition temperature of 150.about.300 (.degree.C.). Owing to these physical properties, thermal stresses which the laminate undergoes in packaging the semiconductor elements thereon can be reduced, so that the connections of the laminate with the semiconductor elements can be made highly reliable.
摘要翻译：能够在其上安装半导体元件的层压体; 包括由海岛结构的树脂部分和织造加强件构成的绝缘层。例如，海岛结构的树脂部分使得岛状树脂以树脂为基体分散。因此，绝缘层在其平面方向上的热膨胀系数为3.0D（ppm / K），玻璃化转变温度为150℃（℃）。由于这些物理性质，可以减少层压体在其上封装半导体元件时的热应力，使得层压体与半导体元件的连接可以高度可靠。

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