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1. 发明授权

US06710610B1 Socket for testing of semiconductor device, and semiconductor device and method of manufacturing the semiconductor device 失效
标题翻译：用于半导体器件测试的插座以及半导体器件及半导体器件的制造方法
公开(公告)号：US06710610B1
公开(公告)日：2004-03-23
申请号：US09407838
申请日：1999-09-29
申请人： Naotaka Tanaka , Hiroyuki Ohta , Ichiro Anjoh , Hideo Arima , Akio Hasebe , Kenichi Yamamoto
发明人： Naotaka Tanaka , Hiroyuki Ohta , Ichiro Anjoh , Hideo Arima , Akio Hasebe , Kenichi Yamamoto
IPC分类号： G01R3102
CPC分类号： G01R1/0441 , H05K3/326
摘要： Electrode pads are formed on a tape circuit to correspond to positions of solder bumps on an IC. A plurality of pins formed on a periphery of the tape circuit provide electrical connection between the tape circuit and a mother socket. An elastomer sheet is provided between a portion of the tape circuit, on which the electrode pads are formed and the IC is mounted, and the mother socket, and a side surface of the sheet, which contacts with the tape circuit, is formed with cut grooves in lattice fashion such that respective centers of the electrode pads substantially coincide with intersections of the grooves. Thus portions defined by the grooves on the sheet are made independent from one another to enable accommodating pushing forces from the solder bumps, so that, even if dispersion in height generates between the solder bumps, the respective portions defined by the grooves are hardly influenced by one another, and so accommodate the pushing forces from the solder bumps to permit the solder bumps and the electrode pads to surely contact with each other.
摘要翻译：电极焊盘形成在磁带电路上以对应于IC上的焊料凸块的位置。形成在磁带电路的周边上的多个引脚在磁带电路和母插座之间提供电连接。弹性体片材设置在带状电路的形成有电极垫的部分和安装有IC的部分之间，并且母带和与带电路接触的片材的侧表面形成有切口凹槽以格子方式使得电极垫的各个中心基本上与凹槽的交叉重合。因此，由片上的凹槽限定的部分彼此独立，以便能够容纳来自焊料凸块的推力，使得即使在焊料凸块之间产生高度分散，由凹槽限定的各个部分几乎不受并且因此容纳来自焊料凸块的推力，以允许焊料凸块和电极焊盘彼此牢固地接触。

2. 发明授权

US5300735A Interconnected multilayer boards and fabrication processes thereof 失效
标题翻译：互连多层板及其制造工艺
公开(公告)号：US5300735A
公开(公告)日：1994-04-05
申请号：US37543
申请日：1993-03-22
申请人： Hitoshi Yokono , Hideo Arima , Takashi Inoue , Naoya Kitamura , Haruhiko Matsuyama , Hitoshi Oka , Fumio Kataoka , Fusaji Shoji , Hideyasu Murooka , Masayuki Kyooi
发明人： Hitoshi Yokono , Hideo Arima , Takashi Inoue , Naoya Kitamura , Haruhiko Matsuyama , Hitoshi Oka , Fumio Kataoka , Fusaji Shoji , Hideyasu Murooka , Masayuki Kyooi
IPC分类号： H01L21/48 , H01L27/01 , H05K3/10 , H05K3/24 , H05K3/46 , H05K1/00
CPC分类号： H01L21/4857 , H05K3/4647 , H01L2224/1147 , H01L2224/16 , H01L2224/73253 , H01L2924/01014 , H01L2924/01019 , H01L2924/01068 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/12044 , H01L2924/15312 , H01L2924/16152 , H01L2924/3025 , H05K2203/0733 , H05K2203/0769 , H05K3/108 , H05K3/243 , Y10S428/901 , Y10T29/49126 , Y10T29/49165
摘要： Described herein are interconnected mutilayer boards and their fabrication processes. Multilayer conductor lines of a skeleton structure are formed by conducting multilayer metallization while including all resist layers and metallic under-conductive layers and then removing the resist layers and metallic under-conductive layers at once. Spaces between the multilayer conductor lines of the skeleton structure are then filled with a solventless varnish so that insulating layers are formed. Modules making use of such interconnected multilayer boards and computers having such modules are also described.
摘要翻译：这里描述了互连的多层板及其制造工艺。骨架结构的多层导体线通过导电多层金属化而形成，同时包括所有的抗蚀剂层和金属的低导电层，然后立即去除抗蚀剂层和金属的不良导电层。然后用无溶剂清漆填充骨架结构的多层导体线之间的空隙，从而形成绝缘层。还描述了使用这种互连的多层板的模块和具有这种模块的计算机。

3. 发明授权

US4603008A Critical temperature sensitive resistor material 失效
标题翻译：临界温度敏感电阻材料
公开(公告)号：US4603008A
公开(公告)日：1986-07-29
申请号：US749279
申请日：1985-06-27
申请人： Hiromi Tosaki , Hideo Arima , Akira Ikegami , Yasuji Kamata
发明人： Hiromi Tosaki , Hideo Arima , Akira Ikegami , Yasuji Kamata
IPC分类号： H01C7/04 , H01B1/06
CPC分类号： H01C7/047 , Y10T29/49085
摘要： Disclosed herein is a critical temperature sensitive resistor material which comprises 60 to 90% by weight of VO.sub.2 and 40 to 10% by weight of RuO.sub.2. This material exhibits hysteresis of resistance that decreases remarkably over a temperature range in which the resistance varies greatly, and is hence used for measuring the temperature maintaining a high precision.
摘要翻译：本文公开了一种临界温度敏感电阻材料，其包含60至90重量％的VO2和40至10重量％的RuO 2。该材料表现出在电阻变化很大的温度范围内显着降低的电阻滞后性，因此用于维持高精度的温度测量。

4. 发明授权

US4386387A Low temperature sintering porcelain composition 失效
标题翻译：低温烧结瓷组成
公开(公告)号：US4386387A
公开(公告)日：1983-05-31
申请号：US321609
申请日：1981-11-16
申请人： Hirayoshi Tanei , Akira Ikegami , Hideo Arima , Tokio Isogai , Kiyoshi Kawabata
发明人： Hirayoshi Tanei , Akira Ikegami , Hideo Arima , Tokio Isogai , Kiyoshi Kawabata
IPC分类号： C04B35/00 , C04B35/499 , H01G4/12 , C04B35/46
CPC分类号： H01G4/1263 , C04B35/499
摘要： A porcelain composition comprising Pb(Fe.sub.2/3 W.sub.1/3)O.sub.3, PbTiO.sub.3 and Pb(Yb.sub.1/2 Nb.sub.1/2)O.sub.3 preferably within the range as defined by closed area of A-B-C-D-A in the accompanying triangular diagram can give a sintered product by sintering at a temperature as low as 1000.degree. C. or lower. The resulting sintered product has a high relative dielectric constant and a small dielectric loss tangent.
摘要翻译：包含Pb（Fe2 / 3W1 / 3）O3，PbTiO3和Pb（Yb1 / 2Nb1 / 2）O3的瓷组合物优选在由三角形图中的ABCDA的封闭区域限定的范围内，可以通过在温度低至1000℃或更低。所得到的烧结产品具有高的相对介电常数和小的介电损耗角正切。

5. 发明授权

US4361597A Process for making sensor for detecting fluid flow velocity or flow amount 失效
标题翻译：制造用于检测流体流速或流量的传感器的方法
公开(公告)号：US4361597A
公开(公告)日：1982-11-30
申请号：US229179
申请日：1981-01-27
申请人： Hideo Arima , Mituko Ito , Akira Ikegami , Sadayasu Ueno , Kanemasa Sato , Yutaka Nishimura
发明人： Hideo Arima , Mituko Ito , Akira Ikegami , Sadayasu Ueno , Kanemasa Sato , Yutaka Nishimura
IPC分类号： G01F1/68 , G01F1/692 , G01K7/22 , G01P5/12 , H01C7/02 , H01C17/065 , H01C17/242 , H01C7/04 , B05D3/06 , B05D5/12
CPC分类号： G01F1/692 , G01F1/68 , H01C17/065 , H01C17/242 , Y10T29/49099
摘要： A sensor for detecting a fluid flow velocity or flow amount with high precision and high reliability is made by applying a conductor paste comprising platinum powder and an organic vehicle to the outer surface of a fine inorganic insulating tube, followed by drying and firing, thereby forming a platinum film, processing the platinum film into a spiral band form by laser application, inserting a lead wire into the insulating tube, applying a platinum conductor paste to between the spiral platinum band and the lead wire, followed by drying and baking, thereby connecting the spiral platinum band film to the lead wire.
摘要翻译：通过将包含铂粉末和有机载体的导体糊料涂覆到无机绝缘管的精细外表面上，然后进行干燥和烧制，从而形成高精度和高可靠性的用于检测流体流速或流量的传感器，由此形成铂金膜，通过激光应用将铂膜加工成螺旋带形式，将引线插入绝缘管中，将铂导体膏施加到螺旋铂带和引线之间，然后进行干燥和烘烤，从而连接将螺旋铂金胶带贴到导线上。

6. 发明授权

US5388328A Process for fabricating an interconnected multilayer board 失效
标题翻译：用于制造互连的多层板的工艺
公开(公告)号：US5388328A
公开(公告)日：1995-02-14
申请号：US187546
申请日：1994-01-28
申请人： Hitoshi Yokono , Hideo Arima , Takashi Inoue , Naoya Kitamura , Haruhiko Matsuyama , Hitoshi Oka , Fumio Kataoka , Fusaji Shoji , Hideyasu Murooka , Masayuki Kyooi
发明人： Hitoshi Yokono , Hideo Arima , Takashi Inoue , Naoya Kitamura , Haruhiko Matsuyama , Hitoshi Oka , Fumio Kataoka , Fusaji Shoji , Hideyasu Murooka , Masayuki Kyooi
IPC分类号： H01L21/48 , H01L27/01 , H05K3/10 , H05K3/24 , H05K3/46
CPC分类号： H01L21/4857 , H05K3/4647 , H01L2224/1147 , H01L2224/16 , H01L2224/73253 , H01L2924/01014 , H01L2924/01019 , H01L2924/01068 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/12044 , H01L2924/15312 , H01L2924/16152 , H01L2924/3025 , H05K2203/0733 , H05K2203/0769 , H05K3/108 , H05K3/243 , Y10S428/901 , Y10T29/49126 , Y10T29/49165
摘要： A process for the fabrication of an interconnected multilayer board involves the steps of forming a metallic under-conductive layer on a base substrate, forming a windowed resist layer on the metallic under-conductive layer, filling windows of the resist layer with a conductor by plating thereby forming a conductor layer, forming another windowed resist layer on the conductor layer and filling windows of this resist layer with a conductor by plating, thereby forming a via-hole layer and to provide a two-level structure of the conductor layer and the via-hole layer. Thereafter, the resist layers and portions of the metallic under-conductor layer other than those in contact with a lower face of the conductor constituting the conductor layer are dissolved to form a two-level skeleton structure of conductor lines and spaces within the skeleton structure are filled with a varnish in a solventless form and the varnish is cured.
摘要翻译：制造相互连接的多层板的方法包括以下步骤：在基底基板上形成金属导电层，在金属下导电层上形成窗口化抗蚀剂层，用导体用电镀填充抗蚀剂层的窗口从而形成导体层，在导体层上形成另一个窗口化的抗蚀剂层，并通过电镀用导体填充该抗蚀剂层的窗口，从而形成通孔层，并提供导体层和通孔的两层结构井层。此后，除了与形成导体层的导体的下表面接触的金属下导体层的抗蚀剂层和部分被溶解以形成骨架结构内的导体线和空间的两级骨架结构填充无溶剂形式的清漆，并且清漆被固化。

7. 发明授权

US4481499A Gas detector 失效
标题翻译：气体探测器
公开(公告)号：US4481499A
公开(公告)日：1984-11-06
申请号：US489179
申请日：1983-04-27
申请人： Hideo Arima , Masayoshi Kaneyasu , Mitsuko Ito
发明人： Hideo Arima , Masayoshi Kaneyasu , Mitsuko Ito
IPC分类号： G01N27/12 , G01N27/04 , H01L7/00
CPC分类号： G01N27/12
摘要： A gas detector with a layer of gas sensing material comprising an oxide semiconductor, wherein at least one coating layer each of a p-type oxide semiconductor and an n-type oxide semiconductor is provided in a multi-layer arrangement on the surface of said layer of gas sensing material that contacts the gas. The gas detector can selectively identify only specific gases.
摘要翻译：一种具有包含氧化物半导体的气体感测材料层的气体检测器，其中在所述层的表面上以多层布置提供每个p型氧化物半导体和n型氧化物半导体的至少一个涂层与气体接触的气体传感材料。气体检测器可以选择性地识别特定气体。

8. 发明授权

US4457161A Gas detection device and method for detecting gas 失效
标题翻译：气体检测装置及气体检测方法
公开(公告)号：US4457161A
公开(公告)日：1984-07-03
申请号：US366304
申请日：1981-04-07
申请人： Shoichi Iwanaga , Nobuo Sato , Akira Ikegami , Tokio Isogai , Takanobu Noro , Hideo Arima
发明人： Shoichi Iwanaga , Nobuo Sato , Akira Ikegami , Tokio Isogai , Takanobu Noro , Hideo Arima
IPC分类号： G01N27/04 , G01N27/12 , G01N33/00
CPC分类号： G01N33/0031 , G01N27/12
摘要： A gas detection device and a method for detecting a gas where gas information including concentrations of gas components in a mixed gas, concentration, presence of specific gas components and the like is detected by measuring, e.g., the output voltages of a plurality of gas sensors having different gas selectivities. The gas selectivities, as a characteristic constant of the specific gas sensor, was previously determined. The measured output voltages and gas selectivities are then used for solving plural simultaneous equations for gas concentrations.
摘要翻译：一种气体检测装置和气体检测方法，其中气体信息包括混合气体中气体组分的浓度，浓度，特定气体组分的存在等，通过测量多个气体传感器的输出电压具有不同的气体选择性。作为特定气体传感器的特性常数，气体选择性是先前确定的。然后测量的输出电压和气体选择性用于求解气体浓度的多个联立方程。

9. 发明授权

US5393406A Method of producing a thin film multilayer wiring board 失效
标题翻译：薄膜多层布线板的制造方法
公开(公告)号：US5393406A
公开(公告)日：1995-02-28
申请号：US845942
申请日：1992-03-04
申请人： Hitoshi Yokono , Hideo Arima , Takashi Inoue , Naoya Kitamura
发明人： Hitoshi Yokono , Hideo Arima , Takashi Inoue , Naoya Kitamura
IPC分类号： H05K3/10 , H01L21/48 , H05K3/20 , H05K3/42 , H05K3/46 , C25D5/02
CPC分类号： H01L21/4857 , H05K3/423 , H05K3/465 , H05K3/4682 , H01L2224/16 , H01L2224/16235 , H01L2224/73253 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H01L2924/15312 , H01L2924/16152 , H01L2924/3511 , H05K2201/09881 , H05K2203/0723 , H05K2203/0733 , H05K2203/0769 , H05K3/107 , H05K3/108 , H05K3/205
摘要： A thin film multilayer wiring board-producing method of the present invention is intended to decrease thermal stresses developing during the formation of the multilayer construction, and also to greatly reduce the number of the steps of the process, as compared with a conventional method. A film material can be used as an insulating film of the multilayer wiring board, and is adhesively bonded to a predetermined portion. Wiring conductors are formed by electroplating. The wiring layers are repeated laminated to form the multilayer construction. A metallic film serving as an electrode is formed on one of upper and lower surfaces of a substrate, the metallic film being removed after a multilayer wiring is formed. A soluble insulating film is formed on a metallic undercoat film on the substrate, and grooves are formed in the soluble insulating film, and wiring conductors are formed in the grooves, using either electroplating or both electroplating and electroless plating. Thereafter, the soluble insulating film and the metallic undercoat film are removed. Subsequently, an insoluble insulating film is formed at those locations from which the soluble insulating film and the metallic undercoat have been removed.
摘要翻译：本发明的薄膜多层布线板的制造方法，与以往的方法相比，旨在降低在形成多层结构时的热应力发展，并且大大减少了工艺步骤的数量。膜材料可以用作多层布线板的绝缘膜，并且粘合到预定部分。接线导体通过电镀形成。重复层压布线层以形成多层结构。用作电极的金属膜形成在基板的上表面和下表面之一上，金属膜在形成多层布线之后被去除。在基板上的金属底涂层上形成可溶性绝缘膜，并且在可溶性绝缘膜中形成槽，并且使用电镀或电镀或无电镀两者在沟槽中形成布线导体。然后，除去可溶性绝缘膜和金属底涂膜。随后，在去除可溶性绝缘膜和金属底涂层的那些位置处形成不溶性绝缘膜。

10. 发明授权

US5375042A Semiconductor package employing substrate assembly having a pair of thin film circuits disposed one on each of oppositely facing surfaces of a thick film circuit 失效
标题翻译：半导体封装采用具有一对薄膜电路的基板组件，该薄膜电路设置在厚膜电路的相对的每个表面上
公开(公告)号：US5375042A
公开(公告)日：1994-12-20
申请号：US799950
申请日：1991-11-29
申请人： Hideo Arima , Kiyoshi Matsui , Kenji Takeda
发明人： Hideo Arima , Kiyoshi Matsui , Kenji Takeda
IPC分类号： H01L23/12 , H01L23/10 , H01L23/538 , H01L25/04 , H01L25/18 , H05K1/11
CPC分类号： H01L23/5385 , H01L23/10 , H01L2224/16 , H01L2224/16225 , H01L2224/45147 , H01L2924/00014 , H01L2924/01046 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/15174 , H01L2924/15312 , H01L2924/16152
摘要： A semiconductor package and an electronic circuit board in which the semiconductor package is mounted on an external circuit board. The semiconductor package has a substrate assembly and a semiconductor mounted on the substrate, where the substrate assembly is composed of a thick film circuit in the form of a ceramic circuit board and a pair of thin film circuits disposed one on each of opposite surfaces of the thick film circuits. Such a substrate assembly has one surface thereof connected to, i.e. electrically contacting, the semiconductor and an opposing surface thereof adapted to be connected to an external circuit. The thin film circuits of the assembly are formed of a heat-resisting resin and a conducting material.
摘要翻译：半导体封装和电子电路板，其中半导体封装安装在外部电路板上。半导体封装具有基板组件和安装在基板上的半导体，其中基板组件由陶瓷电路板形式的厚膜电路和一对薄膜电路组成，薄膜电路一厚膜电路。这种基板组件的一个表面连接到半导体的电接触，以及适于连接到外部电路的相对表面。组件的薄膜电路由耐热树脂和导电材料形成。

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