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1. 发明授权

US06710610B1 Socket for testing of semiconductor device, and semiconductor device and method of manufacturing the semiconductor device 失效
标题翻译：用于半导体器件测试的插座以及半导体器件及半导体器件的制造方法
公开(公告)号：US06710610B1
公开(公告)日：2004-03-23
申请号：US09407838
申请日：1999-09-29
申请人： Naotaka Tanaka , Hiroyuki Ohta , Ichiro Anjoh , Hideo Arima , Akio Hasebe , Kenichi Yamamoto
发明人： Naotaka Tanaka , Hiroyuki Ohta , Ichiro Anjoh , Hideo Arima , Akio Hasebe , Kenichi Yamamoto
IPC分类号： G01R3102
CPC分类号： G01R1/0441 , H05K3/326
摘要： Electrode pads are formed on a tape circuit to correspond to positions of solder bumps on an IC. A plurality of pins formed on a periphery of the tape circuit provide electrical connection between the tape circuit and a mother socket. An elastomer sheet is provided between a portion of the tape circuit, on which the electrode pads are formed and the IC is mounted, and the mother socket, and a side surface of the sheet, which contacts with the tape circuit, is formed with cut grooves in lattice fashion such that respective centers of the electrode pads substantially coincide with intersections of the grooves. Thus portions defined by the grooves on the sheet are made independent from one another to enable accommodating pushing forces from the solder bumps, so that, even if dispersion in height generates between the solder bumps, the respective portions defined by the grooves are hardly influenced by one another, and so accommodate the pushing forces from the solder bumps to permit the solder bumps and the electrode pads to surely contact with each other.
摘要翻译：电极焊盘形成在磁带电路上以对应于IC上的焊料凸块的位置。形成在磁带电路的周边上的多个引脚在磁带电路和母插座之间提供电连接。弹性体片材设置在带状电路的形成有电极垫的部分和安装有IC的部分之间，并且母带和与带电路接触的片材的侧表面形成有切口凹槽以格子方式使得电极垫的各个中心基本上与凹槽的交叉重合。因此，由片上的凹槽限定的部分彼此独立，以便能够容纳来自焊料凸块的推力，使得即使在焊料凸块之间产生高度分散，由凹槽限定的各个部分几乎不受并且因此容纳来自焊料凸块的推力，以允许焊料凸块和电极焊盘彼此牢固地接触。

2. 发明申请

US20050189639A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20050189639A1
公开(公告)日：2005-09-01
申请号：US11025634
申请日：2004-12-28
申请人： Hisashi Tanie , Nae Hisano , Hiroyuki Ohta , Hiroaki Ikeda , Ichiro Anjoh , Mitsuaki Katagiri , Yuji Watanabe
发明人： Hisashi Tanie , Nae Hisano , Hiroyuki Ohta , Hiroaki Ikeda , Ichiro Anjoh , Mitsuaki Katagiri , Yuji Watanabe
IPC分类号： H01L25/18 , H01L23/48 , H01L25/065 , H01L25/07 , H01L25/10
CPC分类号： H01L25/0657 , H01L23/481 , H01L24/48 , H01L2224/05573 , H01L2224/05647 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48472 , H01L2224/73204 , H01L2225/06513 , H01L2225/0652 , H01L2225/06541 , H01L2225/06589 , H01L2225/06593 , H01L2924/00014 , H01L2924/01019 , H01L2924/01079 , H01L2924/01087 , H01L2924/10253 , H01L2924/14 , H01L2924/15311 , H01L2924/15312 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device capable of reducing a temperature increase during operation thereof is provided. In the semiconductor device, an interface chip is stacked on a plurality of stacked semiconductor elements. Both an “Si” interposer and a resin interposer are arranged under the plural semiconductor elements. The Si interposer is arranged between the resin interposer and the plural semiconductor elements. The Si interposer owns a thickness which is thicker than a thickness of a semiconductor element, and also has a linear expansion coefficient which is smaller than a linear expansion coefficient of the resin interposer, and further, is larger than, or equal to linear expansion coefficients of the plural semiconductor elements.
摘要翻译：提供一种能够在其操作期间降低温度升高的半导体器件。在半导体装置中，在多个层叠的半导体元件上层叠有接口芯片。 “Si”插入件和树脂插入器都布置在多个半导体元件下方。 Si插入件布置在树脂插入件和多个半导体元件之间。 Si插入件具有比半导体元件的厚度厚的厚度，并且还具有比树脂插入体的线膨胀系数小的线膨胀系数，并且还大于或等于线膨胀系数的多个半导体元件。

3. 发明申请

US20090212437A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20090212437A1
公开(公告)日：2009-08-27
申请号：US12389071
申请日：2009-02-19
申请人： Yukihiro Kumagai , Hiroyuki Ohta , Naotaka Tanaka , Masahiko Fujisawa , Akihiko Ohsaki
发明人： Yukihiro Kumagai , Hiroyuki Ohta , Naotaka Tanaka , Masahiko Fujisawa , Akihiko Ohsaki
IPC分类号： H01L23/532
CPC分类号： H01L23/53238 , H01L23/3128 , H01L23/53295 , H01L23/585 , H01L24/45 , H01L24/48 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/45124 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/73204 , H01L2924/00014 , H01L2924/01015 , H01L2924/12041 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00015 , H01L2924/00012 , H01L2224/0401
摘要： In a semiconductor device having a Low-k film as an interlayer insulator, peeling of the interlayer insulator in a thermal cycle test is prevented, thereby providing a highly reliable semiconductor device. In a semiconductor device having a structure in which interlayer insulators in which buried wires each having a main electric conductive layer made of copper are formed and cap insulators of the buried wires are stacked, the cap insulator having a relatively high Young's modulus and contacting by its upper surface with the interlayer insulator made of a Low-k film having a relatively low Young's modulus is formed so as not to be provided in an edge portion of the semiconductor device.
摘要翻译：在具有Low-k膜作为层间绝缘体的半导体器件中，防止了热循环试验中的层间绝缘体的剥离，从而提供高可靠性的半导体器件。在具有这样的结构的半导体器件中，其中形成有由铜制成的主导电层的埋入布线和层叠埋入导线的帽绝缘体的层间绝缘体，所述盖绝缘体具有较高的杨氏模量并且通过其接触形成具有相对低的杨氏模量的由Low-k膜制成的层间绝缘体的上表面，以便不设置在半导体器件的边缘部分中。

4. 发明授权

US07906848B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07906848B2
公开(公告)日：2011-03-15
申请号：US12389071
申请日：2009-02-19
申请人： Yukihiro Kumagai , Hiroyuki Ohta , Naotaka Tanaka , Masahiko Fujisawa , Akihiko Ohsaki
发明人： Yukihiro Kumagai , Hiroyuki Ohta , Naotaka Tanaka , Masahiko Fujisawa , Akihiko Ohsaki
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L23/53238 , H01L23/3128 , H01L23/53295 , H01L23/585 , H01L24/45 , H01L24/48 , H01L2224/16225 , H01L2224/16227 , H01L2224/32225 , H01L2224/45124 , H01L2224/45147 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/73204 , H01L2924/00014 , H01L2924/01015 , H01L2924/12041 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2924/00015 , H01L2924/00012 , H01L2224/0401
摘要： In a semiconductor device having a Low-k film as an interlayer insulator, peeling of the interlayer insulator in a thermal cycle test is prevented, thereby providing a highly reliable semiconductor device. In a semiconductor device having a structure in which interlayer insulators in which buried wires each having a main electric conductive layer made of copper are formed and cap insulators of the buried wires are stacked, the cap insulator having a relatively high Young's modulus and contacting by its upper surface with the interlayer insulator made of a Low-k film having a relatively low Young's modulus is formed so as not to be provided in an edge portion of the semiconductor device.
摘要翻译：在具有Low-k膜作为层间绝缘体的半导体器件中，防止了热循环试验中的层间绝缘体的剥离，从而提供高可靠性的半导体器件。在具有这样的结构的半导体器件中，其中形成有由铜制成的主导电层的埋入布线和层叠埋入导线的帽绝缘体的层间绝缘体，所述盖绝缘体具有较高的杨氏模量并且通过其接触形成具有相对低的杨氏模量的由Low-k膜制成的层间绝缘体的上表面，以便不设置在半导体器件的边缘部分中。

5. 发明授权

US09709377B2 Strain sensor chip mounting structure, strain sensor chip and method of manufacturing a strain sensor chip mounting structure 有权
公开(公告)号：US09709377B2
公开(公告)日：2017-07-18
申请号：US14396399
申请日：2012-04-23
申请人： Hiroyuki Ohta , Kisho Ashida
发明人： Hiroyuki Ohta , Kisho Ashida
IPC分类号： G01B7/16 , G01L1/00 , G01L1/18 , G01M5/00 , H01L21/78
CPC分类号： G01B7/18 , G01L1/18 , G01M5/0083 , H01L21/78 , H01L2224/32 , H01L2924/10158
摘要： Even when a strain sensor chip and an object to be measured are bonded to each other by using a metallic bonding material such as solder, the metallic bonding material shows the creep behavior when used under high temperature environment of, for example, 100° C. or higher, and therefore, the strain detected by the strain sensor chip is gradually reduced, and the strain is apparently reduced. In the strain sensor chip mounting structure which is one embodiment of the present application, a strain sensor chip is fixed onto a surface to be measured of the object to be measured via a metallic bonding material. And, the metallic bonding material is bonded to a metallic film that is formed on a side surface of the strain sensor chip. In this manner, temporal change in a measurement error can be suppressed.

6. 发明授权

US08278177B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08278177B2
公开(公告)日：2012-10-02
申请号：US13240303
申请日：2011-09-22
申请人： Yosuke Shimamune , Masahiro Fukuda , Young Suk Kim , Akira Katakami , Akiyoshi Hatada , Naoyoshi Tamura , Hiroyuki Ohta
发明人： Yosuke Shimamune , Masahiro Fukuda , Young Suk Kim , Akira Katakami , Akiyoshi Hatada , Naoyoshi Tamura , Hiroyuki Ohta
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/665 , H01L29/6653 , H01L29/6659 , H01L29/66636 , H01L29/7833
摘要： A first p-type SiGe mixed crystal layer is formed by an epitaxial growth method in a trench, and a second p-type SiGe mixed crystal layer is formed. On the second SiGe mixed crystal layer, a third p-type SiGe mixed crystal layer is formed. The height of an uppermost surface of the first SiGe mixed crystal layer from the bottom of the trench is lower than the depth of the trench with the surface of the silicon substrate being the standard. The height of an uppermost surface of the second SiGe mixed crystal layer from the bottom of the trench is higher than the depth of the trench with the surface of the silicon substrate being the standard. Ge concentrations in the first and third SiGe mixed crystal layers are lower than a Ge concentration in the second SiGe mixed crystal layer.
摘要翻译：在沟槽中通过外延生长法形成第一p型SiGe混晶层，形成第二p型SiGe混晶层。在第二SiGe混晶层上形成第三p型SiGe混晶层。从沟槽底部开始的第一SiGe混合晶体层的最上表面的高度低于沟槽的深度，硅衬底的表面是标准的。从沟槽底部开始的第二SiGe混合晶体层的最上表面的高度高于沟槽的深度，硅衬底的表面是标准的。第一和第三SiGe混晶层中的Ge浓度低于第二SiGe混晶层中的Ge浓度。

7. 发明授权

US08183681B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US08183681B2
公开(公告)日：2012-05-22
申请号：US12493502
申请日：2009-06-29
申请人： Shinji Hiramitsu , Hiroyuki Ohta , Koji Sasaki , Masato Nakamura , Osamu Ikeda , Satoshi Matsuyoshi
发明人： Shinji Hiramitsu , Hiroyuki Ohta , Koji Sasaki , Masato Nakamura , Osamu Ikeda , Satoshi Matsuyoshi
IPC分类号： H01L23/48
CPC分类号： H01L23/051 , H01L23/24 , H01L2224/33181
摘要： A semiconductor device which includes a semiconductor chip; an electrically conductive base electrode bonded to the lower surface of the chip by a first bonding member; an electrically conductive lead electrode bonded to the upper surface of the chip by a second bonding member; and a first stress relief member for reducing stress developed in the first bonding member due to the difference in thermal expansion between the chip and the base electrode. Both the base electrode and the first stress relief member are in direct contact with the lower surface of the first bonding member. A protrusion is formed upstanding from the base electrode in direct contact with the first bonding member, and the first stress relief member surrounds a circumferential portion of the protrusion.
摘要翻译：一种半导体器件，包括半导体芯片; 通过第一接合部件接合到所述芯片的下表面的导电基极; 通过第二接合部件将芯片的上表面接合的导电性引线电极; 以及由于芯片和基极之间的热膨胀差异，用于减小在第一接合部件中产生的应力的第一应力消除部件。基极和第一应力消除构件都与第一接合构件的下表面直接接触。从与第一接合构件直接接触的基极形成突起，并且第一应力消除构件围绕突起的周向部分。

8. 发明申请

US20110259112A1 Mechanical-Quantity Measuring Device 有权
标题翻译：机械量测量装置
公开(公告)号：US20110259112A1
公开(公告)日：2011-10-27
申请号：US13177185
申请日：2011-07-06
申请人： Hiromi Shimazu , Hiroyuki Ohta , Yohei Tanno
发明人： Hiromi Shimazu , Hiroyuki Ohta , Yohei Tanno
IPC分类号： G01B7/16
CPC分类号： G01L1/2293 , G01B7/18 , G01L1/18
摘要： A mechanical-quantity measuring device capable of measuring a strain component in a specific direction with high precision is provided.At least two or more pairs of bridge circuits are formed inside a semiconductor monocrystal substrate and a semiconductor chip, and one of these bridge circuits forms a n-type diffusion resistor in which a direction of a current flow and measuring variation of a resistor value are in parallel with a direction of the semiconductor monocryastal silicon substrate, and an another bridge circuit is composed of combination of p-type diffusion resistors in parallel with a direction.
摘要翻译：提供能够高精度地测量特定方向的应变分量的机械量测量装置。在半导体单晶基板和半导体芯片的内部形成有至少两对以上的桥式电路，并且这些桥式电路之一形成n型扩散电阻器，其中电流方向和电阻值的测量变化为与半导体单晶硅基板的<100>方向并联，另一桥接电路由与<110>方向并联的p型扩散电阻器的组合构成。

9. 发明授权

US07663187B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07663187B2
公开(公告)日：2010-02-16
申请号：US11984738
申请日：2007-11-21
申请人： Takashi Saiki , Hiroyuki Ohta , Hiroyuki Kanata
发明人： Takashi Saiki , Hiroyuki Ohta , Hiroyuki Kanata
IPC分类号： H01L29/76 , H01L29/94
CPC分类号： H01L29/6659 , H01L21/823807 , H01L21/823814 , H01L21/823864 , H01L29/665 , H01L29/6656 , H01L29/7833
摘要： An extension region is formed by ion implantation under masking by a gate electrode, and then a substance having a diffusion suppressive function over an impurity contained in a source-and-drain is implanted under masking by the gate electrode and a first sidewall spacer so as to form amorphous layers a semiconductor substrate within a surficial layer thereof and in alignment with the first sidewall spacer, to thereby form an amorphous diffusion suppressive region.
摘要翻译：通过栅极电极掩蔽下的离子注入形成延伸区域，然后在栅极电极和第一侧壁间隔物的掩蔽下注入在源极和漏极中包含的杂质上具有扩散抑制功能的物质，以便在其表面层内形成半导体衬底并与第一侧壁间隔物对齐，从而形成非晶扩散抑制区域。

10. 发明授权

US07601996B2 Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07601996B2
公开(公告)日：2009-10-13
申请号：US11438684
申请日：2006-05-23
申请人： Hiroyuki Ohta , Kenichi Okabe
发明人： Hiroyuki Ohta , Kenichi Okabe
IPC分类号： H01L29/76
CPC分类号： H01L21/26506 , H01L21/26586 , H01L29/1083 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833
摘要： A semiconductor device comprises a field-effect transistor arranged in a semiconductor substrate, which transistor has a gate electrode, source/drain impurity diffusion regions, and carbon layers surrounding the source/drain impurity diffusion regions. Each of the carbon layers is provided at an associated of the source/drain impurity diffusion regions and positioned so as to be offset from the front edge of a source/drain extension in direction away from the gate electrode and to surround as profile the associated source/drain impurity diffusion region.
摘要翻译：半导体器件包括布置在半导体衬底中的场效应晶体管，该晶体管具有栅电极，源/漏杂质扩散区和围绕源极/漏极杂质扩散区的碳层。每个碳层设置在源极/漏极杂质扩散区域的相关联处，并且被定位成从远离栅电极的方向偏离源极/漏极延伸部的前边缘，并且作为轮廓围绕相关源 /漏杂质扩散区域。

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