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1. 发明授权

US06822339B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06822339B2
公开(公告)日：2004-11-23
申请号：US10167573
申请日：2002-06-13
申请人： Shigeki Kageyama
发明人： Shigeki Kageyama
IPC分类号： H01L2328
CPC分类号： H05K3/1225 , H01L21/4867 , H01L23/13 , H01L23/24 , H01L24/48 , H01L2224/05599 , H01L2224/32225 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/85399 , H01L2924/00014 , H01L2924/01004 , H01L2924/01078 , H01L2924/14 , H01L2924/1423 , H01L2924/15153 , H01L2924/1517 , H01L2924/16152 , H01L2924/181 , H01L2924/19105 , H01L2924/3025 , H05K1/183 , H05K3/284 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor device includes a multiplayer substrate with a cavity, a semiconductor chip in the cavity, wiring lines with lands, a cover of a material, covering the semiconductor chip and having a protruding part, and chips bonded to the wirings lines with a solder having a low melting point. The protruding part has a height from the surface of the multiplayer substrate greater than the thickness of the wiring layer.
摘要翻译：一种半导体器件包括具有空腔的多层基板，空腔中的半导体芯片，具有焊盘的布线，覆盖半导体芯片并具有突出部分的材料盖，以及具有焊料的芯片，焊料具有低熔点。突出部具有比多层基板的表面高于布线层的厚度的高度。

2. 发明授权

US06797543B2 Process for manufacturing IC card 失效
标题翻译： IC卡制造工艺
公开(公告)号：US06797543B2
公开(公告)日：2004-09-28
申请号：US10610526
申请日：2003-07-02
申请人： Tetsuichiro Kasahara , Hirokazu Tsukioka , Shintaro Hayashi
发明人： Tetsuichiro Kasahara , Hirokazu Tsukioka , Shintaro Hayashi
IPC分类号： H01L2328
CPC分类号： G06K19/07779 , G06K19/07749 , G06K19/07783 , H01L2224/48091 , H01L2224/48472 , H05K1/0393 , H05K1/165 , H05K3/0052 , H05K3/202 , H05K3/281 , H05K2201/10424 , H01L2924/00014 , H01L2924/00
摘要： A process for manufacturing an IC card includes a step of forming a plane coil by etching or punching a thin metal plate so that the plane coil consists of a conductor line wound as several loops in substantially the same plane and has respective terminals. A semiconductor element having electrodes is mounted on the plane coil. An adhesive agent or tape is attached to a predetermined area of the plane coil so that adjacent conductor lines in the loops are kept a predetermined gap therebetween. The plane coil is disposed between a pair of films to cover the plane coil therebetween, one of the films being provided with adhesive layer on a surface facing to the other film to seal the plane coil with the semiconductor element by attaching the pair of films with respect to each other by means of the adhesive layer.
摘要翻译： IC卡的制造方法包括通过蚀刻或冲压薄金属板来形成平面线圈的步骤，使得平面线圈由在大体上相同的平面上缠绕成几个环的导体线组成并且具有各自的端子。具有电极的半导体元件安装在平面线圈上。粘合剂或胶带附着到平面线圈的预定区域，使得环中的相邻导体线保持在其间的预定间隙。平面线圈设置在一对薄膜之间以覆盖它们之间的平面线圈，其中一个膜在面向另一个薄膜的表面上设置有粘合剂层，以通过将该对薄膜与通过粘合剂层彼此相对。

3. 发明授权

US06791199B2 Heat radiating semiconductor device 失效
标题翻译：散热半导体器件
公开(公告)号：US06791199B2
公开(公告)日：2004-09-14
申请号：US09810104
申请日：2001-03-16
申请人： Noriaki Sakamoto , Yoshiyuki Kobayashi , Junji Sakamoto , Yukio Okada , Yusuke Igarashi , Eiju Maehara , Kouji Takahashi
发明人： Noriaki Sakamoto , Yoshiyuki Kobayashi , Junji Sakamoto , Yukio Okada , Yusuke Igarashi , Eiju Maehara , Kouji Takahashi
IPC分类号： H01L2328
CPC分类号： H01L21/4832 , H01L21/56 , H01L23/3121 , H01L23/3135 , H01L24/97 , H01L2221/68377 , H01L2224/05571 , H01L2224/05573 , H01L2224/16 , H01L2224/73204 , H01L2224/97 , H01L2924/01046 , H01L2924/01079 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/15787 , H01L2924/351 , H01L2224/81 , H01L2924/00
摘要： AS conductive patterns 11A to 11D are formed burying in a insulating resin 10 and a conductive foil 20 is formed being half-etched, thickness of the device is made thin. As an electrode for radiation 11D is provided, a semiconductor device superior in radiation is provided. Thickness of an electric connection means SD is substantially made definite as the electric connection means SD does not flow to a conductive path 11B by using a flow-prevention film DM.
摘要翻译：形成埋入绝缘树脂10中的导电图形11A至11D，并且半导体形成导电箔20，使该器件的厚度变薄。作为辐射用电极11D，提供了辐射优异的半导体器件。电连接装置SD的厚度基本上是确定的，因为电连接装置SD通过使用防流膜DM不流到导电路径11B。

4. 发明授权

US06787905B1 Electric semiconductor element with a contact hole 失效
标题翻译：具有接触孔的电气半导体元件
公开(公告)号：US06787905B1
公开(公告)日：2004-09-07
申请号：US10030617
申请日：2002-07-25
申请人： Alfred Goerlach , Marion Gebhard
发明人： Alfred Goerlach , Marion Gebhard
IPC分类号： H01L2328
CPC分类号： H01L29/045 , H01L21/76816
摘要： An electric semiconductor component includes a monocrystalline semiconductor substrate made of silicon, for example, an insulation layer arranged on the surface of the semiconductor substrate and penetrated by a contact hole in at least one location and a contact element that contacts the semiconductor substrate through the contact hole and is made of a material in which the semiconductor material of the substrate is soluble in an anisotropic dissolving process. The edges of the contact hole are configured as diffusion stop structures.
摘要翻译：电半导体部件包括由硅制成的单晶半导体衬底，例如，设置在半导体衬底的表面上并被至少一个位置的接触孔穿透的绝缘层和通过触点接触半导体衬底的接触元件并且由其中基板的半导体材料可溶于各向异性溶解工艺的材料制成。接触孔的边缘被配置为扩散停止结构。

5. 发明授权

US06734531B2 Use of selective oxidation conditions for dielectric conditioning 失效
标题翻译：使用选择性氧化条件进行电介质调理
公开(公告)号：US06734531B2
公开(公告)日：2004-05-11
申请号：US10391266
申请日：2003-03-18
申请人： Ronald A. Weimer , Don Carl Powell
发明人： Ronald A. Weimer , Don Carl Powell
IPC分类号： H01L2328
CPC分类号： H01L28/91 , H01L21/3105 , Y10S438/958
摘要： A method for conditioning or repairing a dielectric structure of a semiconductor device structure with selectivity over an adjacent conductive or semiconductive structure of the semiconductor device structure, such as a capacitor dielectric and an adjacent bottom electrode of the capacitor. The method includes exposing the dielectric structure and at least an adjacent surface of the conductive or semiconductive structure to an oxidizing atmosphere that includes at least one oxidant and hydrogen species. The at least one hydrogen species adsorbs to a surface of the conductive or semiconductive structure so as to substantially prevent passage of the at least one oxidant into or through the conductive or semiconductive structure. The oxidant oxidizes or repairs voids or other defects that may be present in the dielectric structure. Semiconductor device structures fabricated by employing the method are also disclosed.
摘要翻译：用于调节或修复半导体器件结构的电介质结构的方法，其具有对半导体器件结构的相邻导电或半导体结构（诸如电容器电介质和电容器的相邻底部电极）的相邻导电或半导体结构的选择性。该方法包括将导电或半导体结构的介电结构和至少相邻表面暴露于包括至少一种氧化剂和氢物质的氧化气氛。所述至少一种氢物质吸附到导电或半导体结构的表面，以便基本上防止至少一种氧化剂进入导电或半导体结构中。氧化剂氧化或修复可能存在于电介质结构中的空隙或其它缺陷。还公开了通过采用该方法制造的半导体器件结构。

6. 发明授权

US06713882B2 Resin sealing apparatus and resin sealing method 失效
标题翻译：树脂密封装置和树脂密封方法
公开(公告)号：US06713882B2
公开(公告)日：2004-03-30
申请号：US10091303
申请日：2002-03-06
申请人： Naoya Yasuda
发明人： Naoya Yasuda
IPC分类号： H01L2328
CPC分类号： H01L21/565 , H01L2924/0002 , H01L2924/00
摘要： The resin sealing apparatus includes a mold that has a main cavity into which a portion of a semiconductor device to be sealed with a resin is disposed. Furthermore, an external-shape regulating member is detachably accommodated in the main cavity of the mold to form a new cavity inside the main cavity.
摘要翻译：树脂密封装置包括具有主空腔的模具，其中设置有用树脂密封的半导体器件的一部分。此外，外形调节构件可拆卸地容纳在模具的主腔中，以在主腔内形成新的空腔。

7. 发明授权

US06713677B2 Housing assembly for an electronic device and method of packaging an electronic device 失效
标题翻译：一种用于电子设备的外壳组件和一种电子设备的封装方法
公开(公告)号：US06713677B2
公开(公告)日：2004-03-30
申请号：US10260469
申请日：2002-09-30
申请人： Reinhard Fischbach , Manfred Fries , Manfred Zaeske
发明人： Reinhard Fischbach , Manfred Fries , Manfred Zaeske
IPC分类号： H01L2328
CPC分类号： H01L21/563 , H01L2224/48472 , H01L2224/73203 , H01L2924/01068 , H01L2924/01078 , H01L2924/01079 , H01L2924/15151
摘要： A housing assembly forms a package for an electronic device. The housing assembly has the electronic device, an external carrier and a housing frame. A capillary-acting epoxy resin is filled into the assembled housing assembly via a filling-in opening and, on account of its capillary action, closes the interspaces between the semiconductor chip and the housing frame.
摘要翻译：壳体组件形成用于电子设备的包装。壳体组件具有电子装置，外部载体和壳体框架。经毛细管作用的环氧树脂通过填充开口填充到组装的壳体组件中，并且由于其毛细作用，封闭半导体芯片和壳体框架之间的间隙。

8. 发明授权

US06664649B2 Lead-on-chip type of semiconductor package with embedded heat sink 失效
标题翻译：具有嵌入式散热器的片上半导体封装
公开(公告)号：US06664649B2
公开(公告)日：2003-12-16
申请号：US09796164
申请日：2001-02-28
申请人： Chien-Ping Huang
发明人： Chien-Ping Huang
IPC分类号： H01L2328
CPC分类号： H01L24/32 , H01L23/4334 , H01L23/4951 , H01L24/45 , H01L24/48 , H01L2224/32014 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/14 , H05K1/0203 , H05K3/341 , H01L2224/05599
摘要： A lead-on-chip type of semiconductor package with an embedded heat sink is constructed on a leadframe including an outer-lead portion, an inner-lead portion, and a downset bond-finger portion. A semiconductor chip is arranged on a back side of the inner-lead portion, with its active surface being attached to the downset bond-finger portion. Then, a plurality of bonding wires are bonded between I/O pads of the chip and the downset bond-finger portion. Further, a heat sink is adhered to a front side of the inner-lead portion by an electrically-insulative and thermally-conductive adhesive material. Finally, an encapsulation body is formed to encapsulate the chip, the inner-lead portion of the leadframe, the bonding wires, and the heat sink. Owing to the embedded heat sink configuration, it allows the packaged chip to have good heat-dissipation efficiency during operation and also allows the overall package body to be made very compact in size.
摘要翻译：具有嵌入式散热器的芯片内片式半导体封装被构造在引线框架上，该引线框架包括外部引线部分，内部引线部分和下降接合指状部分。半导体芯片布置在内引线部分的后侧，其有源表面附接到下端接合指状部分。然后，多个接合线接合在芯片的I / O焊盘和下端接合指部之间。此外，通过电绝缘导热粘合剂材料将散热片粘附到内引线部分的前侧。最后，形成封装本体以封装芯片，引线框的内引线部分，接合线和散热片。由于嵌入式散热器配置，它允许封装芯片在操作期间具有良好的散热效率，并且还允许整体封装体的尺寸非常紧凑。

9. 发明授权

US06541701B1 Containment fence apparatus and potting method 有权
标题翻译：遏制围栏装置和灌封方法
公开(公告)号：US06541701B1
公开(公告)日：2003-04-01
申请号：US09608932
申请日：2000-06-30
申请人： Robert Loose , Scott Eastman
发明人： Robert Loose , Scott Eastman
IPC分类号： H01L2328
CPC分类号： H05K5/064 , H05K3/284 , H05K7/205
摘要： A fluid containment fence apparatus provides a border around the perimeter of an area to be potted on one or both sides of the board. First, or first and second and second (top and bottom), containment walls are secured in place using interlocking elements integral to the walls such that no external fasteners are needed. The interlocking elements permit snug adhesion of the fence to the board even when the board has variations in thickness. The interlocking elements extend through and interlock through engagement with another fence or the board. The size of the holes is minimized. As a result, a minimum amount of board space is occupied by the fence, and the overall size of the board is maintained. A potting fluid containment fence for a board having components to be encased in a potting fluid includes a first wall. The components to be encased are arranged on an upper face of the board, at least. The first wall has segments that form a closed first polygon and a protrusion for engaging a corresponding hole on the upper face of the board. The protrusion is on a lower face of the first wall. The first wall is formed of material which is rigid before the protrusion is engaged in the corresponding hole.
摘要翻译：流体容纳围栏装置围绕要在板的一侧或两侧上封装的区域的周边提供边界。首先，或第一和第二和第二（顶部和底部），安全壳使用与墙壁成一体的互锁元件固定就位，使得不需要外部紧固件。互锁元件即使当板的厚度变化时，也可以将栅栏紧贴到板上。互锁元件通过与另一个围栏或板的接合而延伸通过并互锁。孔的尺寸最小化。因此，栅栏占用最少的电路板空间，并保持电路板的整体尺寸。用于板的灌封液容纳挡板包括第一壁，所述挡板包含封装在灌封液中的部件。待封装的部件至少布置在板的上表面上。第一壁具有形成封闭的第一多边形的段和用于接合板的上表面上的相应孔的突起。突起位于第一壁的下表面上。第一壁由突出物接合在相应的孔中之前刚性的材料形成。

10. 发明授权

US06531763B1 Interposers having encapsulant fill control features 有权
标题翻译：具有密封剂填充控制特征的插件
公开(公告)号：US06531763B1
公开(公告)日：2003-03-11
申请号：US09639395
申请日：2000-08-15
申请人： Todd O. Bolken , David J. Corisis
发明人： Todd O. Bolken , David J. Corisis
IPC分类号： H01L2328
CPC分类号： H01L21/56 , H01L23/16 , H01L24/48 , H01L2224/05599 , H01L2224/45099 , H01L2224/48091 , H01L2224/4824 , H01L2224/85399 , H01L2924/00014 , H01L2924/01322 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： Interposers having an encapsulant fill control feature are disclosed. In one embodiment, an interposer includes a substrate having a first surface proximate the semiconductor component, and a fill control feature projecting from the first surface toward a region adapted to be occupied by a semiconductor component. The fill control feature is positioned between the region and the substrate and is sized to at least partially block an opening between a semiconductor component that may be positioned in the region and the first surface. As an encapsulant material is flowed about the semiconductor component, the fill control feature at least partially blocks the encapsulant material from entering the opening. The encapsulant material may then substantially surround the semiconductor component, after which the encapsulant material may substantially fill a space between the semiconductor component and the interposer.
摘要翻译：公开了具有密封剂填充控制特征的插入件。在一个实施例中，插入器包括具有靠近半导体部件的第一表面的衬底以及从第一表面向适于被半导体部件占据的区域突出的填充控制特征。填充控制特征位于区域和基底之间，其尺寸设计成至少部分地阻挡可位于该区域中的半导体部件与第一表面之间的开口。当密封剂材料围绕半导体部件流动时，填充控制特征至少部分地阻挡密封剂材料进入开口。密封剂材料然后可以基本上围绕半导体部件，此后，密封剂材料可以基本上填充半导体部件和插入件之间的空间。

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