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51. 发明授权

US06642573B1 Use of high-K dielectric material in modified ONO structure for semiconductor devices 有权
标题翻译：在改性ONO结构中使用高K介电材料用于半导体器件
公开(公告)号：US06642573B1
公开(公告)日：2003-11-04
申请号：US10097912
申请日：2002-03-13
申请人： Arvind Halliyal , Mark T. Ramsbey , Wei Zhang , Mark W. Randolph , Fred T. K. Cheung
发明人： Arvind Halliyal , Mark T. Ramsbey , Wei Zhang , Mark W. Randolph , Fred T. K. Cheung
IPC分类号： H01L29788
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L21/28211 , H01L21/28273 , H01L21/28282 , H01L21/3143 , H01L21/3144 , H01L21/31604 , H01L21/31691 , H01L21/3185 , H01L28/56 , H01L29/513 , H01L29/516 , H01L29/517 , H01L29/518 , Y10S438/954
摘要： A process for fabrication of a semiconductor device including a modified ONO structure, comprising forming the modified ONO structure by providing a semiconductor substrate; forming a first dielectric material layer on the semiconductor substrate; depositing a silicon nitride layer on the first dielectric material layer; and forming a top dielectric material layer, wherein at least one of the bottom dielectric material layer and the top dielectric material layer comprise a mid-K or a high-K dielectric material. The semiconductor device may be, e.g., a SONOS two-bit EEPROM device or a floating gate flash device including the modified ONO structure.
摘要翻译：一种制造包括修饰的ONO结构的半导体器件的方法，包括通过提供半导体衬底形成修饰的ONO结构; 在所述半导体衬底上形成第一介电材料层; 在第一介电材料层上沉积氮化硅层; 以及形成顶部介电材料层，其中所述底部电介质材料层和所述顶部电介质材料层中的至少一个包括中间K或高K电介质材料。半导体器件可以是例如SONOS两位EEPROM器件或包括修改的ONO结构的浮动栅极闪存器件。

52. 发明授权

US06639271B1 Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same 失效
标题翻译：用于双位氮化物存储器件的完全隔离的介电存储器单元结构及其制造方法
公开(公告)号：US06639271B1
公开(公告)日：2003-10-28
申请号：US10027253
申请日：2001-12-20
申请人： Wei Zheng , Mark W. Randolph , Nicholas H. Tripsas , Zoran Krivokapic , Jack F. Thomas , Mark T. Ramsbey
发明人： Wei Zheng , Mark W. Randolph , Nicholas H. Tripsas , Zoran Krivokapic , Jack F. Thomas , Mark T. Ramsbey
IPC分类号： H01L29792
CPC分类号： H01L21/28194 , H01L21/28202 , H01L21/28282 , H01L29/512 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/7923
摘要： A method of fabricating a dual bit dielectric memory cell structure on a silicon substrate includes implanting buried bit lines within the substrate and fabricating a layered island on the surface of the substrate between the buried bit lines. The island has a perimeter defining a gate region, and comprises a tunnel dielectric layer on the surface of the silicon on insulator wafer, an isolation barrier dielectric layer on the surface of the tunnel dielectric layer, a top dielectric layer on the surface of the isolation barrier dielectric layer, and a polysilicon gate on the surface of the top dielectric layer. A portion of the isolation barrier dielectric layer is removed to form an undercut region within the gate region and a charge trapping material is deposited within the undercut region.
摘要翻译：在硅衬底上制造双位电介质存储单元结构的方法包括在衬底内埋入掩埋位线，并在掩埋位线之间的衬底表面上制造分层岛。该岛具有限定栅极区域的周边，并且包括在绝缘体上硅晶片的表面上的隧道介电层，在隧道介电层的表面上的隔离阻挡介电层，隔离表面上的顶部介电层势垒介电层，以及在顶部介电层的表面上的多晶硅栅极。去除隔离势垒介电层的一部分以在栅极区内形成底切区域，并且电荷俘获材料沉积在底切区域内。

53. 发明授权

US06589841B1 Charge gain/charge loss junction leakage prevention for flash technology by using double isolation/capping layer between lightly doped drain and gate 失效
公开(公告)号：US06589841B1
公开(公告)日：2003-07-08
申请号：US10180772
申请日：2002-06-25
申请人： Tuan Duc Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui
发明人： Tuan Duc Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui
IPC分类号： H01L29788
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11543
摘要： An improved flash memory device having core stacks and periphery stacks which are protected by first and second thin side walls, side spacers over the side walls, and an HTO layer over the stacks, and side spacer. The flash memory device has an intermetallic dielectric layer placed over the HTO layer. A tungsten plug is placed in the intermetallic dielectric layer to provide an electrical connection to the drain of the flash memory device. The additional first and second side walls reduce current leakage between core stacks and the tungsten plug and help to protect the stacks during fabrication.

54. 发明授权

US06573151B1 Method of forming zero marks 有权
标题翻译：形成零标记的方法
公开(公告)号：US06573151B1
公开(公告)日：2003-06-03
申请号：US09884204
申请日：2001-06-19
申请人： Mark T. Ramsbey , Terence C. Tong
发明人： Mark T. Ramsbey , Terence C. Tong
IPC分类号： H01L2176
CPC分类号： G03F9/7076 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： A method for making a semiconductor structure, includes patterning a photoresist layer to form both a zero marks pattern and a well implant mask pattern. The photoresist layer is on a region of a substrate.
摘要翻译：一种制造半导体结构的方法，包括图案化光致抗蚀剂层以形成零标记图案和阱注入掩模图案。光致抗蚀剂层位于基板的区域上。

55. 发明授权

US06479348B1 Method of making memory wordline hard mask extension 有权
标题翻译：制作内存字线硬掩模扩展的方法
公开(公告)号：US06479348B1
公开(公告)日：2002-11-12
申请号：US10109516
申请日：2002-08-27
申请人： Tazrien Kamal , Minh Van Ngo , Mark T. Ramsbey , Jeffrey Shields , Jean Y. Yang , Emmanuil Lingunis , Hidehiko Shiraiwa , Angela T. Hui
发明人： Tazrien Kamal , Minh Van Ngo , Mark T. Ramsbey , Jeffrey Shields , Jean Y. Yang , Emmanuil Lingunis , Hidehiko Shiraiwa , Angela T. Hui
IPC分类号： H01L218247
CPC分类号： H01L27/11568 , H01L27/115
摘要： A manufacturing method is provided for an integrated circuit memory with closely spaced wordlines formed by using hard mask extensions. A charge-trapping dielectric material is deposited over a semiconductor substrate and first and second bitlines are formed therein. A wordline material and a hard mask material are deposited over the wordline material. A photoresist material is deposited over the hard mask material and is processed to form a patterned photoresist material. The hard mask material is processed using the patterned photoresist material to form a patterned hard mask material. The patterned photoresist is then removed. A hard mask extension material is deposited over the wordline material and is processed to form a hard mask extension. The wordline material is processed using the patterned hard mask material and the hard mask extension to form a wordline, and the patterned hard mask material and the hard mask extension are then removed.
摘要翻译：提供了一种用于通过使用硬掩模延伸部形成的具有紧密间隔的字线的集成电路存储器的制造方法。在半导体衬底上沉积电荷俘获电介质材料，并在其中形成第一和第二位线。字线材料和硬掩模材料沉积在字线材料上。光致抗蚀剂材料沉积在硬掩模材料上并被处理以形成图案化的光致抗蚀剂材料。使用图案化的光致抗蚀剂材料处理硬掩模材料以形成图案化的硬掩模材料。然后去除图案化的光致抗蚀剂。硬掩模延伸材料沉积在字线材料上并被处理以形成硬掩模延伸部。使用图案化的硬掩模材料和硬掩模延伸部来处理字线材料以形成字线，然后去除图案化的硬掩模材料和硬掩模延伸部。

56. 发明授权

US06465303B1 Method of manufacturing spacer etch mask for silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile memory 有权
标题翻译：制造用于氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）型非易失性存储器的间隔物蚀刻掩模的方法
公开(公告)号：US06465303B1
公开(公告)日：2002-10-15
申请号：US09885490
申请日：2001-06-20
申请人： Mark T. Ramsbey , Narbeh Derhacobian , Janet Wang , Angela Hui , Tuan Pham , Ravi Sunkavalli , Mark Randolph
发明人： Mark T. Ramsbey , Narbeh Derhacobian , Janet Wang , Angela Hui , Tuan Pham , Ravi Sunkavalli , Mark Randolph
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11573
摘要： One aspect of the present invention relates to a method of forming spacers in a silicon-oxide-nitride-oxide-silicon (SONOS) type nonvolatile semiconductor memory device, involving the steps of providing a semiconductor substrate having a core region and periphery region, the core region containing SONOS type memory cells and the periphery region containing gate transistors; implanting a first implant into the core region and a first implant into the periphery region of the semiconductor substrate; forming a spacer material over the semiconductor substrate; masking the core region and forming spacers adjacent the gate transistors in the periphery region; and implanting a second implant into the periphery region of the semiconductor substrate.
摘要翻译：本发明的一个方面涉及一种在氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）型非易失性半导体存储器件中形成间隔物的方法，包括以下步骤：提供具有核心区域和外围区域的半导体衬底，包含SONOS型存储单元的核心区域和包含栅极晶体管的外围区域; 将第一注入植入到所述芯区域中，并将第一注入植入所述半导体衬底的周边区域; 在所述半导体衬底上形成隔离材料; 掩蔽所述芯区域并在所述周边区域中形成与所述栅极晶体管相邻的间隔物; 以及将第二植入物植入所述半导体衬底的周边区域。

57. 发明授权

US06291296B1 Method for removing anti-reflective coating layer using plasma etch process before contact CMP 有权
标题翻译：在接触CMP之前使用等离子体蚀刻工艺去除抗反射涂层的方法
公开(公告)号：US06291296B1
公开(公告)日：2001-09-18
申请号：US09416382
申请日：1999-10-12
申请人： Angela T. Hui , Wenge Yang , Kashmir Sahota , Mark T. Ramsbey , Suzette K. Pangrle , Minh Van Ngo
发明人： Angela T. Hui , Wenge Yang , Kashmir Sahota , Mark T. Ramsbey , Suzette K. Pangrle , Minh Van Ngo
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L27/115 , Y10S438/951
摘要： The present invention provides a method for selectively removing anti-reflective coating (ARC) from the surface of an dielectric layer over the surface of a substrate without scratching the dielectric layer and/or tungsten contacts formed therein. In one embodiment, a fluoromethane (CH3F)/oxygen (O2) etch chemistry is used to selectively remove the ARC layer without scratching and/or degradation of the dielectric layer, source/drain regions formed over the substrate, and a silicide layer formed atop stacked gate structures. The CH3F/O2 etch chemistry etches the ARC layer at a rate which is significantly faster than the etch rates of the dielectric layer, the source/drain regions and the silicide layer. In addition, by removing the ARC layer prior to the formation of tungsten contacts by filling of contact openings formed in the dielectric layer with tungsten, potential scratching of tungsten contacts due to ARC layer removal is eliminated.
摘要翻译：本发明提供了一种从基板表面上的电介质层的表面选择性去除抗反射涂层（ARC）的方法，而不会刮擦形成在其中的电介质层和/或钨触点。在一个实施方案中，使用氟甲烷（CH 3 F）/氧（O 2）蚀刻化学物质来选择性地除去ARC层，而不会在电介质层，形成在衬底上的源极/漏极区域的划伤和/或降解，以及形成在顶部的硅化物层堆叠门结构。 CH3F / O2蚀刻化学以比介电层，源/漏区和硅化物层的蚀刻速率明显更快的速率蚀刻ARC层。此外，通过在形成钨触点之前，通过用钨填充形成在电介质层中的接触开口来去除ARC层，消除了由于ARC层去除引起的钨触点的潜在划痕。

58. 发明授权

US6136510A Doubled-sided wafer scrubbing for improved photolithography 失效
标题翻译：双面晶圆洗涤，用于改进光刻
公开(公告)号：US6136510A
公开(公告)日：2000-10-24
申请号：US800940
申请日：1997-02-13
申请人： Tho Le La , Subramanian N. Venkatkrishnan , Mark T. Ramsbey , Jack F. Thomas , Kathleen Regina Early
发明人： Tho Le La , Subramanian N. Venkatkrishnan , Mark T. Ramsbey , Jack F. Thomas , Kathleen Regina Early
IPC分类号： G03F7/16 , H01L21/306 , G03F7/00
CPC分类号： G03F7/16 , H01L21/02063
摘要： The accuracy of photolithographic processing, particularly in forming small diameter through holes and/or trenches in a dielectric layer, is improved by double-sided scrubbing the wafer prior to photolithography. It was found that particles adhering to the wafer backside resulting from prior processing steps cause inaccurate photolithographic processing, particularly at a submicron level. Double-sided wafer scrubbing removes such adhering particles, thereby improving photolithographic accuracy.
摘要翻译：通过在光刻之前双面擦洗晶片来改善光刻处理的精度，特别是在形成介电层中的小直径通孔和/或沟槽中的精度。发现由先前处理步骤导致的粘附到晶片背面的颗粒导致不精确的光刻处理，特别是在亚微米级。双面晶圆洗涤除去这些粘附颗粒，从而提高光刻精度。

59. 发明授权

US6030868A Elimination of oxynitride (ONO) etch residue and polysilicon stringers through isolation of floating gates on adjacent bitlines by polysilicon oxidation 失效
标题翻译：通过多晶硅氧化隔离相邻位线上的浮栅，消除氧氮化物（ONO）蚀刻残渣和多晶硅桁架
公开(公告)号：US6030868A
公开(公告)日：2000-02-29
申请号：US33916
申请日：1998-03-03
申请人： Kathleen R. Early , Michael K. Templeton , Nicholas H. Tripsas , Maria C. Chan , Mark T. Ramsbey
发明人： Kathleen R. Early , Michael K. Templeton , Nicholas H. Tripsas , Maria C. Chan , Mark T. Ramsbey
IPC分类号： H01L21/8247 , H01L27/115 , H01L21/336
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method for fabricating a first memory cell and a second memory cell having floating gates electrically isolated from each other. A first polysilicon (poly I) layer is formed on an oxide coated substrate, portions of the poly I layer to serve as future floating gates for the first and second memory cells. An interpoly dielectric layer is formed over the poly I layer. At least a portion of the interpoly dielectric layer is etched to expose at least a portion of the poly I layer so as to pattern the floating gates on either side of the exposed portion of the poly I layer. The exposed portion of the poly I layer is transformed into an insulator via thermal oxidation such that the insulator electrically isolates a floating gate of the first memory cell from a floating gate of the second memory cell. A second polysilicon (poly II) layer is formed substantially free of abrupt changes in step height.
摘要翻译：一种制造第一存储单元的方法和具有彼此电隔离的浮动栅极的第二存储单元。在氧化物涂覆的基底上形成第一多晶硅（poly I）层，多晶硅层的部分用作第一和第二存储单元的未来浮动栅极。在多晶硅层上形成多层介电层。蚀刻至少一部分互电介质层以暴露多晶硅层的至少一部分，以便在多晶硅层的暴露部分的任一侧上对浮动栅极进行图案化。多层I的暴露部分通过热氧化转变为绝缘体，使得绝缘体将第一存储器单元的浮动栅极与第二存储单元的浮置栅极电隔离。形成基本上没有台阶高度突然变化的第二多晶硅（poly II）层。

60. 发明授权

US08691647B1 Memory devices containing a high-K dielectric layer 有权
标题翻译：包含高K电介质层的存储器件
公开(公告)号：US08691647B1
公开(公告)日：2014-04-08
申请号：US10927692
申请日：2004-08-27
申请人： Wei Zheng , Arvind Halliyal , Mark T. Ramsbey , Jack F. Thomas
发明人： Wei Zheng , Arvind Halliyal , Mark T. Ramsbey , Jack F. Thomas
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , H01L21/28282 , H01L29/513 , H01L29/517 , H01L29/7881
摘要： In one embodiment, a semiconductor device is disclosed. The semiconductor device is formed on a semiconductor substrate having an active region, the semiconductor device comprising: a gate dielectric layer disposed on the semiconductor substrate, the gate dielectric layer having at least two sub-layers with at least one sub-layer having a dielectric constant greater than SiO2; a floating gate formed on the gate dielectric layer defining a channel interposed between a source and a drain formed within the active region of the semiconductor substrate; a control gate formed above the floating gate; and an intergate dielectric layer interposed between the floating gate and the control gate, the intergate dielectric layer comprising: a first layer formed on the floating gate; a second layer formed on the first layer; and a third layer formed on the second layer, wherein each of the first, second and third layers has a dielectric constant greater than SiO2.
摘要翻译：在一个实施例中，公开了一种半导体器件。所述半导体器件形成在具有有源区的半导体衬底上，所述半导体器件包括：栅极电介质层，其设置在所述半导体衬底上，所述栅极电介质层具有至少两个具有至少一个具有电介质的子层的子层常数大于SiO2; 形成在所述栅介质层上的浮置栅极，限定插入在所述半导体衬底的有源区域内形成的源极和漏极之间的沟道; 形成在浮动栅极上方的控制栅极; 以及插入在所述浮置栅极和所述控制栅极之间的隔间介电层，所述栅极间介电层包括：形成在所述浮动栅极上的第一层; 形成在所述第一层上的第二层; 以及形成在第二层上的第三层，其中第一层，第二层和第三层中的每一层具有大于SiO 2的介电常数。

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