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1. 发明授权

US06291296B1 Method for removing anti-reflective coating layer using plasma etch process before contact CMP 有权
标题翻译：在接触CMP之前使用等离子体蚀刻工艺去除抗反射涂层的方法
公开(公告)号：US06291296B1
公开(公告)日：2001-09-18
申请号：US09416382
申请日：1999-10-12
申请人： Angela T. Hui , Wenge Yang , Kashmir Sahota , Mark T. Ramsbey , Suzette K. Pangrle , Minh Van Ngo
发明人： Angela T. Hui , Wenge Yang , Kashmir Sahota , Mark T. Ramsbey , Suzette K. Pangrle , Minh Van Ngo
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L27/115 , Y10S438/951
摘要： The present invention provides a method for selectively removing anti-reflective coating (ARC) from the surface of an dielectric layer over the surface of a substrate without scratching the dielectric layer and/or tungsten contacts formed therein. In one embodiment, a fluoromethane (CH3F)/oxygen (O2) etch chemistry is used to selectively remove the ARC layer without scratching and/or degradation of the dielectric layer, source/drain regions formed over the substrate, and a silicide layer formed atop stacked gate structures. The CH3F/O2 etch chemistry etches the ARC layer at a rate which is significantly faster than the etch rates of the dielectric layer, the source/drain regions and the silicide layer. In addition, by removing the ARC layer prior to the formation of tungsten contacts by filling of contact openings formed in the dielectric layer with tungsten, potential scratching of tungsten contacts due to ARC layer removal is eliminated.
摘要翻译：本发明提供了一种从基板表面上的电介质层的表面选择性去除抗反射涂层（ARC）的方法，而不会刮擦形成在其中的电介质层和/或钨触点。在一个实施方案中，使用氟甲烷（CH 3 F）/氧（O 2）蚀刻化学物质来选择性地除去ARC层，而不会在电介质层，形成在衬底上的源极/漏极区域的划伤和/或降解，以及形成在顶部的硅化物层堆叠门结构。 CH3F / O2蚀刻化学以比介电层，源/漏区和硅化物层的蚀刻速率明显更快的速率蚀刻ARC层。此外，通过在形成钨触点之前，通过用钨填充形成在电介质层中的接触开口来去除ARC层，消除了由于ARC层去除引起的钨触点的潜在划痕。

2. 发明授权

US6136649A Method for removing anti-reflective coating layer using plasma etch process after contact CMP 有权
标题翻译：接触CMP后使用等离子体蚀刻工艺去除抗反射涂层的方法
公开(公告)号：US6136649A
公开(公告)日：2000-10-24
申请号：US416389
申请日：1999-10-12
申请人： Angela T. Hui , Wenge Yang , Kashmir Sahota , Mark T. Ramsbey , Suzette K. Pangrle , Minh Van Ngo
发明人： Angela T. Hui , Wenge Yang , Kashmir Sahota , Mark T. Ramsbey , Suzette K. Pangrle , Minh Van Ngo
IPC分类号： H01L21/311 , H01L21/336 , H01L21/8247
CPC分类号： H01L27/11521 , H01L21/31116 , H01L29/66825
摘要： The present invention provides a method for selectively removing anti-reflective coating (ARC) from the surface of a dielectric layer over the surface of a substrate without scratching the dielectric layer and/or tungsten contacts formed therein. In one embodiment, a fluoromethane (CH.sub.3 F)/oxygen (O.sub.2) etch chemistry is used to selectively remove the ARC layer. The CH.sub.3 F/O.sub.2 etch chemistry etches the ARC layer at a rate which is significantly faster than the etch rates of the dielectric layer or the tungsten contacts.
摘要翻译：本发明提供一种用于在基板表面上从电介质层的表面选择性去除抗反射涂层（ARC）的方法，而不会刮擦形成在其中的电介质层和/或钨触点。在一个实施方案中，使用氟甲烷（CH 3 F）/氧（O 2）蚀刻化学物质来选择性地除去ARC层。 CH3F / O2蚀刻化学蚀刻ARC层的速度明显快于介电层或钨触点的蚀刻速率。

3. 发明授权

US06348406B1 Method for using a low dielectric constant layer as a semiconductor anti-reflective coating 有权
标题翻译：使用低介电常数层作为半导体抗反射涂层的方法
公开(公告)号：US06348406B1
公开(公告)日：2002-02-19
申请号：US09586264
申请日：2000-05-31
申请人： Ramkumar Subramanian , Minh Van Ngo , Kashmir Sahota , Yongzhong Hu , Hiroyuki Kinoshita , Fei Wang , Wenge Yang
发明人： Ramkumar Subramanian , Minh Van Ngo , Kashmir Sahota , Yongzhong Hu , Hiroyuki Kinoshita , Fei Wang , Wenge Yang
IPC分类号： H01L214763
CPC分类号： H01L27/11521 , H01L21/31144
摘要： The present invention provides a method for manufacturing a semiconductor device with an anti-reflective coating (ARC) that does not need to be removed. In one embodiment, electrical devices are formed on a semiconductor substrate. A dielectric layer is then deposited over the electrical devices and the semiconductor substrate, upon which an optically transparent ARC layer of low dielectric constant is then deposited. Photoresist is then deposited on top of the ARC layer and is then photolithographically processed and subsequently developed. The dielectric layer is then etched down to the semiconductor substrate to form contacts or local interconnects. The ARC layer can subsequently be used as a hard mask and does not require removal.
摘要翻译：本发明提供一种制造具有不需要去除的抗反射涂层（ARC）的半导体器件的方法。在一个实施例中，电子器件形成在半导体衬底上。然后将电介质层沉积在电气器件和半导体衬底上，然后沉积出具有低介电常数的光学透明ARC层。然后将光致抗蚀剂沉积在ARC层的顶部上，然后光刻加工并随后显影。然后将电介质层向下蚀刻到半导体衬底以形成接触或局部互连。 ARC层可以随后用作硬掩模，并且不需要去除。

4. 发明授权

US06376389B1 Method for eliminating anti-reflective coating in semiconductors 有权
标题翻译：消除半导体抗反射涂层的方法
公开(公告)号：US06376389B1
公开(公告)日：2002-04-23
申请号：US09588117
申请日：2000-05-31
申请人： Ramkumar Subramanian , Minh Van Ngo , Kashmir Sahota , Yongzhong Hu , Hiroyuki Kinoshita , Fei Wang , Wenge Yang
发明人： Ramkumar Subramanian , Minh Van Ngo , Kashmir Sahota , Yongzhong Hu , Hiroyuki Kinoshita , Fei Wang , Wenge Yang
IPC分类号： H01L2100
CPC分类号： H01L21/76802 , H01L21/76895 , H01L23/522 , H01L27/115 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a method for manufacturing a semiconductor device without the use of an anti-reflective coating. In one embodiment, electrical devices are formed on a semiconductor substrate. A material with a low dielectric constant such as an oxide is then deposited. The low dielectric layer is then covered with photoresist and photolithographically processed and subsequently developed. The low dielectric layer is then etched using the pattern formed on the photoresist and the photoresist is later removed. Because this process works in any similar circumstances, good examples of its application are the formation of both contacts and local interconnects.
摘要翻译：本发明提供一种不使用抗反射涂层的半导体器件的制造方法。在一个实施例中，电子器件形成在半导体衬底上。然后沉积具有低介电常数的材料，例如氧化物。然后用光致抗蚀剂覆盖低介电层，并进行光刻处理并随后显影。然后使用形成在光致抗蚀剂上的图案蚀刻低介电层，随后去除光致抗蚀剂。因为这个过程在任何类似的情况下都可以工作，它的应用的很好的例子是形成两个触点和局部互连。

5. 发明授权

US06359307B1 Method for forming self-aligned contacts and interconnection lines using dual damascene techniques 有权
标题翻译：使用双镶嵌技术形成自对准触点和互连线的方法
公开(公告)号：US06359307B1
公开(公告)日：2002-03-19
申请号：US09493436
申请日：2000-01-29
申请人： Fei Wang , Hiroyuki Kinoshita , Kashmir Sahota , Yu Sun , Wenge Yang
发明人： Fei Wang , Hiroyuki Kinoshita , Kashmir Sahota , Yu Sun , Wenge Yang
IPC分类号： H01L2976
CPC分类号： H01L21/76897 , H01L23/485 , H01L27/115 , H01L27/11521 , H01L2924/0002 , H01L2924/3011 , Y02P80/30 , H01L2924/00
摘要： The present invention further provides a method for forming self-aligned contacts using a dual damascene techniques that reduces the number of process steps and results in a reduction in cycle time, cost and yield loss. In a preferred embodiment, a method for forming a contact and a channel in a dielectric layer over a region on a semiconductor substrate is provided. The contact is self-aligned. The contact and channel are formed by (1) forming a contact opening in the dielectric layer, (2) forming a channel opening in the dielectric layer, wherein the channel opening encompasses the contact opening, (3) extending the contact opening to expose a portion of the region on the semiconductor substrate; and (4) filling the contact opening and the channel opening with a conductive material to form a contact and a channel, respectively.
摘要翻译：本发明还提供了一种使用双镶嵌技术形成自对准接触的方法，其减少了工艺步骤的数量并导致了循环时间，成本和屈服损失的降低。在优选实施例中，提供了在半导体衬底上的区域上形成电介质层中的接触和沟道的方法。联系人自行对齐。接触和通道由（1）在电介质层中形成接触开口形成，（2）在电介质层中形成通道开口，其中通道开口包围接触开口，（3）延伸接触开口以露出所述半导体衬底上的所述区域的部分; 和（4）分别用导电材料填充接触开口和通道开口以形成接触和通道。

6. 发明授权

US06452225B1 Method and structure of etching a memory cell polysilicon gate layer using resist mask and etched silicon oxynitride 有权
标题翻译：使用抗蚀剂掩模和蚀刻的氮氧化硅蚀刻存储单元多晶硅栅极层的方法和结构
公开(公告)号：US06452225B1
公开(公告)日：2002-09-17
申请号：US09617820
申请日：2000-07-17
申请人： Wenge Yang , Lewis Shen
发明人： Wenge Yang , Lewis Shen
IPC分类号： H01L29788
CPC分类号： H01L27/11517 , Y10S438/942 , Y10S438/95
摘要： A resist mask pattern having a reduced thickness is formed overlying on a silicon oxynitride film during formation of a memory gate. The resist mask pattern has a resist thickness (3000 to 4000 Angstroms) sufficient to withstand removal during etching of the silicon oxynitride film. The silicon oxynitride film, having a thickness of about 800 to 1500 Angstroms, is etched based on the resist mask pattern and then used as a mask pattern to etch the polysilicon gate layer underlying the silicon oxynitride layer, to expose a portion of an isolation region aligned relative to the resist mask pattern. The portion of the resist mask remaining after etching, in combination with the etched silicon oxynitride film, have a sufficient overall thickness to serve as a channel implant mask. Use of the resist mask pattern having the reduced thickness improves yield by minimizing the occurrence of misregistration, and enables reliable formation of spaces in the mask pattern having widths of less than 0.25 microns using conventional deep ultraviolet (DUV) photolithography techniques.
摘要翻译：在形成存储器栅极期间，在氧氮化硅膜上形成厚度减小的抗蚀剂掩模图案。抗蚀剂掩模图案具有足以在蚀刻氮氧化硅膜期间耐受去除的抗蚀剂厚度（3000至4000埃）。基于抗蚀剂掩模图案蚀刻具有约800至1500埃厚度的氧氮化硅膜，然后用作掩模图案以蚀刻氮氧化硅层下面的多晶硅栅极层，以暴露部分隔离区域相对于抗蚀剂掩模图案对准。蚀刻后残留的抗蚀剂掩模的部分与蚀刻的氮氧化硅膜组合，具有足够的总厚度以用作沟道注入掩模。使用具有减小的厚度的抗蚀剂掩模图案通过最小化不对准的发生来提高产率，并且使用常规的深紫外（DUV）光刻技术，可以在宽度小于0.25微米的掩模图案中可靠地形成空间。

7. 发明授权

US5977601A Method for etching memory gate stack using thin resist layer 失效
公开(公告)号：US5977601A
公开(公告)日：1999-11-02
申请号：US118377
申请日：1998-07-17
申请人： Wenge Yang , Lewis Shen
发明人： Wenge Yang , Lewis Shen
IPC分类号： H01L21/027 , H01L21/311 , H01L21/3213 , H01L31/0232 , H01L29/788
CPC分类号： H01L21/31144 , H01L21/32139 , H01L21/0276
摘要： A memory gate stack in a high density memory core has spaces on the order of less than 0.25 microns using conventional deep ultraviolet (DUV) lithography techniques by depositing a layer of silicon oxynitride over a plurality of layers, and a thin resist layer overlying on the silicon oxynitride layer. The resist layer has a thickness sufficient to withstand removal during etching of the silicon oxynitride layer, for example about 3,000 Angstroms to about 4,000 Angstroms. The silicon oxynitride layer has a sacrificial portion having a thickness at least about 500 Angstroms, and a stop-layer thickness, used for spacer formation following etching of the memory gate, of at least 1,000 Angstroms. The use of silicon oxynitride as an antireflective coating layer in combination with the thin resist optimizes the resolution of DUV lithography, enabling formation of spacers having widths less than about 0.24 microns. In addition, the sacrificial layer of the silicon oxynitride layer enables self-aligned etching of the plurality of layers to form the memory gate stack, while maintaining sufficient thickness for spacer formation.

8. 发明授权

US06515328B1 Semiconductor devices with reduced control gate dimensions 有权
标题翻译：具有减小的控制栅极尺寸的半导体器件
公开(公告)号：US06515328B1
公开(公告)日：2003-02-04
申请号：US09244429
申请日：1999-02-04
申请人： Wenge Yang , Lewis Shen , Mark Chang
发明人： Wenge Yang , Lewis Shen , Mark Chang
IPC分类号： H01L29788
CPC分类号： H01L21/32137 , H01L21/28273
摘要： The use of chlorine and oxygen chemistry in a polysilicon etch environment provides a process to etch a plurality of silicon-based layers on a semiconductor substrate to an underlying oxide layer in a single step. The process is useful in the formation of gate structures wherein high selectivity to the underlying oxide layer thereby affords higher processing control over the formed gate structure.
摘要翻译：在多晶硅蚀刻环境中使用氯和氧化学提供了在单个步骤中将半导体衬底上的多个硅基层蚀刻到下面的氧化物层的工艺。该方法在形成栅极结构中是有用的，其中对底层氧化物层的高选择性从而对所形成的栅极结构提供更高的处理控制。

9. 发明授权

US06420240B1 Method for reducing the step height of shallow trench isolation structures 有权
标题翻译：降低浅沟槽隔离结构台阶高度的方法
公开(公告)号：US06420240B1
公开(公告)日：2002-07-16
申请号：US09611701
申请日：2000-07-08
申请人： Wenge Yang , John Jianshi Wang , Hao Fang
发明人： Wenge Yang , John Jianshi Wang , Hao Fang
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： In one embodiment, a process for reducing the step height of shallow trench isolation structures includes the acts of (a) forming a hard mask on a semiconductor substrate to define a trench, (b) forming the trench, (c) filling the trench with a dielectric material, (d) planarizing the dielectric material,(e) replacing the hard mask with a resist mask, (f) etching back the dielectric material to reduce its step height, and (g) removing the resist mask. In another embodiment, the hard mask used to define the trench is used during the etch back of the dielectric material. In another embodiment, the hard mask used to define the trench is partially stripped before the dielectric material is planarized to reduce its step height.
摘要翻译：在一个实施例中，用于降低浅沟槽隔离结构的台阶高度的方法包括以下动作：（a）在半导体衬底上形成硬掩模以限定沟槽，（b）形成沟槽，（c）用电介质材料，（d）使介电材料平坦化，（e）用抗蚀剂掩模代替硬掩模，（f）蚀刻电介质材料以降低其台阶高度，和（g）去除抗蚀剂掩模。在另一个实施例中，用于限定沟槽的硬掩模在电介质材料的回蚀刻期间使用。在另一个实施例中，用于限定沟槽的硬掩模在电介质材料平坦化之前被部分剥离以降低其台阶高度。

10. 发明授权

US06306713B1 Method for forming self-aligned contacts and local interconnects for salicided gates using a secondary spacer 有权
标题翻译：用于使用次级间隔件形成用于盐水门的自对准接触件和局部互连的方法
公开(公告)号：US06306713B1
公开(公告)日：2001-10-23
申请号：US09799469
申请日：2001-03-05
申请人： YongZhong Hu , Fei Wang , Wenge Yang , Yu Sun , Hiroyuki Kinoshita
发明人： YongZhong Hu , Fei Wang , Wenge Yang , Yu Sun , Hiroyuki Kinoshita
IPC分类号： H01L21336
CPC分类号： H01L21/76897 , H01L21/76895 , H01L2924/3011
摘要： A method of manufacturing a semiconductor device is provided in which multi-layer structures are formed on a semiconductor substrate to form core and peripheral regions. Sidewall spacers are formed around the multi-layer structures and source and drain regions are implanted adjacent the sidewall spacers. The multi-layer structures and the source and drain regions are silicided and a stop layer is deposited over the semiconductor substrate after which a dielectric layer is deposited over the stop layer. A photoresist contact mask is deposited, processed, and used to form core contact openings over the core region, which expose the multi-layer structure in addition to the source and drain regions while covering the peripheral region. Protective secondary sidewall spacers are formed in the core contact openings over the exposed multi-layer structures. A second photoresist contact mask is deposited, processed, and used to form peripheral local interconnect openings over the peripheral region which the source and drain regions and portions of the plurality of multi-layer structures in the peripheral region while covering the core region. A conductive material is deposited over the dielectric layer and in the core contact and peripheral local interconnect openings and is chemical mechanical planarized to remove the conductive material over the dielectric layer so the conductive material is left isolated in the core and peripheral contact openings.
摘要翻译：提供一种制造半导体器件的方法，其中在半导体衬底上形成多层结构以形成芯和周边区域。围绕多层结构形成侧壁间隔物，并且将源极和漏极区域相邻于侧壁间隔物注入。多层结构和源极和漏极区域被硅化，并且在半导体衬底上沉积停止层，之后在停止层上沉积电介质层。光致抗蚀剂接触掩模被沉积，加工并用于在芯部区域上形成芯接触开口，除了覆盖周边区域之外，还暴露多层结构以及源极和漏极区域。保护性次级侧壁间隔件形成在暴露的多层结构上的芯接触开口中。第二光致抗蚀剂接触掩模被沉积，加工并用于在外围区域上形成周边局部互连开口，周边区域是外围区域的源极和漏极区域以及多个多层结构的部分，同时覆盖芯部区域。导电材料沉积在电介质层上，并在芯接触和外围局部互连开口中沉积，并进行化学机械平面化以去除电介质层上的导电材料，使得导电材料在芯和外围接触开口中被隔离。

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