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1. 发明授权

US6030868A Elimination of oxynitride (ONO) etch residue and polysilicon stringers through isolation of floating gates on adjacent bitlines by polysilicon oxidation 失效
标题翻译：通过多晶硅氧化隔离相邻位线上的浮栅，消除氧氮化物（ONO）蚀刻残渣和多晶硅桁架
公开(公告)号：US6030868A
公开(公告)日：2000-02-29
申请号：US33916
申请日：1998-03-03
申请人： Kathleen R. Early , Michael K. Templeton , Nicholas H. Tripsas , Maria C. Chan , Mark T. Ramsbey
发明人： Kathleen R. Early , Michael K. Templeton , Nicholas H. Tripsas , Maria C. Chan , Mark T. Ramsbey
IPC分类号： H01L21/8247 , H01L27/115 , H01L21/336
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method for fabricating a first memory cell and a second memory cell having floating gates electrically isolated from each other. A first polysilicon (poly I) layer is formed on an oxide coated substrate, portions of the poly I layer to serve as future floating gates for the first and second memory cells. An interpoly dielectric layer is formed over the poly I layer. At least a portion of the interpoly dielectric layer is etched to expose at least a portion of the poly I layer so as to pattern the floating gates on either side of the exposed portion of the poly I layer. The exposed portion of the poly I layer is transformed into an insulator via thermal oxidation such that the insulator electrically isolates a floating gate of the first memory cell from a floating gate of the second memory cell. A second polysilicon (poly II) layer is formed substantially free of abrupt changes in step height.
摘要翻译：一种制造第一存储单元的方法和具有彼此电隔离的浮动栅极的第二存储单元。在氧化物涂覆的基底上形成第一多晶硅（poly I）层，多晶硅层的部分用作第一和第二存储单元的未来浮动栅极。在多晶硅层上形成多层介电层。蚀刻至少一部分互电介质层以暴露多晶硅层的至少一部分，以便在多晶硅层的暴露部分的任一侧上对浮动栅极进行图案化。多层I的暴露部分通过热氧化转变为绝缘体，使得绝缘体将第一存储器单元的浮动栅极与第二存储单元的浮置栅极电隔离。形成基本上没有台阶高度突然变化的第二多晶硅（poly II）层。

2. 发明授权

US6110833A Elimination of oxynitride (ONO) etch residue and polysilicon stringers through isolation of floating gates on adjacent bitlines by polysilicon oxidation 失效
标题翻译：通过多晶硅氧化隔离相邻位线上的浮栅，消除氧氮化物（ONO）蚀刻残渣和多晶硅桁架
公开(公告)号：US6110833A
公开(公告)日：2000-08-29
申请号：US33836
申请日：1998-03-03
申请人： Kathleen R. Early , Michael K. Templeton , Nicholas H. Tripsas , Maria C. Chan
发明人： Kathleen R. Early , Michael K. Templeton , Nicholas H. Tripsas , Maria C. Chan
IPC分类号： A61K38/00 , A61K38/30 , H01L21/8247 , H01L21/70
CPC分类号： H01L27/11521 , A61K38/30
摘要： A method for fabricating a first memory cell and a second memory cell electrically isolated from each other is provided. A first polysilicon (poly I) layer is formed on an oxide coated substrate. Then, a sacrificial oxide layer and nitride layer are formed for masking the poly I layer. At least a portion of the masking layer is etched to pattern the first memory cell and the second memory cell and an unmasked portion therebetween. The unmasked portion of the poly I layer is transformed into an insulator via thermal oxidation such that the insulator separates a floating gate of the first memory cell from a floating gate of the second memory cell. The insulator is etched so as to form a gap having gradually sloping sidewalls between a floating gate of the first memory cell and a floating gate of the second memory cell, the gap isolating the floating gate of the first memory cell from the floating gate of the second memory cell. Thereafter, an interpoly dielectric layer and a second polysilicon (poly II) layer are formed substantially free of abrupt changes in step height.
摘要翻译：提供了一种用于制造彼此电隔离的第一存储单元和第二存储单元的方法。在氧化物涂覆的基底上形成第一多晶硅（poly I）层。然后，形成用于掩蔽多晶硅层的牺牲氧化物层和氮化物层。蚀刻掩模层的至少一部分以对第一存储单元和第二存储单元进行图案化，并且在其间形成未屏蔽部分。多层I层的未屏蔽部分通过热氧化转变为绝缘体，使得绝缘体将第一存储器单元的浮置栅极与第二存储单元的浮置栅极分开。绝缘体被蚀刻以形成在第一存储单元的浮动栅极和第二存储单元的浮置栅极之间具有逐渐倾斜的侧壁的间隙，将第一存储单元的浮置栅极与第一存储单元的浮动栅极隔离的间隙第二存储单元。此后，形成基本上不具有台阶高度突然变化的互聚电介质层和第二多晶硅（poly II）层。

3. 发明授权

US6043120A Elimination of oxynitride (ONO) etch residue and polysilicon stringers through isolation of floating gates on adjacent bitlines by polysilicon oxidation 失效
标题翻译：通过多晶硅氧化隔离相邻位线上的浮栅，消除氧氮化物（ONO）蚀刻残渣和多晶硅桁架
公开(公告)号：US6043120A
公开(公告)日：2000-03-28
申请号：US33723
申请日：1998-03-03
申请人： Kathleen R. Early , Michael K. Templeton , Nicholas H. Tripsas , Maria C. Chan
发明人： Kathleen R. Early , Michael K. Templeton , Nicholas H. Tripsas , Maria C. Chan
IPC分类号： H01L21/8247
CPC分类号： H01L27/11521
摘要： A method for fabricating a first memory cell and a second memory cell electrically isolated from each other. A first polysilicon (poly I) layer is formed on an oxide coated substrate. A masking layer is deposited or grown on the poly I layer, and at least a portion of the masking layer is etched so as to pattern the first memory cell and the second memory cell and an unmasked portion therebetween. The unmasked portion of the poly I layer is transformed into an insulator via thermal oxidation such that the insulator electrically isolates a floating gate of the first memory cell from a floating gate of the second memory cell. An interpoly dielectric layer and a second polysilicon (poly II) layer is formed over the poly I layer and insulator substantially free of abrupt changes in step height.
摘要翻译：一种用于制造彼此电隔离的第一存储单元和第二存储单元的方法。在氧化物涂覆的基底上形成第一多晶硅（poly I）层。在多晶硅层上沉积或生长掩模层，并且蚀刻掩模层的至少一部分，以便对第一存储单元和第二存储单元进行图案化，并且在其间形成未屏蔽部分。多层I层的未屏蔽部分通过热氧化转变为绝缘体，使得绝缘体将第一存储器单元的浮置栅极与第二存储单元的浮置栅极电隔离。在多层I层和绝缘体上形成多层介电层和第二多晶硅（poly II）层，绝缘体基本上没有台阶高度的突然变化。

4. 发明授权

US06455888B1 Memory cell structure for elimination of oxynitride (ONO) etch residue and polysilicon stringers 有权
标题翻译：用于消除氧氮化物（ONO）蚀刻残留物和多晶硅桁架的记忆单元结构
公开(公告)号：US06455888B1
公开(公告)日：2002-09-24
申请号：US09506298
申请日：2000-02-17
申请人： Kathleen R. Early , Michael K. Templeton , Nicholas H. Tripsas , Maria C. Chan
发明人： Kathleen R. Early , Michael K. Templeton , Nicholas H. Tripsas , Maria C. Chan
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , A61K38/30
摘要： A method for fabricating a first memory cell and a second memory cell electrically isolated from each other is provided. A first polysilicon (poly I) layer is formed on an oxide coated substrate. Then, a sacrificial oxide layer and nitride layer are formed for masking the poly I layer. At least a portion of the masking layer is etched to pattern the first memory cell and the second memory cell and an unmasked portion therebetween. The unmasked portion of the poly I layer is transformed into an insulator via thermal oxidation such that the insulator separates a floating gate of the first memory cell from a floating gate of the second memory cell. The insulator is etched so as to form a gap having gradually sloping sidewalls between a floating gate of the first memory cell and a floating gate of the second memory cell, the gap isolating the floating gate of the first memory cell from the floating gate of the second memory cell. Thereafter, an interpoly dielectric layer and a second polysilicon (poly II) layer are formed substantially free of abrupt changes in step height.
摘要翻译：提供了一种用于制造彼此电隔离的第一存储单元和第二存储单元的方法。在氧化物涂覆的基底上形成第一多晶硅（poly I）层。然后，形成用于掩蔽多晶硅层的牺牲氧化物层和氮化物层。蚀刻掩模层的至少一部分以对第一存储单元和第二存储单元进行图案化，并且在其间形成未屏蔽部分。多层I层的未屏蔽部分通过热氧化转变为绝缘体，使得绝缘体将第一存储器单元的浮置栅极与第二存储单元的浮置栅极分开。绝缘体被蚀刻以形成在第一存储单元的浮动栅极和第二存储单元的浮置栅极之间具有逐渐倾斜的侧壁的间隙，将第一存储单元的浮置栅极与第一存储单元的浮动栅极隔离的间隙第二存储单元。此后，形成基本上不具有台阶高度突然变化的互聚电介质层和第二多晶硅（poly II）层。

5. 发明授权

US06630383B1 Bi-layer floating gate for improved work function between floating gate and a high-K dielectric layer 有权
标题翻译：双层浮栅，用于改善浮栅和高K电介质层之间的功函数
公开(公告)号：US06630383B1
公开(公告)日：2003-10-07
申请号：US10274063
申请日：2002-10-17
申请人： Effiong Ibok , Wei Zheng , Nicholas H. Tripsas , Mark T. Ramsbey , Fred T K Cheung
发明人： Effiong Ibok , Wei Zheng , Nicholas H. Tripsas , Mark T. Ramsbey , Fred T K Cheung
IPC分类号： H01L21336
CPC分类号： H01L21/28194 , H01L21/28273 , H01L29/42324 , H01L29/4958 , H01L29/51 , H01L29/511
摘要： In one embodiment, a method of making a gate stack semiconductor device is disclosed. The method comprises the steps of: forming a tunnel oxide layer over a p-type semiconductor substrate; forming a floating gate over the tunnel oxide layer by first forming an n-type polysilicon layer and subjecting the n-type polysilicon layer to nitridation, and then forming a p-type polysilicon layer over the nitridated n-type polysilicon layer; and forming a high-K insulating layer over the p-type polysilicon layer.
摘要翻译：在一个实施例中，公开了制造栅叠层半导体器件的方法。该方法包括以下步骤：在p型半导体衬底上形成隧道氧化物层; 通过首先形成n型多晶硅层并对n型多晶硅层进行氮化，然后在氮化的n型多晶硅层上形成p型多晶硅层，在隧道氧化物层上形成浮栅; 以及在p型多晶硅层上形成高K绝缘层。

6. 发明授权

US06548855B1 Non-volatile memory dielectric as charge pump dielectric 失效
标题翻译：非易失性存储介质作为电荷泵电介质
公开(公告)号：US06548855B1
公开(公告)日：2003-04-15
申请号：US10147622
申请日：2002-05-16
申请人： Mark T. Ramsbey , Arvind Halliyal , Kuo-Tung Chang , Nicholas H. Tripsas , Wei Zheng , Unsoon Kim
发明人： Mark T. Ramsbey , Arvind Halliyal , Kuo-Tung Chang , Nicholas H. Tripsas , Wei Zheng , Unsoon Kim
IPC分类号： H01L2976
CPC分类号： H01L27/11526 , H01L27/115 , H01L27/11539
摘要： A non-volatile memory device for retention of data when electrical power is terminated. The non-volatile memory device includes at least one memory cell and a charge pump for stepping up the incoming voltage supply. The charge pump includes at least one capacitor, wherein the dielectric of the charge pump capacitor and the dielectric of the memory cell are formed during the same processing step.
摘要翻译：一种用于在电力终止时保留数据的非易失性存储器件。非易失性存储器件包括至少一个存储单元和用于加速输入电压源的电荷泵。电荷泵包括至少一个电容器，其中电荷泵电容器的电介质和存储单元的电介质在相同的处理步骤期间形成。

7. 发明授权

US07001807B1 Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same 有权
公开(公告)号：US07001807B1
公开(公告)日：2006-02-21
申请号：US10997345
申请日：2004-11-24
申请人： Wei Zheng , Mark W. Randolph , Nicholas H. Tripsas , Zoran Krivokapic , Jack F. Thomas , Mark T. Ramsbey
发明人： Wei Zheng , Mark W. Randolph , Nicholas H. Tripsas , Zoran Krivokapic , Jack F. Thomas , Mark T. Ramsbey
IPC分类号： H01L21/31
CPC分类号： H01L29/513 , H01L21/28282 , H01L29/512 , H01L29/517 , H01L29/7923
摘要： A method of fabricating a dual bit dielectric memory cell structure on a silicon substrate includes implanting buried bit lines within the substrate and fabricating a layered island on the surface of the substrate between the buried bit lines. The island has a perimeter defining a gate region, and comprises a tunnel dielectric layer on the surface of the silicon on insulator wafer, an isolation barrier dielectric layer on the surface of the tunnel dielectric layer, a top dielectric layer on the surface of the isolation barrier dielectric layer, and a polysilicon gate on the surface of the top dielectric layer. A portion of the isolation barrier dielectric layer is removed to form an undercut region within the gate region and a charge trapping material is deposited within the undercut region.

8. 发明授权

US06872643B1 Implant damage removal by laser thermal annealing 有权
标题翻译：通过激光热退火去除植入物损伤
公开(公告)号：US06872643B1
公开(公告)日：2005-03-29
申请号：US10378885
申请日：2003-03-05
申请人： Arvind Halliyal , Nicholas H. Tripsas , Mark T. Ramsbey
发明人： Arvind Halliyal , Nicholas H. Tripsas , Mark T. Ramsbey
IPC分类号： H01L21/265 , H01L21/268 , H01L21/22
CPC分类号： H01L21/265 , H01L21/268 , Y10S438/914
摘要： A method of manufacturing a semiconductor device includes forming a layer over a substrate, and doping the layer with a dopant, after which the layer is laser thermal annealed. The layer can be a nitride, an oxide, or a polysilicon layer. The dopants can be arsenic, phosphorous, boron, or nitrogen. During the laser thermal annealing, certain portions of a surface of the semiconductor device are laser thermal annealed and other portions of a surface of the semiconductor device are not exposed. Also, the surface of the layer is smoother after the laser thermal annealing.
摘要翻译：制造半导体器件的方法包括在衬底上形成层，并用掺杂剂掺杂该层，之后激光热退火。该层可以是氮化物，氧化物或多晶硅层。掺杂剂可以是砷，磷，硼或氮。在激光热退火期间，半导体器件的表面的某些部分被激光热退火，并且半导体器件的表面的其它部分不被暴露。此外，在激光热退火之后，该层的表面更平滑。

9. 发明授权

US06783591B1 Laser thermal annealing method for high dielectric constant gate oxide films 失效
标题翻译：高介电常数栅氧化膜激光热退火方法
公开(公告)号：US06783591B1
公开(公告)日：2004-08-31
申请号：US10212237
申请日：2002-08-06
申请人： Arvind Halliyal , Nicholas H. Tripsas , Mark T. Ramsbey
发明人： Arvind Halliyal , Nicholas H. Tripsas , Mark T. Ramsbey
IPC分类号： C30B2504
CPC分类号： H01L29/6659 , H01L21/268 , H01L21/28194 , H01L21/28202 , H01L21/31604 , H01L21/31637 , H01L21/31641 , H01L21/31645 , H01L21/31691 , H01L29/517 , H01L29/518 , H01L29/665
摘要： A method of manufacturing a semiconductor device, including depositing a gate oxide film over a substrate and conditioning the deposited gate oxide film using laser thermal annealing in a single process chamber, and depositing a gate electrode film over the conditioned gate oxide film.
摘要翻译：一种制造半导体器件的方法，包括在衬底上沉积栅极氧化膜并在单个处理室中使用激光热退火调节沉积的栅极氧化膜，并在调节的栅极氧化物膜上沉积栅电极膜。

10. 发明授权

US06735123B1 High density dual bit flash memory cell with non planar structure 失效
标题翻译：具有非平面结构的高密度双位闪存单元
公开(公告)号：US06735123B1
公开(公告)日：2004-05-11
申请号：US10164895
申请日：2002-06-07
申请人： Nicholas H. Tripsas , Mark T. Ramsbey , Wei Zheng , Effiong Ibok , Fred T K Cheung
发明人： Nicholas H. Tripsas , Mark T. Ramsbey , Wei Zheng , Effiong Ibok , Fred T K Cheung
IPC分类号： G11C1604
CPC分类号： H01L29/66833 , G11C16/0475 , H01L21/28282 , H01L29/7923 , Y10S438/981
摘要： A dual bit dielectric memory cell comprises a substrate with a source region and a drain region implanted on opposing sides of a central channel region. A multilevel charge trapping dielectric is positioned on the substrate above the central channel region and includes a central region between an opposing source lateral region and a drain lateral region. A control gate is positioned above the multilevel charge trapping dielectric. The multilevel charge trapping dielectric comprises a tunnel dielectric layer adjacent the substrate, a top dielectric adjacent the control gate, and a charge trapping dielectric positioned there between. The thickness of the tunnel dielectric layer in the central region is greater than a thickness of the tunnel dielectric layer in each of the source lateral region and the drain lateral region.
摘要翻译：双位电介质存储单元包括具有源极区和衬底的衬底，衬底在中心沟道区的相对侧上。多电荷电荷捕获电介质位于中心通道区域上方的衬底上，并且包括在相对的源侧向区域和漏极侧向区域之间的中心区域。控制栅极位于多电平电荷捕获电介质的上方。多电荷电荷俘获电介质包括邻近衬底的隧道电介质层，邻近控制栅极的顶部电介质和位于其间的电荷捕获电介质。中心区域中的隧道介电层的厚度大于源极横向区域和漏极侧向区域中的每一个中的隧道介电层的厚度。

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