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41. 发明授权

US06524883B2 Quantum dot of single electron memory device and method for fabricating thereof 失效
公开(公告)号：US06524883B2
公开(公告)日：2003-02-25
申请号：US09929511
申请日：2001-08-15
申请人： Il-Gweon Kim
发明人： Il-Gweon Kim
IPC分类号： H01L2100
CPC分类号： G06N99/002 , B82Y10/00 , G11C2216/08 , H01L21/26586 , H01L21/28273 , H01L21/31155 , H01L29/66825 , H01L29/7888 , Y10T428/24917
摘要： A method for fabricating a quantum dot, which can be used to fabricate a single electron memory device. The method includes forming a first insulation layer on a semiconductor layer, then forming a second insulation layer on the first insulation layer. Next, the second insulation layer is patterned to form an opening to partially expose the upper surface of the first insulation layer. Using the opening in the second insulation layer, a silicon ion is then implanted into the first insulation layer through the opening by using a tilt angle ion implantation method. Finally, the semiconductor layer is treated to re-crystallize the silicon ion implanted into the first insulation layer.

42. 发明授权

US06507509B1 Nonvolatile memory 失效
标题翻译：非易失性存储器
公开(公告)号：US06507509B1
公开(公告)日：2003-01-14
申请号：US09856913
申请日：2001-08-17
申请人： Youichi Ohtsuka , Junichi Sone , Jaw-Shen Tsai , Takanari Yasui , Yasunobu Nakamura
发明人： Youichi Ohtsuka , Junichi Sone , Jaw-Shen Tsai , Takanari Yasui , Yasunobu Nakamura
IPC分类号： G11C1122
CPC分类号： B82Y10/00 , G11C11/22 , G11C11/5657 , H01L27/11502 , H01L29/7613 , H01L29/78391 , H01L29/7888
摘要： High device reliability, a reduction in power consumption, and a high operation speed are achieved. When a predetermined bias voltage is applied between a source 1 and a drain 2 to change a gate voltage, a current discretely flows between the source 1 and the drain 2 in accordance with quantized electrostatic energy levels in an island electrode 3. The switching ON/OFF of the current between the source 1 and the drain 2 in this case is enabled by applying ½-electron charge to a gate. When the gate voltage induces polarization in a ferroelectric layer 6, its electric field is applied to the island electrode 3. The current between the source 1 and the drain 2 in this case can be measured with high sensitivity. Charge holding is carried out by the polarization in the ferroelectric layer 6, and stored data can be held even if power supply is cut off.
摘要翻译：实现了高的设备可靠性，功耗的降低和高的运行速度。当在源极1和漏极2之间施加预定的偏置电压以改变栅极电压时，根据岛状电极3中的量化的静电能量水平，电流离散地流过源极1和漏极2之间。开关导通/ 在这种情况下，源1和漏极2之间的电流的截止通过向栅极施加1/2电子电荷来实现。当栅极电压在铁电层6中引起极化时，其电场被施加到岛状电极3.在这种情况下，源1和漏极2之间的电流可以高灵敏度地测量。通过强电介质层6中的极化进行电荷保持，即使电源被切断，也可以保持存储的数据。

43. 发明申请

US20020134996A1 Information processing structures 失效
标题翻译：信息处理结构
公开(公告)号：US20020134996A1
公开(公告)日：2002-09-26
申请号：US09926698
申请日：2001-12-04
发明人： Takashi Morie , Atsushi Iwata , Makoto Nagata , Toshio Yamanaka , Tomohiro Matsuura
IPC分类号： H01L027/10
CPC分类号： B82Y10/00 , G11C11/34 , G11C2216/08 , H01L29/7613 , H01L29/7888
摘要： An information processing structure is disclosed that is formed of single electron circuits each operating rapidly and stably by way of a single electron operation. The information processing structure includes a MOSFET (11), and a plurality of quantum dots (13) disposed immediately above a gate electrode (12) of the MOSFET and each of which is made of a microconductor or microsemiconductor of a nanometer scale in size. Between each of the quantum dots and the gate electrode is there formed an energy barrier that an electron is capable of directly tunneling. The total number of such electrons moved between the quantum dots and the gate electrode is used to represent information. In the structure, a power source electrode (14) is disposed in contact with the quantum dots and a pair of information electrodes (15) is disposed across a quantum dot in contact therewith for having electric potentials applied thereto, representing data of information. Between each of the quantum dots and the power source electrode is there also formed a potential barrier that an electron is capable of directly tunneling. A capacitive coupling is provided between the information electrodes in pair and the quantum dot between them to prevent movement of an electron between the quantum dot and the information electrodes, and an electron is rendered movable by the Coulomb blockade through the quantum dot between the power source electrode and the gate electrode in response to a relative electric potential determined at the information electrodes.
摘要翻译：公开了一种信息处理结构，其由单电子电路形成，每个电子电路通过单个电子操作快速且稳定地操作。信息处理结构包括MOSFET（11）和设置在MOSFET的栅电极（12）正上方的多个量子点（13），并且每个量子点由尺寸为纳米级的微导体或微半导体制成。在每个量子点和栅电极之间形成了电子能够直接隧穿的能量势垒。在量子点和栅电极之间移动的这种电子的总数用于表示信息。在该结构中，电源电极（14）与量子点接触地设置，并且一对信息电极（15）跨越与其接触的量子点设置，以使其具有表示数据的信息。在每个量子点和电源电极之间还形成电子能够直接隧穿的势垒。在一对信息电极和它们之间的量子点之间提供电容耦合，以防止电子在量子点和信息电极之间的移动，并且电子通过库仑阻挡使得可移动通过电源之间的量子点电极和栅电极响应于在信息电极处确定的相对电位。

44. 发明授权

US06413819B1 Memory device and method for using prefabricated isolated storage elements 有权
标题翻译：使用预制隔离存储元件的存储器件和方法
公开(公告)号：US06413819B1
公开(公告)日：2002-07-02
申请号：US09595821
申请日：2000-06-16
申请人： Sufi Zafar , Ramachandran Muralidhar , Bich-Yen Nguyen , Sucharita Madhukar , Daniel T. Pham , Michael A. Sadd , Chitra K. Subramanian
发明人： Sufi Zafar , Ramachandran Muralidhar , Bich-Yen Nguyen , Sucharita Madhukar , Daniel T. Pham , Michael A. Sadd , Chitra K. Subramanian
IPC分类号： H01L21336
CPC分类号： B82Y10/00 , H01L21/28273 , H01L29/7883 , H01L29/7888
摘要： A semiconductor device that includes a floating gate made up of a plurality of pre-formed isolated storage elements (18) and a method for making such a device is presented. The device is formed by first providing a semiconductor layer (12) upon which a first gate insulator (14) is formed. A plurality of pre-fabricated isolated storage elements (18) is then deposited on the first gate insulator (14). This deposition step may be accomplished by immersion in a colloidal solution (16) that includes a solvent and pre-fabricated isolated storage elements (18). Once deposited, the solvent of the solution (16) can be removed, leaving the pre-fabricated isolated storage elements (18) deposited on the first gate insulator (14). After depositing the pre-fabricated isolated storage elements (18), a second gate insulator (20) is formed over the pre-fabricated isolated storage elements (18). A gate electrode (24) is then formed over the second gate insulator (20), and portions the first and second gate insulators and the plurality of pre-fabricated isolated storage elements that do not underlie the gate electrode are selectively removed. A source region (32) and a drain region (34) are then formed in the semiconductor layer (12) such that a channel region is formed between underlying the gate electrode (24).
摘要翻译：提供了一种半导体器件，其包括由多个预先形成的隔离存储元件（18）构成的浮动栅极和用于制造这种器件的方法。该器件通过首先提供形成第一栅极绝缘体（14）的半导体层（12）形成。然后，多个预制隔离存储元件（18）沉积在第一栅极绝缘体（14）上。该沉积步骤可以通过浸入包括溶剂和预制隔离存储元件（18）的胶体溶液（16）中来实现。一旦沉积，可以除去溶液（16）的溶剂，留下沉积在第一栅极绝缘体（14）上的预制隔离存储元件（18）。在沉积预制隔离存储元件（18）之后，在预制隔离存储元件（18）上形成第二栅极绝缘体（20）。然后，在第二栅极绝缘体（20）之上形成栅电极（24），并且选择性地去除不在栅电极下面的第一和第二栅极绝缘体和多个预制隔离存储元件的部分。然后在半导体层（12）中形成源极区（32）和漏极区（34），使得在栅电极（24）下方形成沟道区。

45. 发明授权

US06407426B1 Single electron resistor memory device and method 有权
标题翻译：单电子电阻存储器件及方法
公开(公告)号：US06407426B1
公开(公告)日：2002-06-18
申请号：US09703364
申请日：2000-10-31
申请人： Kie Y. Ahn , Leonard Forbes
发明人： Kie Y. Ahn , Leonard Forbes
IPC分类号： H01L27108
CPC分类号： G11C16/04 , B82Y10/00 , G11C11/34 , G11C16/0416 , G11C2216/08 , H01L29/7888 , Y10S977/937
摘要： A memory device includes a plurality of cells, each having a first electrode coupled to a first location on semiconductor material, a second electrode coupled to a second location disposed away from the first location on the semiconductor material and a plurality of islands of semiconductor material. The islands have a maximum dimension of three to five nanometers and are surrounded by an insulator having a thickness of between five and twenty nanometers. The islands and the surrounding insulator are formed in pores extending into the semiconductor material between the first and second electrodes. As a result, the memory cells are able to provide consistent, externally observable changes in response to the presence or absence of a single electron on the island.
摘要翻译：存储器件包括多个单元，每个单元具有耦合到半导体材料上的第一位置的第一电极，耦合到远离半导体材料上的第一位置设置的第二位置的第二电极和多个半导体材料岛。这些岛的最大尺寸为3至5纳米，并被厚度在5至20纳米之间的绝缘体包围。岛和周围的绝缘体形成在延伸到第一和第二电极之间的半导体材料中的孔中。结果，存储器单元能够响应于岛上存在或不存在单个电子而提供一致的外部可观察到的变化。

46. 发明申请

US20020041519A1 Single electron resistor memory device and method 有权
公开(公告)号：US20020041519A1
公开(公告)日：2002-04-11
申请号：US09943726
申请日：2001-08-29
发明人： Kie Y. Ahn , Leonard Forbes
IPC分类号： G11C016/04
CPC分类号： G11C16/04 , B82Y10/00 , G11C11/34 , G11C16/0416 , G11C2216/08 , H01L29/7888 , Y10S977/937
摘要： A memory device includes a plurality of cells, each having a first electrode coupled to a first location on semiconductor material, a second electrode coupled to a second location disposed away from the first location on the semiconductor material and a plurality of islands of semiconductor material. The islands have a maximum dimension of three to five nanometers and are surrounded by an insulator having a thickness of between five and twenty nanometers. The islands and the surrounding insulator are formed in pores extending into the semiconductor material between the first and second electrodes. As a result, the memory cells are able to provide consistent, externally observable changes in response to the presence or absence of a single electron on the island.

47. 发明申请

US20020031649A1 Quantum dot of single electron memory device and method for fabricationg thereof 失效
标题翻译：单电子存储器件的量子点及其制造方法
公开(公告)号：US20020031649A1
公开(公告)日：2002-03-14
申请号：US09929511
申请日：2001-08-15
申请人： Hynix Semiconductor. Inc.
发明人： Il-Gweon Kim
IPC分类号： B32B009/00
CPC分类号： G06N99/002 , B82Y10/00 , G11C2216/08 , H01L21/26586 , H01L21/28273 , H01L21/31155 , H01L29/66825 , H01L29/7888 , Y10T428/24917
摘要： A method for fabricating a quantum dot, which can be used to fabricate a single electron memory device. The method includes forming a first insulation layer on a semiconductor layer, then forming a second insulation layer on the first insulation layer. Next, the second insulation layer is patterned to form an opening to partially expose the upper surface of the first insulation layer. Using the opening in the second insulation layer, a silicon ion is then implanted into the first insulation layer through the opening by using a tilt angle ion implantation method. Finally, the semiconductor layer is treated to re-crystallize the silicon ion implanted into the first insulation layer.
摘要翻译：一种用于制造量子点的方法，其可用于制造单个电子存储器件。该方法包括在半导体层上形成第一绝缘层，然后在第一绝缘层上形成第二绝缘层。接下来，将第二绝缘层图案化以形成开口，以部分地暴露第一绝缘层的上表面。使用第二绝缘层中的开口，然后通过使用倾斜离子注入法将硅离子通过开口注入第一绝缘层。最后，处理半导体层以重新结晶注入到第一绝缘层中的硅离子。

48. 发明申请

US20010052615A1 Nonvolatile semiconductor memory device and process of production and write method thereof 审中-公开
标题翻译：非易失性半导体存储器件及其制作和写入方法
公开(公告)号：US20010052615A1
公开(公告)日：2001-12-20
申请号：US09826815
申请日：2001-04-06
发明人： Ichiro Fujiwara
IPC分类号： H01L029/788
CPC分类号： H01L21/28202 , B82Y10/00 , G11C16/0466 , G11C16/10 , G11C16/30 , H01L21/28194 , H01L29/40114 , H01L29/40117 , H01L29/42324 , H01L29/513 , H01L29/518 , H01L29/7883 , H01L29/7888 , H01L29/792
摘要： A nonvolatile semiconductor memory device featuring a reducing operating voltage while maintaining a good disturbance characteristic and high speed in a write operation, including a gate insulating film and gate electrode stacked on a channel forming region of a semiconductor provided on the surface of a substrate and planarly dispersed charge storing means such as carrier traps in a nitride film or near the interface with the top insulating film, provided in the gate insulating film, the gate insulating film including an FN tunnel film having a dielectric constant larger than that of a silicon oxide film and exhibiting an FN electroconductivity, whereby the thickness of the gate insulating film, converted to that of a silicon oxide film, can be reduced and the voltage can be reduced. Further, to reduce the operation voltage, it is possible to provide a pull-up electrode near the gate electrode through the dielectric film and pull-up gate bias circuit supplying a predetermined voltage to the same and boost the gate electrode capacity coupling.
摘要翻译：一种非易失性半导体存储器件，其具有降低工作电压，同时在写入操作中保持良好的干扰特性和高速度，包括堆叠在设置在衬底表面上的半导体的沟道形成区域上的栅极绝缘膜和栅电极，并且平面地分散的电荷存储装置，例如在栅极绝缘膜中设置在氮化物膜中或与顶部绝缘膜的界面附近的载流子阱，栅极绝缘膜包括介电常数大于氧化硅膜的介电常数的FN隧道膜并且具有FN导电性，由此可以减小转换为氧化硅膜的栅极绝缘膜的厚度，并且可以降低电压。此外，为了降低工作电压，可以通过向其提供预定电压的电介质膜和上拉栅极偏置电路在栅电极附近提供上拉电极，并提高栅电极电容耦合。

49. 发明申请

US20010038135A1 Memory using insulator traps 有权
公开(公告)号：US20010038135A1
公开(公告)日：2001-11-08
申请号：US09858304
申请日：2001-05-15
发明人： Leonard Forbes , Joseph E. Geusic
IPC分类号： H01L029/94 , H01L029/76 , H01L021/336 , H01L031/062
CPC分类号： G11C11/5671 , B82Y10/00 , G11C16/0458 , G11C2216/08 , H01L29/7887 , H01L29/7888 , H01L29/792 , H01L29/7923
摘要： A memory cell provides point defect trap sites in an insulator for storing data charges. Single electrons are stored on respective point defect trap sites and a resulting parameter, such as transistor drain current, is detected. By adjusting the density of the point defect trap sites, more uniform step changes in drain current are obtained as single electrons are stored on or removed from respective trap sites. By also adjusting the trapping energy of the point defect trap sites, the memory cell provides either volatile data storage, similar to a dynamic random access memory (DRAM), or nonvolatile data storage, similar to an electrically erasable and programmable read only memory (EEPROM). The memory cell is used for storing binary or multi-state data.

50. 发明授权

US06310376B1 Semiconductor storage device capable of improving controllability of density and size of floating gate 失效
标题翻译：能够提高浮栅的密度和尺寸的可控性的半导体存储装置
公开(公告)号：US06310376B1
公开(公告)日：2001-10-30
申请号：US09165800
申请日：1998-10-02
申请人： Tohru Ueda , Kenta Nakamura , Yasumori Fukushima
发明人： Tohru Ueda , Kenta Nakamura , Yasumori Fukushima
IPC分类号： H01L29788
CPC分类号： B82Y10/00 , H01L29/7883 , H01L29/7887 , H01L29/7888
摘要： There is provided is a semiconductor storage device that can reduce a dispersion in characteristics such as a threshold voltage and a writing performance and has a low consumption power and a non-volatility. There are included a source region 9 and a drain region 10 formed on a silicon substrate 1, a channel region 3a located between the source and drain regions 9 and 10, a gate electrode 8 that is formed above the channel region 3a and controls a channel current flowing through the channel region 3a, and a control gate insulating film 7, a floating gate 6 and a tunnel insulating film 4 that are arranged in order from the gate electrode 8 side between the channel region 3a and the gate electrode 8. The floating gate 6 is comprised of a plurality of crystal grains 6a linearly discretely arranged substantially parallel to the surface of the channel region 3a.
摘要翻译：提供了可以降低诸如阈值电压和写入性能等特性的色散并具有低消耗功率和非挥发性的半导体存储装置。包括形成在硅衬底1上的源极区9和漏极区10，位于源极和漏极区9和10之间的沟道区3a，形成在沟道区3a上方的栅极8并控制沟道流过沟道区域3a的电流以及从沟道区域3a和栅电极8之间的栅电极8侧依次排列的控制栅绝缘膜7，浮栅6和隧道绝缘膜4。栅极6由基本上平行于沟道区域3a的表面线性离散布置的多个晶粒6a组成。

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