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1. 发明授权

US06518070B1 Process of forming a semiconductor device and a semiconductor device 失效
标题翻译：形成半导体器件和半导体器件的工艺
公开(公告)号：US06518070B1
公开(公告)日：2003-02-11
申请号：US09571586
申请日：2000-05-17
申请人： Prasad V. Alluri , Mark Victor Raymond , Sucharita Madhukar , Roland R. Stumpf , Chun-Li Liu , Clarence J. Tracy
发明人： Prasad V. Alluri , Mark Victor Raymond , Sucharita Madhukar , Roland R. Stumpf , Chun-Li Liu , Clarence J. Tracy
IPC分类号： H01L2170
CPC分类号： H01L21/3212 , H01L27/1057 , H01L27/108 , H01L27/10844 , H01L27/10852 , H01L27/10882 , H01L28/55 , H01L28/60 , H01L28/65
摘要： A process for forming a capacitor with a high-k dielectric or ferroelectric layer within a semiconductor device is used to reduce the likelihood of oxidation or materials interactions between that layer and an underlying layer. A first electrode layer includes atoms that form along grain boundaries within the first electrode layer to reduce the oxidation of a conductive plug or undesired materials interactions.
摘要翻译：用于在半导体器件内形成具有高k电介质层或铁电体层的电容器的工艺被用于降低该层与下层之间的氧化或材料相互作用的可能性。第一电极层包括沿第一电极层内的晶界形成的原子，以减少导电塞的氧化或不期望的材料相互作用。

2. 发明授权

US06413819B1 Memory device and method for using prefabricated isolated storage elements 有权
标题翻译：使用预制隔离存储元件的存储器件和方法
公开(公告)号：US06413819B1
公开(公告)日：2002-07-02
申请号：US09595821
申请日：2000-06-16
申请人： Sufi Zafar , Ramachandran Muralidhar , Bich-Yen Nguyen , Sucharita Madhukar , Daniel T. Pham , Michael A. Sadd , Chitra K. Subramanian
发明人： Sufi Zafar , Ramachandran Muralidhar , Bich-Yen Nguyen , Sucharita Madhukar , Daniel T. Pham , Michael A. Sadd , Chitra K. Subramanian
IPC分类号： H01L21336
CPC分类号： B82Y10/00 , H01L21/28273 , H01L29/7883 , H01L29/7888
摘要： A semiconductor device that includes a floating gate made up of a plurality of pre-formed isolated storage elements (18) and a method for making such a device is presented. The device is formed by first providing a semiconductor layer (12) upon which a first gate insulator (14) is formed. A plurality of pre-fabricated isolated storage elements (18) is then deposited on the first gate insulator (14). This deposition step may be accomplished by immersion in a colloidal solution (16) that includes a solvent and pre-fabricated isolated storage elements (18). Once deposited, the solvent of the solution (16) can be removed, leaving the pre-fabricated isolated storage elements (18) deposited on the first gate insulator (14). After depositing the pre-fabricated isolated storage elements (18), a second gate insulator (20) is formed over the pre-fabricated isolated storage elements (18). A gate electrode (24) is then formed over the second gate insulator (20), and portions the first and second gate insulators and the plurality of pre-fabricated isolated storage elements that do not underlie the gate electrode are selectively removed. A source region (32) and a drain region (34) are then formed in the semiconductor layer (12) such that a channel region is formed between underlying the gate electrode (24).
摘要翻译：提供了一种半导体器件，其包括由多个预先形成的隔离存储元件（18）构成的浮动栅极和用于制造这种器件的方法。该器件通过首先提供形成第一栅极绝缘体（14）的半导体层（12）形成。然后，多个预制隔离存储元件（18）沉积在第一栅极绝缘体（14）上。该沉积步骤可以通过浸入包括溶剂和预制隔离存储元件（18）的胶体溶液（16）中来实现。一旦沉积，可以除去溶液（16）的溶剂，留下沉积在第一栅极绝缘体（14）上的预制隔离存储元件（18）。在沉积预制隔离存储元件（18）之后，在预制隔离存储元件（18）上形成第二栅极绝缘体（20）。然后，在第二栅极绝缘体（20）之上形成栅电极（24），并且选择性地去除不在栅电极下面的第一和第二栅极绝缘体和多个预制隔离存储元件的部分。然后在半导体层（12）中形成源极区（32）和漏极区（34），使得在栅电极（24）下方形成沟道区。

3. 发明授权

US06794281B2 Dual metal gate transistors for CMOS process 有权
标题翻译：用于CMOS工艺的双金属栅极晶体管
公开(公告)号：US06794281B2
公开(公告)日：2004-09-21
申请号：US10238314
申请日：2002-09-10
申请人： Sucharita Madhukar , Bich-Yen Nguyen
发明人： Sucharita Madhukar , Bich-Yen Nguyen
IPC分类号： H01L214763
CPC分类号： H01L21/823842 , H01L29/66545
摘要： A process for forming a first transistor of a first conductivity type and a second transistor of a second conductivity type in a semiconductor substrate is disclosed. The substrate has a first well of the first conductivity type and a second well of the second conductivity type. A gate dielectric is formed over the wells. A first metal layer is then formed over the gate dielectric. A portion of the first metal layer located over the second well is then removed. A second metal layer different from said first metal is then formed over the wells and a gate mask is formed over the second metal. The metal layers are then patterned to leave a first gate over the first well and a second gate over the second well. Source/drains are then formed in the first and second wells to form the first and second transistor.
摘要翻译：公开了一种在半导体衬底中形成第一导电类型的第一晶体管和第二导电类型的第二晶体管的工艺。衬底具有第一导电类型的第一阱和第二导电类型的第二阱。在阱上形成栅极电介质。然后在栅极电介质上形成第一金属层。然后去除位于第二孔上方的第一金属层的一部分。然后在阱上形成与所述第一金属不同的第二金属层，并且在第二金属上形成栅极掩模。然后将金属层图案化以在第一阱上留下第一栅极，在第二阱上留下第二栅极。然后在第一和第二阱中形成源极/漏极，以形成第一和第二晶体管。

4. 发明授权

US06344403B1 Memory device and method for manufacture 有权
标题翻译：存储器件及其制造方法
公开(公告)号：US06344403B1
公开(公告)日：2002-02-05
申请号：US09595735
申请日：2000-06-16
申请人： Sucharita Madhukar , Ramachandran Muralidhar , David L. O'Meara , Kristen C. Smith , Bich-Yen Nguyen
发明人： Sucharita Madhukar , Ramachandran Muralidhar , David L. O'Meara , Kristen C. Smith , Bich-Yen Nguyen
IPC分类号： H01L2120
CPC分类号： H01L21/28273 , B82Y10/00 , H01L21/02381 , H01L21/02532 , H01L21/0259 , H01L21/0262 , H01L21/3105 , H01L21/3144 , H01L21/3145 , H01L29/42332 , H01L29/66825
摘要： A semiconductor memory device with a floating gate that includes a plurality of nanoclusters (21) and techniques useful in the manufacturing of such a device are presented. The device is formed by first providing a semiconductor substrate (12) upon which a tunnel dielectric layer (14) is formed. A plurality of nanoclusters (19) is then grown on the tunnel dielectric layer (14). The growth of the nanoclusters (19) may be accomplished using low pressure chemical vapor deposition (LPCVD) or ultra high vacuum chemical vapor deposition (UHCVD) processes. Such growth may be facilitated by formation of a nitrogen-containing layer (502) overlying the tunnel dielectric layer (14). After growth of the nanoclusters (21), a control dielectric layer (20) is formed over the nanoclusters (21). In order to prevent oxidation of the formed nanoclusters (21), the nanoclusters (21) may be encapsulated using various techniques prior to formation of the control dielectric layer (20). A gate electrode (24) is then formed over the control dielectric (20), and portions of the control dielectric, the plurality of nanoclusters, and the gate dielectric that do not underlie the gate electrode are selectively removed. After formation of spacers (35), source and drain regions (32, 34) are then formed by implantation in the semiconductor layer (12) such that a channel region is formed between the source and drain regions (32, 34) underlying the gate electrode (24).
摘要翻译：提出了一种具有浮动栅极的半导体存储器件，其包括多个纳米团簇（21）和用于制造这种器件的技术。该器件通过首先提供其上形成有隧道介电层（14）的半导体衬底（12）形成。然后在隧道介电层（14）上生长多个纳米团簇（19）。纳米团簇（19）的生长可以使用低压化学气相沉积（LPCVD）或超高真空化学气相沉积（UHCVD）工艺来实现。可以通过形成覆盖在隧道介电层（14）上的含氮层（502）来促进这种生长。在纳米团簇（21）生长之后，在纳米团簇（21）上形成控制电介质层（20）。为了防止形成的纳米团簇（21）的氧化，可以在形成控制电介质层（20）之前使用各种技术将纳米团簇（21）进行封装。然后在控制电介质（20）上形成栅极（24），并且选择性地去除不在栅电极下面的控制电介质，多个纳米团簇和栅极电介质的部分。在形成间隔物（35）之后，然后通过注入在半导体层（12）中形成源极和漏极区域（32,34），使得沟道区域形成在栅极下面的源极和漏极区域（32,34）之间电极（24）。

5. 发明授权

US06444545B1 Device structure for storing charge and method therefore 有权
标题翻译：因此，用于存储电荷和方法的装置结构
公开(公告)号：US06444545B1
公开(公告)日：2002-09-03
申请号：US09740249
申请日：2000-12-19
申请人： Michael A. Sadd , Sucharita Madhukar , Frank Kelsey Baker
发明人： Michael A. Sadd , Sucharita Madhukar , Frank Kelsey Baker
IPC分类号： H01L2120
CPC分类号： H01L29/42332 , B82Y10/00 , H01L21/28273 , H01L21/28282
摘要： A semiconductor device structure for storing charge has a silicon nitride layer, in which a plurality of nanoclusters are sandwiched between oxide layers. The nanoclusters and the silicon nitride make up a storage region, which is particularly useful in non-volatile memories. The nanoclusters provide a repository for holes or electrons that jump from trap to trap in the silicon nitride when the silicon nitride is heated. This results in much of the charge, which would normally leak off from the silicon nitride at high temperatures, remaining in the storage region due to trapping in the nanoclusters. The silicon nitride layer with nanoclusters therein is formed by depositing a silicon nitride layer, then nanoclusters, and then another silicon nitride layer or by depositing a silicon-rich silicon nitride layer and subsequent heating to cause it to transform to a regular silicon nitride layer with silicon nanoclusters therein.
摘要翻译：用于存储电荷的半导体器件结构具有氮化硅层，其中多个纳米团簇夹在氧化物层之间。纳米团簇和氮化硅组成存储区域，这在非易失性存储器中特别有用。当氮化硅被加热时，纳米团簇提供了在氮化硅中从阱陷阱陷阱的空穴或电子库。这导致大量的电荷，其通常在高温下从氮化硅泄漏出来，由于在纳米团簇中的捕获而残留在存储区域中。其中具有纳米团簇的氮化硅层通过沉积氮化硅层，然后沉积纳米团簇，然后沉积另一个氮化硅层或通过沉积富硅氮化硅层并随后加热使其转变成规则的氮化硅层而形成，硅纳米团簇。

6. 发明授权

US06444512B1 Dual metal gate transistors for CMOS process 有权
公开(公告)号：US06444512B1
公开(公告)日：2002-09-03
申请号：US09592448
申请日：2000-06-12
申请人： Sucharita Madhukar , Bich-Yen Nguyen
发明人： Sucharita Madhukar , Bich-Yen Nguyen
IPC分类号： H01L218238
CPC分类号： H01L21/823842 , H01L29/66545 , Y10S977/707 , Y10S977/721 , Y10S977/891
摘要： A process for forming a first transistor of a first conductivity type and a second transistor of a second conductivity type in a semiconductor substrate is disclosed. The substrate has a first well of the first conductivity type and a second well of the second conductivity type. A gate dielectric is formed over the wells. A first metal layer is then formed over the gate dielectric. A portion of the first metal layer located over the second well is then removed. A second metal layer different from said first metal is then formed over the wells and a gate mask is formed over the second metal. The metal layers are then patterned to leave a first gate over the first well and a second gate over the second well. Source/drains are then formed in the first and second wells to form the first and second transistor.

7. 发明授权

US06297095B1 Memory device that includes passivated nanoclusters and method for manufacture 有权
标题翻译：包含钝化纳米簇的记忆体装置及其制造方法
公开(公告)号：US06297095B1
公开(公告)日：2001-10-02
申请号：US09596399
申请日：2000-06-16
申请人： Ramachandran Muralidhar , Chitra K. Subramanian , Sucharita Madhukar , Bruce E. White , Michael A. Sadd , Sufi Zafar , David L. O'Meara , Bich-Yen Nguyen
发明人： Ramachandran Muralidhar , Chitra K. Subramanian , Sucharita Madhukar , Bruce E. White , Michael A. Sadd , Sufi Zafar , David L. O'Meara , Bich-Yen Nguyen
IPC分类号： H01L21336
CPC分类号： H01L21/28282 , B82Y10/00 , H01L21/28273 , H01L29/66439 , H01L29/7888
摘要： A semiconductor memory device with a floating gate that includes a plurality of nanoclusters (21) and techniques useful in the manufacturing of such a device are presented. The device is formed by first providing a semiconductor substrate (12) upon which a tunnel dielectric layer (14) is formed. A plurality of nanoclusters (19) is then grown on the tunnel dielectric layer (14). After growth of the nanoclusters (21), a control dielectric layer (20) is formed over the nanoclusters (21). In order to prevent oxidation of the formed nanoclusters (21), the nanoclusters (21) may be encapsulated using various techniques prior to formation of the control dielectric layer (20). A gate electrode (24) is then formed over the control dielectric (20), and portions of the control dielectric, the plurality of nanoclusters, and the gate dielectric that do not underlie the gate electrode are selectively removed. After formation of spacers (35), source and drain regions (32, 34) are then formed by implantation in the semiconductor layer (12) such that a channel region is formed between the source and drain regions (32, 34) underlying the gate electrode (24).
摘要翻译：提出了一种具有浮动栅极的半导体存储器件，其包括多个纳米团簇（21）和用于制造这种器件的技术。该器件通过首先提供其上形成有隧道介电层（14）的半导体衬底（12）形成。然后在隧道介电层（14）上生长多个纳米团簇（19）。在纳米团簇（21）生长之后，在纳米团簇（21）上形成控制电介质层（20）。为了防止形成的纳米团簇（21）的氧化，可以在形成控制电介质层（20）之前使用各种技术将纳米团簇（21）进行封装。然后在控制电介质（20）上形成栅极（24），并且选择性地去除不在栅电极下面的控制电介质，多个纳米团簇和栅极电介质的部分。在形成间隔物（35）之后，然后通过注入在半导体层（12）中形成源极和漏极区域（32,34），使得沟道区域形成在栅极下面的源极和漏极区域（32,34）之间电极（24）。

8. 发明授权

US06545324B2 Dual metal gate transistors for CMOS process 有权
公开(公告)号：US06545324B2
公开(公告)日：2003-04-08
申请号：US10151371
申请日：2002-05-20
申请人： Sucharita Madhukar , Bich-Yen Nguyen
发明人： Sucharita Madhukar , Bich-Yen Nguyen
IPC分类号： H01L2976
CPC分类号： H01L21/823842 , H01L29/66545 , Y10S977/707 , Y10S977/721 , Y10S977/891
摘要： A process for forming a first transistor of a first conductivity type and a second transistor of a second conductivity type in a semiconductor substrate is disclosed. The substrate has a first well of the first conductivity type and a second well of the second conductivity type. A gate dielectric is formed over the wells. A first metal layer is then formed over the gate dielectric. A portion of the first metal layer located over the second well is then removed. A second metal layer different from said first metal is then formed over the wells and a gate mask is formed over the second metal. The metal layers are then patterned to leave a first gate over the first well and a second gate over the second well. Source/drains are then formed in the first and second wells to form the first and second transistor.

9. 发明授权

US06320784B1 Memory cell and method for programming thereof 有权
标题翻译：存储单元及其编程方法
公开(公告)号：US06320784B1
公开(公告)日：2001-11-20
申请号：US09524916
申请日：2000-03-14
申请人： Ramachandran Muralidhar , Sucharita Madhukar , Bo Jiang , Bruce E. White , Srikanth B. Samavedam , David L. O'Meara , Michael Alan Sadd
发明人： Ramachandran Muralidhar , Sucharita Madhukar , Bo Jiang , Bruce E. White , Srikanth B. Samavedam , David L. O'Meara , Michael Alan Sadd
IPC分类号： G11C1100
CPC分类号： B82Y10/00 , G11C11/56 , G11C11/5671 , G11C16/0416 , G11C2216/08 , H01L29/7887 , H01L29/7888
摘要： A memory cell (101), its method of formation, and operation are disclosed. In accordance with one embodiment, the memory cell (101) comprises a first and second current carrying electrode (12) a control electrode (19), and doped discontinuous storage elements (17). In accordance with an alternative embodiment, memory cell programming is accomplished by removing or adding an average of approximately at least a first charge (30, 62, 64), which can be electron(s) or hole(s) from each of the doped discontinuous storage elements (17).
摘要翻译：公开了一种存储单元（101），其形成方法和操作。根据一个实施例，存储单元（101）包括第一和第二载流电极（12），控制电极（19）和掺杂的非连续存储元件（17）。根据替代实施例，存储器单元编程通过去除或添加大约至少第一电荷（30,62,64）的平均值来实现，所述第一电荷可以是来自掺杂的每一个的电子或空穴不连续存储元件（17）。

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