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1. 发明授权

US06834006B2 Method and circuit for reading data from a ferroelectric memory cell 有权
标题翻译：用于从铁电存储单元读取数据的方法和电路
公开(公告)号：US06834006B2
公开(公告)日：2004-12-21
申请号：US10247375
申请日：2002-09-20
申请人： Yasushi Igarashi
发明人： Yasushi Igarashi
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： Data stored in a ferroelectric capacitor in a ferroelectric memory cell are read by applying a preliminary voltage to the ferroelectric capacitor to increase its polarization if a certain data value is stored, then applying a series of read voltages to produce a potential responsive to the stored data. The preliminary voltage may be applied either before or after one terminal of the ferroelectric capacitor is placed in a floating state, which is maintained while the series of read voltages is applied. Application of the preliminary voltage provides an increased reading margin if the ferroelectric capacitor has partially lost polarization while storing the certain data value, by restoring some of the lost polarization.
摘要翻译：通过向铁电电容器施加初步电压来读取存储在铁电存储单元中的铁电电容器的数据，以便如果存储某个数据值则增加其极化，然后施加一系列读取电压以响应于所存储的数据产生电位。可以在将铁电电容器的一个端子置于浮置状态之前或之后施加初始电压，该浮置状态在施加一系列读取电压时保持。如果铁电电容器通过恢复一些失去的极化而在存储某些数据值的同时部分地失去极化，则初始电压的应用提供增加的读取余量。

2. 发明授权

US06829155B2 Nonvolatile ferroelectric memory device 有权
标题翻译：非易失性铁电存储器件
公开(公告)号：US06829155B2
公开(公告)日：2004-12-07
申请号：US10608573
申请日：2003-06-30
申请人： Hee Bok Kang
发明人： Hee Bok Kang
IPC分类号： G11C1122
CPC分类号： G11C11/22 , G11C8/10
摘要： The nonvolatile ferroelectric memory device comprises a plurality of cell array blocks; a plurality of drivers; and a plurality of decoders connected to the cell array blocks, respectively, wherein the decoder comprises a first sub-decoder for generating the decoding signal applied to the driver and a second sub-decoder for generating a signal selecting the driver. As a result, the nonvolatile ferroelectric memory device can reduce the area of the device and improve the driving speed.
摘要翻译：非易失性铁电存储器件包括多个单元阵列块; 多个司机; 以及分别连接到单元阵列块的多个解码器，其中解码器包括用于产生施加到驱动器的解码信号的第一子解码器和用于产生选择驱动器的信号的第二子解码器。结果，非易失性铁电存储器件可以减小器件的面积并提高驱动速度。

3. 发明授权

US06807080B2 Enhanced storage states in an memory 失效
标题翻译：内存中增强的存储状态
公开(公告)号：US06807080B2
公开(公告)日：2004-10-19
申请号：US10150744
申请日：2002-05-17
申请人： Jurgen Thomas Rickes , Hugh Pryor McAdams , Scott Robert Summerfelt
发明人： Jurgen Thomas Rickes , Hugh Pryor McAdams , Scott Robert Summerfelt
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A memory with mechanisms for enhancing storage states without boosting voltages to levels that damage storage cell structures. A storage cell according to the present teachings includes a storage structure capable of switching storage states. A memory according to the present teachings includes means for writing the storage cell by applying a first voltage to a first node of the storage structure and for applying a second voltage to a second node of the storage structure such that the first and second voltages have opposite polarities.
摘要翻译：具有增强存储状态的机制的存储器，而不将电压提升到损坏存储单元结构的电平。根据本教导的存储单元包括能够切换存储状态的存储结构。根据本教导的存储器包括通过向存储结构的第一节点施加第一电压并且将第二电压施加到存储结构的第二节点来写入存储单元的装置，使得第一和第二电压具有相反的极性

4. 发明授权

US06801447B2 Ferroelectric storage device 失效
标题翻译：铁电存储设备
公开(公告)号：US06801447B2
公开(公告)日：2004-10-05
申请号：US10232313
申请日：2002-09-03
申请人： Yasuo Murakuki
发明人： Yasuo Murakuki
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： To provide a ferroelectric storage device which can read all the quantities of charge (polarization quantity: 2Pr) accumulated in a ferroelectric during a writing operation. In the present invention, a bit line is recharged, a charge quantity required for recharging is detected, and the quantity is read on a sub bit line, thereby achieving a stable reading operation.
摘要翻译：提供一种在写入操作期间可以读取累积在铁电体中的所有量的电荷（极化量：2Pr）的铁电存储装置。在本发明中，对位线进行再充电，检测再充电所需的电荷量，并且在子位线上读取量，从而实现稳定的读取操作。

5. 发明授权

US06791862B2 Junction-isolated depletion mode ferroelectric memory devices 失效
标题翻译：结型隔离耗尽型铁电存储器件
公开(公告)号：US06791862B2
公开(公告)日：2004-09-14
申请号：US10339503
申请日：2003-01-09
申请人： Craig T. Salling , Brian W. Huber
发明人： Craig T. Salling , Brian W. Huber
IPC分类号： G11C1122
CPC分类号： H01L27/11502 , G11C11/22 , H01L27/11585 , H01L27/1159 , H01L29/78391
摘要： Depletion-mode ferroelectric transistors are adapted for use as non-volatile memory cells. Various embodiments are described having a diode interposed between the bit line and a source/drain region of the transistor for added margin against read disturb. Various additional embodiments are described having an array architecture such that two memory cells sharing the same bit line also share the same program line. Using this configuration, non-selected cells are readily supplied with gate/source voltages sufficient to maintain the cells in a deactivated state during read and write operations on selected cells.
摘要翻译：耗尽型铁电晶体管适合用作非易失性存储单元。描述了具有夹在晶体管的位线和源极/漏极区之间的二极管的各种实施例，用于增加读取干扰的余量。描述具有阵列架构的各种附加实施例，使得共享相同位线的两个存储器单元也共享相同的程序行。使用这种配置，非选择的单元容易地被提供有足够的栅极/源极电压，以便在对所选择的单元的读取和写入操作期间将单元维持在去激活状态。

6. 发明授权

US06754096B2 Apparatus and method for driving ferroelectric memory 有权
标题翻译：用于驱动铁电存储器的装置和方法
公开(公告)号：US06754096B2
公开(公告)日：2004-06-22
申请号：US10320611
申请日：2002-12-17
申请人： Hee Bok Kang , Hun Woo Kye , Geun Il Lee , Je Hoon Park , Jung Hwan Kim
发明人： Hee Bok Kang , Hun Woo Kye , Geun Il Lee , Je Hoon Park , Jung Hwan Kim
IPC分类号： G11C1122
CPC分类号： G11C11/22 , G11C8/06 , G11C8/18
摘要： Disclosed is an apparatus and method for driving a ferroelectric memory that can secure an enough read/write cycle time of a corresponding address during a chip is driven. In a driving circuit to generate an operation pulse for controlling operation of a ferroelectric chip, the ferroelectric memory driving apparatus includes an address latch block for latching a buffered address signal by a feedback cell operation pulse, an address transition detection summation value outputting block for generating an address transition detection pulse by detecting change of an address signal, and for outputting summation of address transition pulses generated by a plurality of addresses, a pulse width extension/control pulse generating block for extending a pulse width of the summation of the address transition pulses and outputting a chip control pulse by using an extended signal, and a cell operation pulse generating block for generating a cell operating pulse with a pulse width required on a read/write chip operation by using the chip control pulse, wherein in an active region of the cell operation pulse corresponding the address, an ATD signal of a different address is not generated.
摘要翻译：公开了一种用于驱动铁电存储器的装置和方法，其可以在驱动芯片期间确保相应地址的足够的读/写周期时间。在用于产生用于控制铁电芯片的操作的操作脉冲的驱动电路中，铁电存储器驱动装置包括用于通过反馈单元操作脉冲来锁存缓冲地址信号的地址锁存块，用于产生的地址转移检测求和值输出块通过检测地址信号的变化并输出由多个地址产生的地址转换脉冲的和的地址转换检测脉冲，用于扩展地址转换脉冲的和的脉冲宽度的脉宽扩展/控制脉冲发生块并通过使用扩展信号输出芯片控制脉冲;以及单元操作脉冲产生模块，用于通过使用芯片控制脉冲产生具有读/写芯片操作所需的脉冲宽度的单元操作脉冲，其中在单元操作脉冲对应的地址，一个ATD信号不同的地址 s不生成。

7. 发明授权

US06754095B2 Digital to analog converter including a ferroelectric non-volatile semiconductor memory, and method for converting digital data to analog data 失效
公开(公告)号：US06754095B2
公开(公告)日：2004-06-22
申请号：US10283313
申请日：2002-10-29
申请人： Masahiro Tanaka , Toshiyuki Nishihara , Yukihisa Tsuneda
发明人： Masahiro Tanaka , Toshiyuki Nishihara , Yukihisa Tsuneda
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A D/A converter capable of temporally controlling output of analog data during D/A conversion is provided. The digital to analog converter includes a ferroelectric non-volatile semiconductor memory. The ferroelectric non-volatile semiconductor memory includes a data line, a memory unit which has M memory cells, and M plate lines. Each of the memory cells includes a first electrode, a ferroelectric layer and a second electrode. The first electrode of the memory cells is shared in the memory unit and is connected to the data line. The second electrode of the mth memory cell is connected to the mth plate line. And the area of the ferroelectric layer of the memory cells varies among the memory cells.

8. 发明授权

US06721198B2 Nonvolatile ferroelectric memory device and driving method thereof 有权
标题翻译：非易失性铁电存储器件及其驱动方法
公开(公告)号：US06721198B2
公开(公告)日：2004-04-13
申请号：US10287823
申请日：2002-11-05
申请人： Hee Bok Kang
发明人： Hee Bok Kang
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A nonvolatile ferroelectric memory device includes a plurality of sense amplifiers, top and bottom cell array units disposed respectively at an upper and a lower sections, the top and bottom cell array units each including a plurality of unit cells, and being disposed symmetrically about the sense amplifiers. The nonvolatile ferroelectric memory device further includes at least one top reference array unit, at least one bottom reference array unit, a plurality of main bit lines connected to the unit cells of the top or bottom cell array unit, and a plurality of reference bit lines of the bottom or top cell array unit. Reference bit lines of the top or bottom cell array unit correspond to main bit lines of the bottom or top cell array unit disposed symmetrically about the sense amplifiers.
摘要翻译：非易失性铁电存储器件包括多个读出放大器，分别设置在上部和下部的顶部和底部单元阵列单元，每个顶部和底部单元阵列单元包括多个单位单元，并且围绕感觉对称地设置放大器非易失性铁电存储器件还包括至少一个顶部参考阵列单元，至少一个底部参考阵列单元，连接到顶部或底部单元阵列单元的单位单元的多个主位线以及多个参考位线的底部或顶部单元阵列单元。顶部或底部单元阵列单元的参考位线对应于围绕读出放大器对称设置的底部或顶部单元阵列单元的主位线。

9. 发明授权

US06700811B1 Random access memory device and method for driving a plate line segment therein 有权
标题翻译：用于在其中驱动板线段的随机存取存储器件和方法
公开(公告)号：US06700811B1
公开(公告)日：2004-03-02
申请号：US10235688
申请日：2002-09-04
申请人： Chi-Ming Weng , Chin-Hsi Lin
发明人： Chi-Ming Weng , Chin-Hsi Lin
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： A random access memory device includes a number of memory cells, with word lines, plate lines, and bit lines coupled to the memory cells. A switch, controlled by a word line, couples one end of the plate line to a first global plate line, while another switch, controlled by a second global plate line, couples the one end of the plate line to a reference voltage. The plate lines are charged by the first global plate line, which improves operational speed of the device and reduces loading of the word lines.
摘要翻译：随机存取存储器件包括多个存储器单元，其中字线，板线和耦合到存储器单元的位线。由字线控制的开关将板线的一端耦合到第一全局板线，而由第二全局板线控制的另一开关将板线的一端耦合到参考电压。板线由第一全局板线充电，这提高了设备的操作速度并减少了字线的负载。

10. 发明授权

US06665206B2 Array architecture for depletion mode ferroelectric memory devices 有权
公开(公告)号：US06665206B2
公开(公告)日：2003-12-16
申请号：US10205989
申请日：2002-07-26
申请人： Craig T. Salling
发明人： Craig T. Salling
IPC分类号： G11C1122
CPC分类号： H01L27/11502 , G11C11/22 , H01L27/1203
摘要： Depletion-mode ferroelectric transistors are adapted for use as non-volatile memory cells. Various embodiments have an array architecture such that two memory cells sharing the same bit line also share the same program line. Using this configuration, non-selected cells are readily supplied with gate/source voltages sufficient to maintain the cells in a deactivated state during read and write operations on selected cells.

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