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1. 发明申请

US20040252554A1 Nonvolatile SRAM memory cell 有权
标题翻译：非易失SRAM存储单元
公开(公告)号：US20040252554A1
公开(公告)日：2004-12-16
申请号：US10726263
申请日：2003-12-02
申请人： STMicroelectronics S.A.
发明人： Richard Fournel , Emmanuel Vincent , Sylvie Bruyere , Philippe Candelier , Francois Jacquet
IPC分类号： G11C016/04
CPC分类号： G11C14/00 , G11C17/14
摘要： An SRAM memory cell includes first and second inverters (14, 16) interconnected between first and second data nodes. Each inverter is formed from complementary MOS transistors (18, 20, 18null, 20null) connected in series between a DC voltage supply source and a grounding circuit (22). A circuit (28, 30) programs the MOS transistors by causing an irreversible degradation of a gate oxide layer of at least some of the transistors (18, 18null).
摘要翻译： SRAM存储单元包括在第一和第二数据节点之间互连的第一和第二反相器（14,16）。每个反相器由串联连接在DC电压源和接地电路（22）之间的互补MOS晶体管（18,20,18'，20'）形成。电路（28,30）通过使至少一些晶体管（18,18'）的栅极氧化层不可逆地退化来对MOS晶体管进行编程。

2. 发明申请

US20040196723A1 Dynamically mapping block-alterable memories 有权
标题翻译：动态映射块可变记忆
公开(公告)号：US20040196723A1
公开(公告)日：2004-10-07
申请号：US10408131
申请日：2003-04-07
发明人： Sean S. Eilert , Alec W. Smidt
IPC分类号： G11C008/00 , G11C016/04 , G11C011/34
CPC分类号： G11C16/08 , G11C8/12
摘要： In one embodiment, the present invention includes a method for reassigning a first address of a block-alterable memory to a second address of the block-alterable memory, where the second address corresponds to an updated available block. In such manner block-alterable memories may be dynamically mapped.
摘要翻译：在一个实施例中，本发明包括一种用于将块可改变存储器的第一地址重新分配给块可更改存储器的第二地址的方法，其中第二地址对应于更新的可用块。以这种方式，块可变存储器可以被动态映射。

3. 发明申请

US20040190342A1 DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators 失效
标题翻译：具有压制浮动栅极存储器的DRAM单元，低隧道势垒绝缘体
公开(公告)号：US20040190342A1
公开(公告)日：2004-09-30
申请号：US10819550
申请日：2004-04-07
申请人： Micron Technology, Inc.
发明人： Leonard Forbes
IPC分类号： G11C011/34 , G11C016/04 , G11C016/06
CPC分类号： H01L29/7881 , G11C11/404 , H01L27/10873 , H01L29/42324 , H01L29/511
摘要： Structures and methods for memory cells having a volatile and a non-volatile component in a single memory cell are provided. The memory cell includes a first source/drain region and a second source/drain region separated by a channel region in a substrate. A floating gate opposes the channel region and separated therefrom by a gate oxide. A control gate opposes the floating gate. The control gate is separated from the floating gate by a low tunnel barrier intergate insulator. The memory cell is adapted to operate in a first and a second mode of operation. The first mode of operation is a dynamic mode of operation and the second mode of operation is a repressed memory mode of operation.
摘要翻译：提供了在单个存储单元中具有易失性和非易失性成分的存储单元的结构和方法。存储单元包括由衬底中的沟道区分隔开的第一源极/漏极区域和第二源极/漏极区域。浮动栅极与沟道区域相对并且由栅极氧化物分离。控制门反对浮动门。控制栅极通过低隧道势垒栅极绝缘体与浮动栅极分离。存储器单元适于在第一和第二操作模式下操作。第一种操作模式是动态操作模式，第二种操作模式是压制存储器操作模式。

4. 发明申请

US20040179407A1 Nonvolatile semiconductor memory 有权
标题翻译：非易失性半导体存储器
公开(公告)号：US20040179407A1
公开(公告)日：2004-09-16
申请号：US10812080
申请日：2004-03-30
发明人： Masataka Kato , Tetsuo Adachi , Toshihiro Tanaka , Toshio Sasaki , Hitoshi Kume , Katsutaka Kimura
IPC分类号： G11C011/34 , G11C016/04 , G11C005/00
CPC分类号： G11C16/0416 , G11C8/08 , G11C16/10 , G11C16/12 , G11C16/16 , G11C16/34 , G11C16/3418 , G11C16/3427 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L29/7883 , H01L29/7885
摘要： Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte.
摘要翻译：公开了一种非易失性存储器系统，包括至少一个非易失性存储器，每个非易失性存储器具有多个非易失性存储单元和缓冲存储器; 以及耦合到所述非易失性存储器的控制装置。控制装置能够接收外部数据并将数据应用于非易失性存储器，并且使非易失性存储器能够操作程序操作，包括将接收到的数据存储到缓冲存储器并将保存在缓冲存储器中的数据存储到缓冲存储器中的非易失性存储单元。此外，控制装置能够在非易失性存储器在程序操作中操作时接收外部数据。此外，缓冲存储器能够接收与程序运行一次要存储的数据的数据长度相等的数据单位，数据长度大于1字节。

5. 发明申请

US20040160824A1 METHOD OF OPERATING A SEMICONDUCTOR MEMORY ARRAY OF FLOATING GATE MEMORY CELLS WITH BURIED BIT-LINE AND VERTICAL WORD LINE TRANSISTOR 审中-公开
标题翻译：操作带有双向直线和垂直字线晶体管的闸门存储器电池的半导体存储器阵列的方法
公开(公告)号：US20040160824A1
公开(公告)日：2004-08-19
申请号：US10776483
申请日：2004-02-10
发明人： Sohrab Kianian , Chih Hsin Wang
IPC分类号： G11C016/04
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42332 , H01L29/7885
摘要： A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate, and an array formed thereby, whereby each memory cell includes a trench formed into a surface of a semiconductor substrate, spaced apart source and drain regions with a channel region formed therebetween. The drain region is formed underneath the trench, and the channel region includes a first portion that extends substantially vertically along a sidewall of the trench and a second portion that extends substantially horizontally along the surface of the substrate. An electrically conductive floating gate is formed over and insulated from at least a portion of the channel region and a portion of the source region. An electrically conductive control gate is formed having a first portion disposed in the trench and a second portion formed over but insulated from the floating gate.
摘要翻译：一种在半导体衬底中形成浮置栅极存储单元的半导体存储器阵列的自对准方法，以及由此形成的阵列，由此每个存储单元包括形成在半导体衬底的表面中的沟槽，间隔开的源极和漏极区域具有沟道区域之间形成。漏极区域形成在沟槽下方，并且沟道区域包括沿着沟槽的侧壁基本垂直地延伸的第一部分和沿着衬底的表面基本水平延伸的第二部分。导电浮栅形成在沟道区的至少一部分和源极区的一部分之上并与之绝缘。导电控制栅极形成为具有设置在沟槽中的第一部分和形成在浮动栅极上但与浮动栅极绝缘的第二部分。

6. 发明申请

US20040156236A1 Programmable semiconductor memory 审中-公开
标题翻译：可编程半导体存储器
公开(公告)号：US20040156236A1
公开(公告)日：2004-08-12
申请号：US10771320
申请日：2004-02-05
申请人： Kabushiki Kaisha Toshiba
发明人： Fujio Masuoka
IPC分类号： G11C016/04
CPC分类号： H01L27/115 , G11C16/0483
摘要： Memory cells are divided into a plurality of series circuit units arranged in matrix fashion and comprising some memory cells connected in series. The memory cells each consist of non-volatile transistors provided with a control gate electrode, a floating gate electrode and an erase gate electrode. Bit lines to which one end of each of the series circuit units of the plurality of series circuit units arranged in one row are connected in common. Column lines are provided in common for the series circuit units that are arranged in one column and that are respectively connected to each control gate electrode of the memory cells constituting each of the series circuit unit. A voltage by which the selected non-volatile transistor works in a saturation state is applied to the control gate electrode of the selected transistor of a series circuit unit by a column line, thereby injecting hot electrons from the semiconductor substrate into the floating gate electrode. Another voltage by which the non-selected non-volatile transistor works in a non-saturation operation is applied to the gate electrodes of the remaining non-volatile transistors of the series circuit unit. By sequentially selecting memory cells in one series circuit unit, the sequential data writing operation is performed. The sequential data reading operation is performed in a similar manner.
摘要翻译：存储单元被分成以矩阵方式布置的多个串联电路单元，并且包括串联连接的一些存储器单元。每个存储单元由设置有控制栅电极，浮栅电极和擦除栅电极的非易失性晶体管组成。排列成一排的多个串联电路单元的串联电路单元的一端的共同连接的位线。对于排列成一列的串联电路单元共同地提供列线，并且分别连接到构成串联电路单元的每一个的存储单元的每个控制栅电极。所选择的非易失性晶体管工作在饱和状态的电压通过列线施加到串联电路单元的选定晶体管的控制栅电极，从而将热电子从半导体衬底注入到浮置栅电极中。未选择的非易失性晶体管工作在非饱和操作中的另一电压被施加到串联电路单元的剩余非易失性晶体管的栅电极。通过依次选择一个串联电路单元中的存储单元，执行顺序数据写入操作。以类似的方式执行顺序数据读取操作。

7. 发明申请

US20040151029A1 Programmable memory cell using charge trapping in a gate oxide 有权
标题翻译：可编程存储单元，使用栅极氧化物中的电荷俘获
公开(公告)号：US20040151029A1
公开(公告)日：2004-08-05
申请号：US10763136
申请日：2004-01-22
申请人： Micron Technology, Inc.
发明人： Leonard Forbes , Wendell P. Noble , Eugene H. Cloud
IPC分类号： G11C016/04
CPC分类号： G11C29/789 , G11C8/08 , G11C8/10 , G11C11/4087 , G11C16/0466 , H01L27/10897 , H01L27/11803 , H03K3/356008
摘要： An illustrative embodiment of the present invention includes a non-volatile, reprogrammable circuit switch. The circuit switch includes a metal oxide semiconductor field effect transistor (MOSFET) in a substrate. The MOSFET has a source region, a drain region, a channel region between the source and drain regions, and a gate separated from the channel region by a gate oxide. According to the teachings of the present invention, the MOSFET is a programmed MOSFET having a charge trapped in the gate oxide adjacent to the source region such that the channel region has a first voltage threshold region (Vt1) and a second voltage threshold region (Vt2).
摘要翻译：本发明的说明性实施例包括非易失性可再编程电路开关。电路开关包括在衬底中的金属氧化物半导体场效应晶体管（MOSFET）。 MOSFET具有源极区域，漏极区域，源极和漏极区域之间的沟道区域以及通过栅极氧化物与沟道区域分离的栅极。根据本发明的教导，MOSFET是编程的MOSFET，其具有与源极区相邻的栅极氧化物中的电荷，使得沟道区具有第一电压阈值区域（Vt1）和第二电压阈值区域（Vt2 ）。

8. 发明申请

US20040145948A1 Power-on reset circuit for erasing of split gate flash memory reference cells 失效
标题翻译：用于擦除分闸门闪存参考单元的上电复位电路
公开(公告)号：US20040145948A1
公开(公告)日：2004-07-29
申请号：US10755496
申请日：2004-01-12
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY
发明人： Shao-Yu Chou
IPC分类号： G11C016/04
CPC分类号： G11C16/28 , G11C16/16 , G11C16/30
摘要： In a standard Flash EPROM, a plurality of flash memory cells are arranged in an array of rows and columns. In order to determine the programming state of each cell, the magnitude of the cell read current is measured using a reference current source set to approximately 25uA. The memory cell being examined is connected with the drain wired to a positive voltage between about 1 to 2 volts. The source of the memory cell is connected to the current source. The control gate voltage is set to approximately 5V. An unprogrammed memory cell will have a drain current equal to that of the reference current source and the cell output will be slightly less than the drain voltage (logic 1). Under these conditions, a programmed memory cell, having a higher threshold voltage, will conduct only leakage currents. This results in the cell output being very close to ground potential (logic 0). Older technologies utilized fixed current sources for the reference current. In order to better track manufacturing tolerances, more recent technologies use a nullreference cellnull identical to the standard memory cell to form the reference current source. This reference cell is erased under the same conditions as a memory cell. Since the memory and reference cells are identical in geometry, their current characteristics will track regardless of manufacturing process variations. In order to maintain the proper state for the reference cells, they must be periodically erased. Most manufacturers erase the reference cells during a mass erase resulting in repeated high voltage stress equal to the memory array and decoder. The present invention reduces this high voltage stress using a method where a pulse initiating the erasure of the reference cells is generated upon application of power to the memory.
摘要翻译：在标准闪存EPROM中，多个闪存单元被排成行和列的阵列。为了确定每个单元的编程状态，使用设置为大约25uA的参考电流源来测量单元读取电流的大小。被检查的存储单元与被连接到约1至2伏之间的正电压的漏极连接。存储单元的源连接到当前源。控制栅极电压设置为大约5V。未编程的存储单元将具有等于参考电流源的漏极电流，并且单元输出将稍微小于漏极电压（逻辑1）。在这些条件下，具有较高阈值电压的编程存储器单元将仅传导泄漏电流。这导致单元输出非常接近地电位（逻辑0）。较老的技术使用固定电流源作为参考电流。为了更好地跟踪制造公差，更新的技术使用与标准存储器单元相同的“参考单元”来形成参考电流源。该参考单元在与存储单元相同的条件下被擦除。由于存储器和参考单元的几何形状相同，所以它们的电流特性将跟踪制造工艺的变化。为了保持参考单元的适当状态，必须定期擦除。大多数制造商在批量擦除期间擦除参考电池，导致重复的高电压应力等于存储器阵列和解码器。本发明使用这样的方法来降低这种高电压应力，其中在向存储器施加电力时产生引发参考单元擦除的脉冲。

9. 发明申请

US20040136239A1 Semiconductor integrated circuit device with erasable and programmable fuse memory 失效
标题翻译：具有可擦除和可编程保险丝存储器的半导体集成电路器件
公开(公告)号：US20040136239A1
公开(公告)日：2004-07-15
申请号：US10743385
申请日：2003-12-23
申请人： Kabushiki Kaisha Toshiba
发明人： Shigeru Atsumi , Masao Kuriyama , Akira Umezawa , Hironori Banba , Tadayuki Taura , Hidetoshi Saito
IPC分类号： G11C016/04
CPC分类号： G11C5/143 , G11C5/14 , G11C7/1045 , G11C16/26 , G11C16/30
摘要： A semiconductor integrated circuit device includes nonvolatile memory cell, a source of the cell receiving a ground potential, and a gate of the cell receiving a first control signal; a transistor, a source of the transistor receiving a drain potential of the cell, and a gate of the transistor receiving a second control signal; and a controller. The controller receives a third control signal generated upon detection of power-on and outputs the first and second control signals. A potential of the first control signal changes from the ground potential to a potential different from the ground potential, which is maintained during a first period of time, and a potential of the second control signal changes from the ground potential to a potential different from the ground potential, which is maintained during a second period of time.
摘要翻译：半导体集成电路器件包括非易失性存储单元，接收地电位的单元的源极和接收第一控制信号的单元的栅极; 晶体管，晶体管的源极，接收所述单元的漏极电位，以及所述晶体管的栅极接收第二控制信号; 和控制器。控制器接收在检测到电源接通时产生的第三控制信号，并输出第一和第二控制信号。第一控制信号的电位从接地电位变化到在第一时间段期间保持的接地电位不同的电位，并且第二控制信号的电位从地电势变为不同于地电位，在第二段时间内保持。

10. 发明申请

US20040125653A1 Seek window verify program system and method for a multilevel non-volatile memory integrated circuit system 有权
标题翻译：寻求窗口验证程序系统和方法，用于多级非易失性存储器集成电路系统
公开(公告)号：US20040125653A1
公开(公告)日：2004-07-01
申请号：US10737689
申请日：2003-12-15
发明人： Hieu Van Tran , Hung Q. Nguyen , Amitay Levi , Isao Nojima
IPC分类号： G11C016/04 , G11C011/34
CPC分类号： G11C13/0064 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C11/5678 , G11C13/0004 , G11C13/0026 , G11C13/0028 , G11C13/004 , G11C13/0069 , G11C16/08 , G11C16/10 , G11C16/24 , G11C16/28 , G11C27/005 , G11C2013/0054 , G11C2211/5634
摘要： A memory comprises a plurality of digital multilevel memory cells. A window of valid data voltages for accessing the said plurality of digital multilevel memory cells is detected. The window may be detected by incrementing a first programming voltage to program data in the plurality of memory cells and verifying whether the data in at least one of said plurality of memory cells is properly programmed. The incrementing and verifying may be repeated until data is verified to be properly programmed in one of said plurality of memory cells. The data in each memory cell of said plurality of memory cells is verified. The verification may be by incrementing a second programming voltage, and verifying whether data in each memory cell is properly programmed within a margin. The incrementing and verifying is repeated for each memory cell outside of the margin.
摘要翻译：存储器包括多个数字多电平存储器单元。检测用于访问所述多个数字多电平存储器单元的有效数据电压的窗口。可以通过将第一编程电压递增到多个存储器单元中的程序数据并且验证所述多个存储器单元中的至少一个中的数据是否被适当地编程来检测窗口。可以重复递增和验证直到数据被验证为在所述多个存储器单元之一中被适当地编程。验证所述多个存储单元的每个存储单元中的数据。验证可以通过增加第二编程电压，并验证每个存储器单元中的数据是否在一定的范围内被正确编程。对边缘外的每个存储单元重复递增和验证。

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