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1. 发明授权

US07692180B2 Layered composite film incorporating quantum dots as programmable dopants 失效
标题翻译：将量子点作为可编程掺杂剂的层状复合膜
公开(公告)号：US07692180B2
公开(公告)日：2010-04-06
申请号：US11145417
申请日：2005-06-03
申请人： Gary E. Snyder , Wil McCarthy
发明人： Gary E. Snyder , Wil McCarthy
IPC分类号： H01L31/00
CPC分类号： G11C19/38 , B82Y10/00 , B82Y20/00 , B82Y30/00 , G02F1/01725 , G02F1/3556 , G02F2001/01791 , H01L29/127 , H01L29/7888 , Y10S977/774
摘要： Quantum dots are positioned within a layered composite film to produce a plurality of real-time programmable dopants within the film. Charge carriers are driven into the quantum dots by energy in connected control paths. The charge carriers are trapped in the quantum dots through quantum confinement, such that the charge carriers form artificial atoms, which serve as dopants for the surrounding materials. The atomic number of each artificial atom is adjusted through precise variations in the voltage across the quantum dot that confines it. The change in atomic number alters the doping characteristics of the artificial atoms. The layered composite film is also configured as a shift register.
摘要翻译：量子点位于层状复合膜内以在膜内产生多个实时可编程掺杂物。电荷载体通过连接的控制路径中的能量被驱动到量子点中。电荷载流子通过量子限制被捕获在量子点中，使得载流子形成人造原子，其用作周围材料的掺杂剂。每个人造原子的原子数通过限制它的量子点两端的电压的精确变化来调节。原子序数的变化会改变人造原子的掺杂特性。分层复合膜也配置为移位寄存器。

2. 发明授权

US07465953B1 Positioning of nanoparticles and fabrication of single election devices 有权
标题翻译：纳米颗粒的定位和单电子器件的制造
公开(公告)号：US07465953B1
公开(公告)日：2008-12-16
申请号：US11412273
申请日：2006-04-27
申请人： Seong Jin Koh , Choong-Un Kim , Liang-Chieh Ma , Ramkumar Subramanian
发明人： Seong Jin Koh , Choong-Un Kim , Liang-Chieh Ma , Ramkumar Subramanian
IPC分类号： H01L29/06 , H01L21/8234
CPC分类号： H01L29/7613 , B82Y10/00 , G01N27/4146 , H01L21/28273 , H01L29/7888
摘要： The present invention includes single electron structures and devices comprising a substrate having an upper surface, one or more dielectric layers formed on the upper surface of the substrate and having at least one exposed portion, at least one monolayer of self-assembling molecules attracted to and in contact with the at least one exposed portion of only one of the one or more dielectric layers, one or more nanoparticles attracted to and in contact with the at least one monolayer, and at least one tunneling barrier in contact with the one or more nanoparticles. Typically, the single electron structure or device formed therefrom further comprise a drain, a gate and a source to provide single electron behavior, wherein there is a defined gap between source and drain and the one or more nanoparticles is positioned between the source and drain.
摘要翻译：本发明包括单电子结构和器件，其包括具有上表面的衬底，形成在衬底的上表面上的一个或多个电介质层，并具有至少一个暴露部分，至少一个单层的自组装分子被吸引到与所述一个或多个电介质层中的仅一个电介质层的至少一个暴露部分接触，一个或多个吸附于所述至少一个单层并与所述至少一个单层接触的纳米颗粒以及与所述一个或多个纳米颗粒接触的至少一个隧道势垒。通常，由此形成的单电子结构或器件还包括漏极，栅极和源极以提供单一电子行为，其中在源极和漏极之间存在限定的间隙，并且一个或多个纳米颗粒位于源极和漏极之间。

3. 发明申请

US20080256152A1 RANDOM NUMBER GENERATING DEVICE 有权
公开(公告)号：US20080256152A1
公开(公告)日：2008-10-16
申请号：US12143206
申请日：2008-06-20
申请人： Tetsufumi Tanamoto , Shinobu Fujita
发明人： Tetsufumi Tanamoto , Shinobu Fujita
IPC分类号： G06F7/58
CPC分类号： B82Y10/00 , G06F7/588 , H01L29/7888 , H04L9/0861
摘要： The objective is to provide a random number generating device having a smaller circuit size and a smaller value of output bias. The random number generating device includes a pair of first and second current paths arranged in parallel with each other, and a pair of first and second fine particles, which can mutually exchange charges, and are located in the vicinity of the first and second current paths.

4. 发明申请

US20080251783A1 RANDOM NUMBER GENERATING DEVICE 失效
标题翻译：随机数生成装置
公开(公告)号：US20080251783A1
公开(公告)日：2008-10-16
申请号：US12143124
申请日：2008-06-20
申请人： Tetsufumi TANAMOTO , Shinobu Fujita
发明人： Tetsufumi TANAMOTO , Shinobu Fujita
IPC分类号： H01L29/00
CPC分类号： B82Y10/00 , G06F7/588 , H01L29/7888 , H04L9/0861
摘要： The objective is to provide a random number generating device having a smaller circuit size and a smaller value of output bias. The random number generating device includes a pair of first and second current paths arranged in parallel with each other, and a pair of first and second fine particles, which can mutually exchange charges, and are located in the vicinity of the first and second current paths.
摘要翻译：目的是提供具有较小的电路尺寸和较小的输出偏压值的随机数产生装置。随机数产生装置包括彼此平行布置的一对第一和第二电流路径，以及一对可互相交换电荷并位于第一和第二电流路径附近的第一和第二细颗粒。

5. 发明授权

US07348670B2 Nanostructure, electronic device and method of manufacturing the same 失效
标题翻译：纳米结构，电子器件及其制造方法
公开(公告)号：US07348670B2
公开(公告)日：2008-03-25
申请号：US10533565
申请日：2003-12-12
申请人： Tohru Den , Kazuhiko Fukutani
发明人： Tohru Den , Kazuhiko Fukutani
IPC分类号： H01L23/48
CPC分类号： C30B29/60 , B82Y10/00 , B82Y30/00 , H01L29/42332 , H01L29/7888 , H01L2924/0002 , Y10S977/762 , Y10S977/893 , H01L2924/00
摘要： Cylinders having Al as a major constituent are orderly arrayed in an (Si, Ge) matrix. In a nanostructure in the form of a mixture film having a plurality of cylinders having Al as a major constituent, and a matrix region surrounding the plurality of cylinders and having Si and/or Ge as a major constituent, the total amount of Si and Ge is in the range from 20 to 70 atomic % in the mixture film, the cylinders are orderly arrayed, the diameter of the cylinders is in the range from 1 to 30 nm, and the interval between the cylinders is 30 nm or less.
摘要翻译：具有Al作为主要成分的气缸有序排列在（Si，Ge）基体中。在具有以Al为主要成分的多个圆柱体的混合物膜的形式的纳米结构体和围绕多个圆筒的基体区域中，具有Si和/或Ge作为主要成分的Si和Ge的总量在混合膜中为20〜70原子％的范围，气缸排列顺序，气缸的直径为1〜30nm，气缸间的间隔为30nm以下。

6. 发明授权

US07217620B2 Methods of forming silicon quantum dots and methods of fabricating semiconductor memory device using the same 有权
标题翻译：形成硅量子点的方法和使用其制造半导体存储器件的方法
公开(公告)号：US07217620B2
公开(公告)日：2007-05-15
申请号：US11027516
申请日：2004-12-30
申请人： Kwan-Ju Koh
发明人： Kwan-Ju Koh
IPC分类号： H01L21/336
CPC分类号： B82Y10/00 , H01L21/28273 , H01L29/127 , H01L29/42332 , H01L29/7888 , Y10S438/962
摘要： The disclosure provides methods of forming a silicon quantum dots for application in a semiconductor memory device. One example method includes sequentially forming a pad oxide film and a sacrificial insulation film on a silicon substrate; forming a wall layer by selectively etching the sacrificial insulation film; forming a spacer at the side wall of the wall layer; etching the silicon substrate as much as a predetermined thickness using the spacer as a mask, thereby forming a silicon pattern; forming a barrier film for burying the upper surface and the side surface of the silicon pattern; applying isotropic etching to the substrate using the barrier film as a mask; and oxidizing the isotropic etched substrate with thermal treatment.
摘要翻译：本公开提供了形成用于半导体存储器件的硅量子点的方法。一种示例性方法包括在硅衬底上顺序地形成衬垫氧化物膜和牺牲绝缘膜; 通过选择性地蚀刻牺牲绝缘膜形成壁层; 在壁层的侧壁上形成间隔物; 使用间隔物作为掩模将硅衬底蚀刻到预定厚度，从而形成硅图案; 形成用于掩埋硅图案的上表面和侧表面的阻挡膜; 使用阻挡膜作为掩模对基板进行各向同性蚀刻; 并用热处理氧化各向同性蚀刻的衬底。

7. 发明授权

US07138651B2 Logic apparatus and logic circuit 有权
公开(公告)号：US07138651B2
公开(公告)日：2006-11-21
申请号：US10893916
申请日：2004-07-20
申请人： Ken Uchida , Junji Koga , Ryuji Ohba
发明人： Ken Uchida , Junji Koga , Ryuji Ohba
IPC分类号： H01L29/06
CPC分类号： B82Y10/00 , H01L29/7888 , H01L49/006 , H03K19/08
摘要： A logic apparatus comprises a first single-electron device formed of a first conductive island, two first tunnel barriers with the first conductive island interposed, first and second electrodes, and a first charge storage region, and a second single-electron device formed of a second conductive island, second tunnel barriers with the second island interposed, third and fourth electrodes, and a second charge storage region, the first electrode of the first single-electron device being connected to the third electrode of the second single-electron device being connected to each other.

8. 发明申请

US20060011972A1 Non-volatile memory cell, memory cell arrangement and method for production of a non-volatile memory cell 有权
标题翻译：非易失性存储单元，存储单元布置和用于生产非易失性存储单元的方法
公开(公告)号：US20060011972A1
公开(公告)日：2006-01-19
申请号：US10533215
申请日：2003-10-29
申请人： Andrew Graham , Franz Hofmann , Wolfgang Honlein , Johannes Kretz , Franz Kreupl , Erhard Landoraf , Richard Luyken , Wolfgang Rosner , Thomas Schultz , Michael Specht
发明人： Andrew Graham , Franz Hofmann , Wolfgang Honlein , Johannes Kretz , Franz Kreupl , Erhard Landoraf , Richard Luyken , Wolfgang Rosner , Thomas Schultz , Michael Specht
IPC分类号： H01L29/792
CPC分类号： H01L29/7888 , B82Y10/00 , G11C13/025 , G11C2213/17 , H01L21/28282 , H01L21/84 , H01L27/115 , H01L27/11568 , H01L27/1203 , H01L27/28 , H01L29/66833 , H01L29/792 , H01L29/7926 , H01L51/0048 , H01L51/0052 , H01L51/057
摘要： A nonvolatile memory cell, memory cell arrangement, and method for production of a nonvolatile memory cell is disclosed. The nonvolatile memory cell includes a vertical field-effect transistor (FET). The FET contains a nanoelement arranged as a channel region and an electrically insulating layer. The electrically insulating layer at least partially surrounds the nanoelement and acts as a charge storage layer and as a gate-insulating layer. The electrically insulating layer is arranged such that electrical charge carriers may be selectively introduced into or removed from the electrically insulating layer and the electrical conductivity characteristics of the nanoelement may be influenced by the electrical charge carriers introduced into the electrically insulating layer.
摘要翻译：公开了一种用于制造非易失性存储单元的非易失性存储单元，存储单元布置和方法。非易失性存储单元包括垂直场效应晶体管（FET）。 FET包含布置为沟道区和电绝缘层的纳米元件。电绝缘层至少部分地包围纳米元件并充当电荷存储层和作为栅极绝缘层。电绝缘层被布置成使得电荷载体可以被选择性地引入到电绝缘层中或从电绝缘层移除，并且纳米元件的导电特性可能受到引入到电绝缘层中的电荷载流子的影响。

9. 发明申请

US20050142753A1 Methods of forming silicon quantum dots and methods of fabricating semiconductor memory device using the same 有权
标题翻译：形成硅量子点的方法和使用其制造半导体存储器件的方法
公开(公告)号：US20050142753A1
公开(公告)日：2005-06-30
申请号：US11027516
申请日：2004-12-30
申请人： Kwan-Ju Koh
发明人： Kwan-Ju Koh
IPC分类号： H01L21/8247 , H01L21/28 , H01L27/115 , H01L29/12 , H01L29/423 , H01L29/775 , H01L29/788 , H01L29/792 , H01L29/06 , H01L21/336 , H01L31/0328
CPC分类号： B82Y10/00 , H01L21/28273 , H01L29/127 , H01L29/42332 , H01L29/7888 , Y10S438/962
摘要： The disclosure provides methods of forming a silicon quantum dots for application in a semiconductor memory device. One example method includes sequentially forming a pad oxide film and a sacrificial insulation film on a silicon substrate; forming a wall layer by selectively etching the sacrificial insulation film; forming a spacer at the side wall of the wall layer; etching the silicon substrate as much as a predetermined thickness using the spacer as a mask, thereby forming a silicon pattern; forming a barrier film for burying the upper surface and the side surface of the silicon pattern; applying isotropic etching to the substrate using the barrier film as a mask; and oxidizing the isotropic etched substrate with thermal treatment.
摘要翻译：本公开提供了形成用于半导体存储器件的硅量子点的方法。一种示例性方法包括在硅衬底上顺序地形成衬垫氧化物膜和牺牲绝缘膜; 通过选择性地蚀刻牺牲绝缘膜形成壁层; 在壁层的侧壁上形成间隔物; 使用间隔物作为掩模将硅衬底蚀刻到预定厚度，从而形成硅图案; 形成用于掩埋硅图案的上表面和侧表面的阻挡膜; 使用阻挡膜作为掩模对基板进行各向同性蚀刻; 并用热处理氧化各向同性蚀刻的衬底。

10. 发明申请

US20050122775A1 Novolatile semiconductor memory device and manufacturing process of the same 失效
标题翻译：非易失性半导体存储器件及其制造工艺相同
公开(公告)号：US20050122775A1
公开(公告)日：2005-06-09
申请号：US11033142
申请日：2005-01-12
申请人： Mitsumasa Koyanagi , Masaaki Takata , Shinji Kondoh
发明人： Mitsumasa Koyanagi , Masaaki Takata , Shinji Kondoh
IPC分类号： C23C14/06 , H01L21/28 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/423 , H01L29/788 , H01L29/792 , G11C16/04
CPC分类号： H01L29/42348 , B82Y10/00 , H01L21/28273 , H01L21/28282 , H01L29/42332 , H01L29/66825 , H01L29/66833 , H01L29/7883 , H01L29/7888 , Y10S977/773 , Y10S977/936
摘要： There is provided a nonvolatile semiconductor memory device which can shorten data writing and erasing time, significantly improve the endurance characteristic and be activated with low power consumption. The nonvolatile semiconductor memory device comprises an insulating layer 3b with electric insulation, wherein, a charge retention layer 3 formed adjacent to a tunnel insulating film 2 contains nano-particles 3a comprised of a compound which is constituted from at least one single-element substance or chemical compound having a particle diameter of at most 5 nm functions as a floating gate, and which are independently dispersed with a density of from 10+12 to 10+14 particles per square centimeter.
摘要翻译：提供了可以缩短数据写入和擦除时间的非易失性半导体存储器件，显着提高耐久特性并以低功耗被激活。非易失性半导体存储器件包括具有电绝缘性的绝缘层3b，其中与隧道绝缘膜2相邻形成的电荷保持层3包含纳米粒子3a，该纳米粒子由由至少一种单元素物质构成的化合物或粒径为5nm以下的化合物作为浮栅，分别独立地分散，密度为10〜12个/ 10〜14个/ 平方厘米。

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