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41. 发明申请

US20060163738A1 Dual damascene structure and methods of forming the same 失效
标题翻译：双镶嵌结构及其形成方法
公开(公告)号：US20060163738A1
公开(公告)日：2006-07-27
申请号：US11333110
申请日：2006-01-17
申请人： Jun Seo , Jong-Hyuk Kim , Jong-Heui Song , Yung-Jun Kim , Min-Chul Chae
发明人： Jun Seo , Jong-Hyuk Kim , Jong-Heui Song , Yung-Jun Kim , Min-Chul Chae
IPC分类号： H01L23/48
CPC分类号： H01L21/76876 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/02645 , H01L21/28525 , H01L21/28562 , H01L21/76808 , H01L21/76831 , H01L21/76879 , H01L21/76895 , H01L29/66477 , Y10T428/24331
摘要： A dual damascene structure and a method of forming a dual damascene structure are disclosed. The dual damascene structure includes an insulation member, a single crystal member and a filling member. The insulation member has an opening having a dual damascene shape. The filling member is formed on a side face of the opening. The single crystal member contacts the filling member. The single crystal member fills up the opening. In order to form a dual damascene structure, an insulating member having an opening partially filled with a preliminary single crystal member is formed. The filling member is formed on a side face of the opening. The preliminary single crystal member epitaxially grows to fill up the opening. Because the filling member is positioned between the single crystal member and the insulation member, void formation may be reduced between the single crystal member and the insulation member.
摘要翻译：公开了一种双镶嵌结构和形成双镶嵌结构的方法。双镶嵌结构包括绝缘构件，单晶构件和填充构件。绝缘构件具有双镶嵌形状的开口。填充构件形成在开口的侧面上。单晶构件接触填充构件。单晶构件填充开口。为了形成双镶嵌结构，形成具有部分填充有初级单晶构件的开口的绝缘构件。填充构件形成在开口的侧面上。外延的初步单晶构件生长以填满开口。由于填充构件位于单晶构件和绝缘构件之间，所以在单晶构件和绝缘构件之间可能会减小空隙形成。

42. 发明申请

US20120285622A1 PLASMA DEVICE 审中-公开
标题翻译：等离子体装置
公开(公告)号：US20120285622A1
公开(公告)日：2012-11-15
申请号：US13419287
申请日：2012-03-13
申请人： Ji Man LIM , Jae-Woo Lee , Jun Seo , Dae Young Han
发明人： Ji Man LIM , Jae-Woo Lee , Jun Seo , Dae Young Han
IPC分类号： H01L21/3065
CPC分类号： H01J37/32091 , H01J37/32633
摘要： A plasma device includes: a reaction chamber; an upper electrode positioned upward in the reaction chamber; a lower electrode facing the upper electrode; a baffle plate enclosing the lower electrode and including a plurality of cutouts formed at the edge thereof, wherein a boundary line of the cutout is connected to a boundary line of the baffle plate, thereby forming a recess portion at the edge of the baffle plate. The cutouts of the baffle plate change the flow of the reactive gas in the chamber, helping achieve a more uniform etch.
摘要翻译：等离子体装置包括：反应室; 位于反应室中的上电极; 面向上电极的下电极; 封闭所述下电极并且在其边缘处形成有多个切口的挡板，其中所述切口的边界线连接到所述挡板的边界线，从而在所述挡板的边缘处形成凹部。挡板的切口改变了腔室中反应气体的流动，有助于实现更均匀的蚀刻。

43. 发明申请

US20110182111A1 ELECTROMECHANICAL SWITCH AND METHOD OF FORMING THE SAME 有权
标题翻译：电动开关及其形成方法
公开(公告)号：US20110182111A1
公开(公告)日：2011-07-28
申请号：US13082605
申请日：2011-04-08
申请人： Min-Sang Kim , Ji-Myoung Lee , Hyun-Jun Bae , Dong-Won Kim , Jun Seo , Weonwi Jang , Keun-Hwi Cho
发明人： Min-Sang Kim , Ji-Myoung Lee , Hyun-Jun Bae , Dong-Won Kim , Jun Seo , Weonwi Jang , Keun-Hwi Cho
IPC分类号： G11C11/24 , G11C11/50
CPC分类号： H01L28/40 , H01L27/10894
摘要： A memory device includes a storage node, a first electrode, and a second electrode formed in a memory cell, the storage node stores electrical charges, the first electrode comprising a first portion electrically connected to a second portion, the first portion moves to connect to the storage node when the second electrode is energized.
摘要翻译：存储装置包括存储节点，第一电极和形成在存储单元中的第二电极，所述存储节点存储电荷，所述第一电极包括电连接到第二部分的第一部分，所述第一部分移动以连接到当第二电极通电时的存储节点。

44. 发明申请

US20110095345A1 Methods of Fabricating Field Effect Transistors Having Protruded Active Regions 有权
标题翻译：制造具有突出活动区域的场效应晶体管的方法
公开(公告)号：US20110095345A1
公开(公告)日：2011-04-28
申请号：US12977811
申请日：2010-12-23
申请人： Ji-Young Lee , Jun Seo
发明人： Ji-Young Lee , Jun Seo
IPC分类号： H01L29/78
CPC分类号： H01L29/1037 , H01L21/76229 , H01L27/105 , H01L29/66621 , H01L29/7834
摘要： Provided are a field effect transistor, a method of manufacturing the same, and an electronic device including the field effect transistor. The field effect transistor may have a structure in which a double gate field effect transistor and a recess channel array transistor are formed in a single transistor in order to improve a short channel effect which occurs as field effect transistors become more highly integrated, a method of manufacturing the same, and an electronic device including the field effect transistor. The field effect transistor can exhibit stable device characteristics even when more highly integrated in such a manner that both the length and width of a channel increase and particularly the channel can be significantly long, and can be manufactured simply.
摘要翻译：提供了场效应晶体管，其制造方法以及包括场效应晶体管的电子器件。场效应晶体管可以具有在单个晶体管中形成双栅极场效应晶体管和凹槽沟道阵列晶体管的结构，以便改善随着场效应晶体管变得更高度集成而发生的短沟道效应，制造它们，以及包括场效应晶体管的电子器件。即使当以通道的长度和宽度都增加并且特别是通道可以显着长的方式更高度集成时，场效应晶体管也可以表现出稳定的器件特性，并且可以简单地制造。

45. 发明申请

US20100135064A1 SWITCH AND METHOD OF FORMING THE SAME 有权
标题翻译：开关及其形成方法
公开(公告)号：US20100135064A1
公开(公告)日：2010-06-03
申请号：US12533581
申请日：2009-07-31
申请人： Min-Sang Kim , Ji-Myoung Lee , Hyun-Jun Bae , Dong-Won Kim , Jun Seo , Yong-Hyun Kwon , Weon-Wi Jang , Keun-Hwi Cho
发明人： Min-Sang Kim , Ji-Myoung Lee , Hyun-Jun Bae , Dong-Won Kim , Jun Seo , Yong-Hyun Kwon , Weon-Wi Jang , Keun-Hwi Cho
IPC分类号： G11C11/24 , H01L27/108
CPC分类号： H01L27/101 , H01L27/108 , H01L27/10882 , H01L27/10885 , H01L27/10891 , H01L27/10897 , H01L28/40 , H01L29/685
摘要： A memory device includes a memory cell that includes a storage node, a first electrode, and a second electrode, the storage node stores an electrical charge, and the first electrode moves to connect to the storage node when the second electrode is energized.
摘要翻译：存储器件包括存储单元，其包括存储节点，第一电极和第二电极，所述存储节点存储电荷，并且当所述第二电极通电时，所述第一电极移动以连接到所述存储节点。

46. 发明授权

US07667221B2 Phase change memory devices and methods for fabricating the same 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US07667221B2
公开(公告)日：2010-02-23
申请号：US11708323
申请日：2007-02-21
申请人： Jong-Heui Song , Yong-Sun Ko , Jae-Seung Hwang , Jun Seo
发明人： Jong-Heui Song , Yong-Sun Ko , Jae-Seung Hwang , Jun Seo
IPC分类号： H01L47/00
CPC分类号： H01L45/1233 , H01L45/06 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1675 , Y10S438/90
摘要： In a phase change memory, an interlayer insulating layer is disposed on a substrate. A heater plug includes a lower portion disposed in a contact hole penetrating the interlayer insulating layer and an upper portion protruding upward over the top surface of the interlayer insulating layer. A phase change pattern is disposed on the interlayer insulating layer to cover the top surface and the side surface of the protruding portion of the heater plug. An insulating spacer is interposed between the phase change pattern and the side surface of the protruding portion of the heater plug. A capping electrode is disposed on the phase change pattern.
摘要翻译：在相变存储器中，在基板上设置层间绝缘层。加热器插头包括设置在穿过层间绝缘层的接触孔中的下部和在层间绝缘层的顶表面上方向上突出的上部。相变图案设置在层间绝缘层上，以覆盖加热器插头的突出部分的顶表面和侧表面。在相变图案和加热器插头的突出部分的侧表面之间插入绝缘间隔件。封盖电极设置在相变图案上。

47. 发明授权

US07534704B2 Thin layer structure and method of forming the same 失效
标题翻译：薄层结构及其形成方法
公开(公告)号：US07534704B2
公开(公告)日：2009-05-19
申请号：US11449839
申请日：2006-06-09
申请人： Jae-Kyu Ha , Jun Seo , Min-Chul Chae , Yong-Sun Ko , Young-Mi Lee , Jae-Seung Hwang
发明人： Jae-Kyu Ha , Jun Seo , Min-Chul Chae , Yong-Sun Ko , Young-Mi Lee , Jae-Seung Hwang
IPC分类号： H01L21/20
CPC分类号： H01L21/84 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/02647 , H01L21/02667 , H01L21/76262 , H01L27/1203
摘要： In a thin layer structure and a method of forming the same, a first preliminary insulation pattern is formed on a substrate and includes a first opening exposing the substrate. One or more preliminary seed patterns including single crystalline silicon are formed in the first opening. A second insulation layer is formed on the first preliminary insulation pattern and the one or more preliminary seed patterns. A second insulation pattern, a first insulation pattern and one or more seed patterns are formed by etching the first and second insulation layers and the one or more preliminary seed patterns. The second insulation pattern includes a second opening having a flat bottom portion. A single crystalline silicon pattern is formed in the second opening, wherein a central thickness of the single crystalline silicon pattern is substantially identical to a peripheral thickness thereof, thereby reducing or preventing a thinning defect in a semiconductor device.
摘要翻译：在薄层结构及其形成方法中，在基板上形成第一预备绝缘图案，并且包括暴露基板的第一开口。在第一开口中形成包括单晶硅的一种或多种初步种子图案。在第一预备绝缘图案和一个或多个初步种子图案上形成第二绝缘层。通过蚀刻第一和第二绝缘层和一个或多个初步种子图案来形成第二绝缘图案，第一绝缘图案和一个或多个种子图案。第二绝缘图案包括具有平坦底部的第二开口。在第二开口中形成单晶硅图案，其中单晶硅图案的中心厚度与其周边厚度基本相同，从而减少或防止半导体器件中的变薄缺陷。

48. 发明授权

US07531450B2 Method of fabricating semiconductor device having contact hole with high aspect-ratio 有权
标题翻译：制造具有高纵横比的接触孔的半导体器件的方法
公开(公告)号：US07531450B2
公开(公告)日：2009-05-12
申请号：US11759788
申请日：2007-06-07
申请人： Yun-Seung Kang , Jun Seo , Min-Chul Chae , Jae-Seung Hwang , Sung-Un Kwon , Woo-Jin Cho
发明人： Yun-Seung Kang , Jun Seo , Min-Chul Chae , Jae-Seung Hwang , Sung-Un Kwon , Woo-Jin Cho
IPC分类号： H01L21/44
CPC分类号： H01L27/11551 , H01L21/31144 , H01L21/743 , H01L27/0688 , H01L27/11526
摘要： Provided is a method of fabricating a semiconductor device having a contact hole with a high aspect-ratio. The method includes: sequentially forming a lower pattern and an upper layer on a semiconductor substrate; sequentially forming a lower mask layer and an upper mask layer on the upper layer; sequentially patterning the lower and upper mask layers to form a hole exposing a top surface of the upper layer on the lower pattern; using the upper mask layer as an etching mask to anisotropically etch the exposed top surface to form an upper contact hole exposing a top surface of the lower pattern; and using the lower mask layer as an etching mask to anisotropically etch the exposed lower pattern to form a lower contact hole in the lower pattern, the lower contact hole extending from the upper contact hole.
摘要翻译：提供一种制造具有高纵横比的接触孔的半导体器件的方法。该方法包括：在半导体衬底上依次形成下图案和上层; 在上层依次形成下掩模层和上掩模层; 顺序地图案化上下掩模层以形成暴露下图案上的上层的顶表面的孔; 使用上掩模层作为蚀刻掩模以各向异性地蚀刻暴露的顶表面以形成暴露下图案的顶表面的上接触孔; 并且使用下掩模层作为蚀刻掩模来各向异性蚀刻暴露的下图案以在下图案中形成下接触孔，下接触孔从上接触孔延伸。

49. 发明授权

US07531414B2 Method of manufacturing integrated circuit device including recessed channel transistor 失效
标题翻译：集成电路器件制造方法，包括凹陷沟道晶体管
公开(公告)号：US07531414B2
公开(公告)日：2009-05-12
申请号：US11956153
申请日：2007-12-13
申请人： Jong-Chul Park , Jun Seo , Tae-Hyuk Ahn , Hyuk-Jin Kwon , Jong-Heui Song , Dae-Keun Kang
发明人： Jong-Chul Park , Jun Seo , Tae-Hyuk Ahn , Hyuk-Jin Kwon , Jong-Heui Song , Dae-Keun Kang
IPC分类号： H01L21/31 , H01L21/336
CPC分类号： H01L29/66553 , H01L29/66621 , H01L29/7834
摘要： A method according to some embodiments of the invention includes defining an active region by forming a trench device isolation region on an integrated substrate, forming a mask pattern that exposes a channel sub-region of the active region and the trench device isolation region adjacent to the channel sub-region, etching the trench device isolation region, which is exposed by the mask pattern, to be recessed to a first depth using the mask pattern as an etch mask, etching the channel sub-region to form a gate trench having a second depth that is deeper than the first depth using the mask pattern as an etch mask, and forming a recess gate that fills the gate trench.
摘要翻译：根据本发明的一些实施例的方法包括通过在集成衬底上形成沟槽器件隔离区域来限定有源区域，形成掩模图案，其暴露有源区域的沟道子区域和与该区域相邻的沟槽器件隔离区域使用掩模图案作为蚀刻掩模蚀刻由掩模图案曝光的沟槽器件隔离区域，以凹陷到第一深度，蚀刻沟道子区域以形成栅极沟槽，栅极沟道具有第二深度比使用掩模图案的第一深度深的蚀刻掩模，以及形成填充栅极沟槽的凹槽。

50. 发明授权

US07524733B2 Asymmetric source/drain transistor employing selective epitaxial growth (SEG) layer and method of fabricating same 有权
标题翻译：采用选择性外延生长（SEG）层的不对称源极/漏极晶体管及其制造方法
公开(公告)号：US07524733B2
公开(公告)日：2009-04-28
申请号：US11735919
申请日：2007-04-16
申请人： Hyeoung-Won Seo , Nak-Jin Son , Du-Heon Song , Jun Seo
发明人： Hyeoung-Won Seo , Nak-Jin Son , Du-Heon Song , Jun Seo
IPC分类号： H01L21/76
CPC分类号： H01L29/66636 , H01L29/78 , Y10S438/942
摘要： According to some embodiments of the invention, a method includes preparing a semiconductor substrate having an active region, doping channel ions in the active region, forming a planarized selective epitaxial growth (SEG) layer in a predetermined region of the active region doped with the channel ions, sequentially forming a gate insulating layer, a gate conductive layer and a gate hard mask layer on the semiconductor substrate having the planarized SEG layer, forming a gate pattern crossing the active region by sequentially patterning the gate hard mask layer and the gate conductive layer, the planarized SEG layer being located at one side of the gate pattern, and forming source/drain regions by implanting impurity ions using the gate pattern as an ion implantation mask. Accordingly, there is provided an asymmetric source/drain transistor capable of preventing a leakage current by diffusing the channel ions into the SEG layer.
摘要翻译：根据本发明的一些实施例，一种方法包括制备具有有源区的半导体衬底，在有源区中掺杂沟道离子，在掺杂有沟道的有源区的预定区域中形成平面化选择性外延生长（SEG）层离子，在具有平坦化SEG层的半导体衬底上依次形成栅极绝缘层，栅极导电层和栅极硬掩模层，通过顺序构图栅极硬掩模层和栅极导电层形成与有源区交叉的栅极图案，平面化SEG层位于栅极图案的一侧，并且通过使用栅极图案作为离子注入掩模注入杂质离子来形成源极/漏极区域。因此，提供了一种不对称源/漏晶体管，其能够通过将沟道离子扩散到SEG层中来防止漏电流。

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