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1. 发明申请

US20050042833A1 Method of manufacturing integrated circuit device including recessed channel transistor 失效
标题翻译：集成电路器件制造方法，包括凹陷沟道晶体管
公开(公告)号：US20050042833A1
公开(公告)日：2005-02-24
申请号：US10902642
申请日：2004-07-28
申请人： Jong-Chul Park , Jun Seo , Tae-Hyuk Ahn , Hyuk-Jin Kwon , Jong-Heui Song , Dae-Keun Kang
发明人： Jong-Chul Park , Jun Seo , Tae-Hyuk Ahn , Hyuk-Jin Kwon , Jong-Heui Song , Dae-Keun Kang
IPC分类号： H01L21/336 , H01L21/4763 , H01L29/78
CPC分类号： H01L29/66553 , H01L29/66621 , H01L29/7834
摘要： A method according to some embodiments of the invention includes defining an active region by forming a trench device isolation region on an integrated substrate, forming a mask pattern that exposes a channel sub-region of the active region and the trench device isolation region adjacent to the channel sub-region, etching the trench device isolation region, which is exposed by the mask pattern, to be recessed to a first depth using the mask pattern as an etch mask, etching the channel sub-region to form a gate trench having a second depth that is deeper than the first depth using the mask pattern as an etch mask, and forming a recess gate that fills the gate trench.
摘要翻译：根据本发明的一些实施例的方法包括通过在集成衬底上形成沟槽器件隔离区域来限定有源区域，形成掩模图案，其暴露有源区域的沟道子区域和与该区域相邻的沟槽器件隔离区域使用掩模图案作为蚀刻掩模蚀刻由掩模图案曝光的沟槽器件隔离区域，以凹陷到第一深度，蚀刻沟道子区域以形成栅极沟槽，栅极沟道具有第二深度比使用掩模图案的第一深度深的蚀刻掩模，以及形成填充栅极沟槽的凹槽。

2. 发明授权

US07531414B2 Method of manufacturing integrated circuit device including recessed channel transistor 失效
标题翻译：集成电路器件制造方法，包括凹陷沟道晶体管
公开(公告)号：US07531414B2
公开(公告)日：2009-05-12
申请号：US11956153
申请日：2007-12-13
申请人： Jong-Chul Park , Jun Seo , Tae-Hyuk Ahn , Hyuk-Jin Kwon , Jong-Heui Song , Dae-Keun Kang
发明人： Jong-Chul Park , Jun Seo , Tae-Hyuk Ahn , Hyuk-Jin Kwon , Jong-Heui Song , Dae-Keun Kang
IPC分类号： H01L21/31 , H01L21/336
CPC分类号： H01L29/66553 , H01L29/66621 , H01L29/7834
摘要： A method according to some embodiments of the invention includes defining an active region by forming a trench device isolation region on an integrated substrate, forming a mask pattern that exposes a channel sub-region of the active region and the trench device isolation region adjacent to the channel sub-region, etching the trench device isolation region, which is exposed by the mask pattern, to be recessed to a first depth using the mask pattern as an etch mask, etching the channel sub-region to form a gate trench having a second depth that is deeper than the first depth using the mask pattern as an etch mask, and forming a recess gate that fills the gate trench.
摘要翻译：根据本发明的一些实施例的方法包括通过在集成衬底上形成沟槽器件隔离区域来限定有源区域，形成掩模图案，其暴露有源区域的沟道子区域和与该区域相邻的沟槽器件隔离区域使用掩模图案作为蚀刻掩模蚀刻由掩模图案曝光的沟槽器件隔离区域，以凹陷到第一深度，蚀刻沟道子区域以形成栅极沟槽，栅极沟道具有第二深度比使用掩模图案的第一深度深的蚀刻掩模，以及形成填充栅极沟槽的凹槽。

3. 发明授权

US07326619B2 Method of manufacturing integrated circuit device including recessed channel transistor 失效
标题翻译：集成电路器件制造方法，包括凹陷沟道晶体管
公开(公告)号：US07326619B2
公开(公告)日：2008-02-05
申请号：US10902642
申请日：2004-07-28
申请人： Jong-Chul Park , Jun Seo , Tae-Hyuk Ahn , Hyuk-Jin Kwon , Jong-Heui Song , Dae-Keun Kang
发明人： Jong-Chul Park , Jun Seo , Tae-Hyuk Ahn , Hyuk-Jin Kwon , Jong-Heui Song , Dae-Keun Kang
IPC分类号： H01L21/31 , H01L21/336
CPC分类号： H01L29/66553 , H01L29/66621 , H01L29/7834
摘要： A method according to some embodiments of the invention includes defining an active region by forming a trench device isolation region on an integrated substrate, forming a mask pattern that exposes a channel sub-region of the active region and the trench device isolation region adjacent to the channel sub-region, etching the trench device isolation region, which is exposed by the mask pattern, to be recessed to a first depth using the mask pattern as an etch mask, etching the channel sub-region to form a gate trench having a second depth that is deeper than the first depth using the mask pattern as an etch mask, and forming a recess gate that fills the gate trench.
摘要翻译：根据本发明的一些实施例的方法包括通过在集成衬底上形成沟槽器件隔离区域来限定有源区域，形成掩模图案，其暴露有源区域的沟道子区域和与该区域相邻的沟槽器件隔离区域使用掩模图案作为蚀刻掩模蚀刻由掩模图案曝光的沟槽器件隔离区域，以凹陷到第一深度，蚀刻沟道子区域以形成栅极沟槽，栅极沟道具有第二深度比使用掩模图案的第一深度深的蚀刻掩模，以及形成填充栅极沟槽的凹槽。

4. 发明授权

US08372198B2 Methods of forming dual damascene structures 失效
标题翻译：形成双镶嵌结构的方法
公开(公告)号：US08372198B2
公开(公告)日：2013-02-12
申请号：US12043576
申请日：2008-03-06
申请人： Jun Seo , Jong-Hyuk Kim , Jong-Heui Song , Yung-Jun Kim , Min-Chul Chae
发明人： Jun Seo , Jong-Hyuk Kim , Jong-Heui Song , Yung-Jun Kim , Min-Chul Chae
IPC分类号： C30B21/02
CPC分类号： H01L21/76876 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/02645 , H01L21/28525 , H01L21/28562 , H01L21/76808 , H01L21/76831 , H01L21/76879 , H01L21/76895 , H01L29/66477 , Y10T428/24331
摘要： A dual damascene structure and a method of forming a dual damascene structure are disclosed. The dual damascene structure includes an insulation member, a single crystal member and a filling member. The insulation member has an opening having a dual damascene shape. The filling member is formed on a side face of the opening. The single crystal member contacts the filling member. The single crystal member fills up the opening. In order to form a dual damascene structure, an insulating member having an opening partially filled with a preliminary single crystal member is formed. The filling member is formed on a side face of the opening. The preliminary single crystal member epitaxially grows to fill up the opening. Because the filling member is positioned between the single crystal member and the insulation member, void formation may be reduced between the single crystal member and the insulation member.
摘要翻译：公开了一种双镶嵌结构和形成双镶嵌结构的方法。双镶嵌结构包括绝缘构件，单晶构件和填充构件。绝缘构件具有双镶嵌形状的开口。填充构件形成在开口的侧面上。单晶构件接触填充构件。单晶构件填充开口。为了形成双镶嵌结构，形成具有部分填充有初级单晶构件的开口的绝缘构件。填充构件形成在开口的侧面上。外延的初步单晶构件生长以填满开口。由于填充构件位于单晶构件和绝缘构件之间，所以在单晶构件和绝缘构件之间可能会减小空隙形成。

5. 发明授权

US07358126B2 Dual damascene structure and methods of forming the same 失效
标题翻译：双镶嵌结构及其形成方法
公开(公告)号：US07358126B2
公开(公告)日：2008-04-15
申请号：US11333110
申请日：2006-01-17
申请人： Jun Seo , Jong-Hyuk Kim , Jong-Heui Song , Yung-Jun Kim , Min-Chul Chae
发明人： Jun Seo , Jong-Hyuk Kim , Jong-Heui Song , Yung-Jun Kim , Min-Chul Chae
IPC分类号： H01L23/43 , H01L21/4763
CPC分类号： H01L21/76876 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/02645 , H01L21/28525 , H01L21/28562 , H01L21/76808 , H01L21/76831 , H01L21/76879 , H01L21/76895 , H01L29/66477 , Y10T428/24331
摘要： A dual damascene structure and a method of forming a dual damascene structure are disclosed. The dual damascene structure includes an insulation member, a single crystal member and a filling member. The insulation member has an opening having a dual damascene shape. The filling member is formed on a side face of the opening. The single crystal member contacts the filling member. The single crystal member fills up the opening. In order to form a dual damascene structure, an insulating member having an opening partially filled with a preliminary single crystal member is formed. The filling member is formed on a side face of the opening. The preliminary single crystal member epitaxially grows to fill up the opening. Because the filling member is positioned between the single crystal member and the insulation member, void formation may be reduced between the single crystal member and the insulation member.
摘要翻译：公开了一种双镶嵌结构和形成双镶嵌结构的方法。双镶嵌结构包括绝缘构件，单晶构件和填充构件。绝缘构件具有双镶嵌形状的开口。填充构件形成在开口的侧面上。单晶构件接触填充构件。单晶构件填充开口。为了形成双镶嵌结构，形成具有部分填充有初级单晶构件的开口的绝缘构件。填充构件形成在开口的侧面上。外延的初步单晶构件生长以填满开口。由于填充构件位于单晶构件和绝缘构件之间，所以在单晶构件和绝缘构件之间可能会减小空隙形成。

6. 发明授权

US07745290B2 Methods of fabricating semiconductor device including fin-fet 失效
标题翻译：制造半导体器件的方法包括鳍片
公开(公告)号：US07745290B2
公开(公告)日：2010-06-29
申请号：US11773372
申请日：2007-07-03
申请人： Jun Seo , Jong-Heui Song , Jae-Seung Hwang , Min-Chul Chae , Woo-Jin Cho , Yun-Seung Kang , Young-Mi Lee
发明人： Jun Seo , Jong-Heui Song , Jae-Seung Hwang , Min-Chul Chae , Woo-Jin Cho , Yun-Seung Kang , Young-Mi Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/66795 , H01L29/7851
摘要： A method of fabricating a semiconductor device including a fin field effect transistor (Fin-FET) includes forming sacrificial bars on a semiconductor substrate, patterning the sacrificial bars to form sacrificial islands on the semiconductor substrate, forming a device isolation layer to fill a space between the sacrificial islands, selectively removing the sacrificial islands to expose the semiconductor substrate below the sacrificial islands, and anisotropically etching the exposed semiconductor substrate using the device isolation layer as an etch mask to form a recessed channel region. The recessed channel region allows the channel width and channel length of a transistor to be increased, thereby reducing the occurrence of short channel effects and narrow channel effects in highly integrated semiconductor devices.
摘要翻译：一种制造包括鳍状场效应晶体管（Fin-FET）的半导体器件的方法包括：在半导体衬底上形成牺牲棒，对牺牲棒进行构图以在半导体衬底上形成牺牲岛，形成器件隔离层以填充第牺牲岛，选择性地去除牺牲岛以将牺牲岛下方的半导体衬底暴露出来，并且使用器件隔离层作为蚀刻掩模来各向异性蚀刻暴露的半导体衬底以形成凹陷沟道区。凹陷沟道区域允许晶体管的沟道宽度和沟道长度增加，从而减少在高度集成的半导体器件中的短沟道效应和窄沟道效应的发生。

7. 发明申请

US20080149021A1 Methods of Forming Dual Damascene Structures 失效
标题翻译：形成双镶嵌结构的方法
公开(公告)号：US20080149021A1
公开(公告)日：2008-06-26
申请号：US12043576
申请日：2008-03-06
申请人： Jun Seo , Jong-Hyuk Kim , Jong-Heui Song , Yung-Jun Kim , Min-Chul Chae
发明人： Jun Seo , Jong-Hyuk Kim , Jong-Heui Song , Yung-Jun Kim , Min-Chul Chae
IPC分类号： C30B25/02
CPC分类号： H01L21/76876 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/02645 , H01L21/28525 , H01L21/28562 , H01L21/76808 , H01L21/76831 , H01L21/76879 , H01L21/76895 , H01L29/66477 , Y10T428/24331
摘要： A dual damascene structure and a method of forming a dual damascene structure are disclosed. The dual damascene structure includes an insulation member, a single crystal member and a filling member. The insulation member has an opening having a dual damascene shape. The filling member is formed on a side face of the opening. The single crystal member contacts the filling member. The single crystal member fills up the opening. In order to form a dual damascene structure, an insulating member having an opening partially filled with a preliminary single crystal member is formed. The filling member is formed on a side face of the opening. The preliminary single crystal member epitaxially grows to fill up the opening. Because the filling member is positioned between the single crystal member and the insulation member, void formation may be reduced between the single crystal member and the insulation member.
摘要翻译：公开了一种双镶嵌结构和形成双镶嵌结构的方法。双镶嵌结构包括绝缘构件，单晶构件和填充构件。绝缘构件具有双镶嵌形状的开口。填充构件形成在开口的侧面上。单晶构件接触填充构件。单晶构件填充开口。为了形成双镶嵌结构，形成具有部分填充有初级单晶构件的开口的绝缘构件。填充构件形成在开口的侧面上。外延的初步单晶构件生长以填满开口。由于填充构件位于单晶构件和绝缘构件之间，所以在单晶构件和绝缘构件之间可能会减小空隙形成。

8. 发明授权

US06239022B1 Method of fabricating a contact in a semiconductor device 有权
标题翻译：在半导体器件中制造接触的方法
公开(公告)号：US06239022B1
公开(公告)日：2001-05-29
申请号：US09604708
申请日：2000-06-27
申请人： Jun Seo , Woo-Sik Kim , Jong-Heui Song , Young-Woo Park
发明人： Jun Seo , Woo-Sik Kim , Jong-Heui Song , Young-Woo Park
IPC分类号： H01L214763
CPC分类号： H01L21/76885 , H01L21/31116 , H01L21/32137 , H01L21/7684
摘要： A method for forming a contact plug formed of polysilicon and a method for manufacturing a semiconductor device using the same are provided. The contact plug is formed by etching back polysilicon which fills a contact hole and is deposited on an interlayer dielectric film using a gas mixture of SF6, CHF3, and CF4, thus planarizing the polysilicon. Also, the contact plug can be made protrude above the interlayer dielectric film by etching the entire surface of the exposed interlayer dielectric film around the polysilicon contact plug formed by etching back the polysilicon. According to the present invention, the degree of planarization of the polysilicon contact plug is improved by etching back the polysilicon using the gas mixture of SF6, CHF3, and CF4. Furthermore, it is possible to prevent contact failure due to the depression of the contact plug by etching the entire surface of the interlayer dielectric film thus causing the contact plug to protrude above the interlayer dielectric film, thereby increasing the plug's contact area and reducing the contact failure.
摘要翻译：提供一种用于形成由多晶硅形成的接触插塞的方法以及使用其形成半导体器件的方法。接触插塞是通过将填充接触孔的多晶硅蚀刻回来形成的，并且使用SF6，CHF3和CF4的气体混合物沉积在层间电介质膜上，从而平坦化多晶硅。此外，通过蚀刻暴露的层间电介质膜的整个表面，接触插塞可以突出在层间电介质膜的上方，通过蚀刻多晶硅而形成的多晶硅接触插塞周围。根据本发明，通过使用SF6，CHF3和CF4的气体混合物蚀刻多晶硅来提高多晶硅接触插塞的平坦化程度。此外，可以通过蚀刻层间电介质膜的整个表面来防止接触插塞的接触故障，从而使接触插塞突出到层间电介质膜之上，从而增加插头的接触面积并减少接触失败。

9. 发明授权

US07667221B2 Phase change memory devices and methods for fabricating the same 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US07667221B2
公开(公告)日：2010-02-23
申请号：US11708323
申请日：2007-02-21
申请人： Jong-Heui Song , Yong-Sun Ko , Jae-Seung Hwang , Jun Seo
发明人： Jong-Heui Song , Yong-Sun Ko , Jae-Seung Hwang , Jun Seo
IPC分类号： H01L47/00
CPC分类号： H01L45/1233 , H01L45/06 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1675 , Y10S438/90
摘要： In a phase change memory, an interlayer insulating layer is disposed on a substrate. A heater plug includes a lower portion disposed in a contact hole penetrating the interlayer insulating layer and an upper portion protruding upward over the top surface of the interlayer insulating layer. A phase change pattern is disposed on the interlayer insulating layer to cover the top surface and the side surface of the protruding portion of the heater plug. An insulating spacer is interposed between the phase change pattern and the side surface of the protruding portion of the heater plug. A capping electrode is disposed on the phase change pattern.
摘要翻译：在相变存储器中，在基板上设置层间绝缘层。加热器插头包括设置在穿过层间绝缘层的接触孔中的下部和在层间绝缘层的顶表面上方向上突出的上部。相变图案设置在层间绝缘层上，以覆盖加热器插头的突出部分的顶表面和侧表面。在相变图案和加热器插头的突出部分的侧表面之间插入绝缘间隔件。封盖电极设置在相变图案上。

10. 发明申请

US20080152866A1 Dual Damascene Structure 审中-公开
标题翻译：双镶嵌结构
公开(公告)号：US20080152866A1
公开(公告)日：2008-06-26
申请号：US12043563
申请日：2008-03-06
申请人： Jun Seo , Jong-Hyuk Kim , Jong-Heui Song , Yung-Jun Kim , Min-Chul Chae
发明人： Jun Seo , Jong-Hyuk Kim , Jong-Heui Song , Yung-Jun Kim , Min-Chul Chae
IPC分类号： B32B3/10
CPC分类号： H01L21/76876 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/02645 , H01L21/28525 , H01L21/28562 , H01L21/76808 , H01L21/76831 , H01L21/76879 , H01L21/76895 , H01L29/66477 , Y10T428/24331
摘要： A dual damascene structure and a method of forming a dual damascene structure are disclosed. The dual damascene structure includes an insulation member, a single crystal member and a filling member. The insulation member has an opening having a dual damascene shape. The filling member is formed on a side face of the opening. The single crystal member contacts the filling member. The single crystal member fills up the opening. In order to form a dual damascene structure, an insulating member having an opening partially filled with a preliminary single crystal member is formed. The filling member is formed on a side face of the opening. The preliminary single crystal member epitaxially grows to fill up the opening. Because the filling member is positioned between the single crystal member and the insulation member, void formation may be reduced between the single crystal member and the insulation member.
摘要翻译：公开了一种双镶嵌结构和形成双镶嵌结构的方法。双镶嵌结构包括绝缘构件，单晶构件和填充构件。绝缘构件具有双镶嵌形状的开口。填充构件形成在开口的侧面上。单晶构件接触填充构件。单晶构件填充开口。为了形成双镶嵌结构，形成具有部分填充有初级单晶构件的开口的绝缘构件。填充构件形成在开口的侧面上。外延的初步单晶构件生长以填满开口。由于填充构件位于单晶构件和绝缘构件之间，所以在单晶构件和绝缘构件之间可能会减小空隙形成。

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