专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07531450B2 Method of fabricating semiconductor device having contact hole with high aspect-ratio 有权
标题翻译：制造具有高纵横比的接触孔的半导体器件的方法
公开(公告)号：US07531450B2
公开(公告)日：2009-05-12
申请号：US11759788
申请日：2007-06-07
申请人： Yun-Seung Kang , Jun Seo , Min-Chul Chae , Jae-Seung Hwang , Sung-Un Kwon , Woo-Jin Cho
发明人： Yun-Seung Kang , Jun Seo , Min-Chul Chae , Jae-Seung Hwang , Sung-Un Kwon , Woo-Jin Cho
IPC分类号： H01L21/44
CPC分类号： H01L27/11551 , H01L21/31144 , H01L21/743 , H01L27/0688 , H01L27/11526
摘要： Provided is a method of fabricating a semiconductor device having a contact hole with a high aspect-ratio. The method includes: sequentially forming a lower pattern and an upper layer on a semiconductor substrate; sequentially forming a lower mask layer and an upper mask layer on the upper layer; sequentially patterning the lower and upper mask layers to form a hole exposing a top surface of the upper layer on the lower pattern; using the upper mask layer as an etching mask to anisotropically etch the exposed top surface to form an upper contact hole exposing a top surface of the lower pattern; and using the lower mask layer as an etching mask to anisotropically etch the exposed lower pattern to form a lower contact hole in the lower pattern, the lower contact hole extending from the upper contact hole.
摘要翻译：提供一种制造具有高纵横比的接触孔的半导体器件的方法。该方法包括：在半导体衬底上依次形成下图案和上层; 在上层依次形成下掩模层和上掩模层; 顺序地图案化上下掩模层以形成暴露下图案上的上层的顶表面的孔; 使用上掩模层作为蚀刻掩模以各向异性地蚀刻暴露的顶表面以形成暴露下图案的顶表面的上接触孔; 并且使用下掩模层作为蚀刻掩模来各向异性蚀刻暴露的下图案以在下图案中形成下接触孔，下接触孔从上接触孔延伸。

2. 发明授权

US07745290B2 Methods of fabricating semiconductor device including fin-fet 失效
标题翻译：制造半导体器件的方法包括鳍片
公开(公告)号：US07745290B2
公开(公告)日：2010-06-29
申请号：US11773372
申请日：2007-07-03
申请人： Jun Seo , Jong-Heui Song , Jae-Seung Hwang , Min-Chul Chae , Woo-Jin Cho , Yun-Seung Kang , Young-Mi Lee
发明人： Jun Seo , Jong-Heui Song , Jae-Seung Hwang , Min-Chul Chae , Woo-Jin Cho , Yun-Seung Kang , Young-Mi Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/66795 , H01L29/7851
摘要： A method of fabricating a semiconductor device including a fin field effect transistor (Fin-FET) includes forming sacrificial bars on a semiconductor substrate, patterning the sacrificial bars to form sacrificial islands on the semiconductor substrate, forming a device isolation layer to fill a space between the sacrificial islands, selectively removing the sacrificial islands to expose the semiconductor substrate below the sacrificial islands, and anisotropically etching the exposed semiconductor substrate using the device isolation layer as an etch mask to form a recessed channel region. The recessed channel region allows the channel width and channel length of a transistor to be increased, thereby reducing the occurrence of short channel effects and narrow channel effects in highly integrated semiconductor devices.
摘要翻译：一种制造包括鳍状场效应晶体管（Fin-FET）的半导体器件的方法包括：在半导体衬底上形成牺牲棒，对牺牲棒进行构图以在半导体衬底上形成牺牲岛，形成器件隔离层以填充第牺牲岛，选择性地去除牺牲岛以将牺牲岛下方的半导体衬底暴露出来，并且使用器件隔离层作为蚀刻掩模来各向异性蚀刻暴露的半导体衬底以形成凹陷沟道区。凹陷沟道区域允许晶体管的沟道宽度和沟道长度增加，从而减少在高度集成的半导体器件中的短沟道效应和窄沟道效应的发生。

3. 发明授权

US07682450B2 Stacked semiconductor device and related method 有权
标题翻译：叠层半导体器件及相关方法
公开(公告)号：US07682450B2
公开(公告)日：2010-03-23
申请号：US11485323
申请日：2006-07-13
申请人： Yun-Seung Kang , Eun-Kuk Chung , Joon Kim , Jin-Hong Kim , Suk-Chul Bang
发明人： Yun-Seung Kang , Eun-Kuk Chung , Joon Kim , Jin-Hong Kim , Suk-Chul Bang
IPC分类号： C30B21/02
CPC分类号： H01L29/66772 , H01L21/02381 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/28525 , H01L21/76879 , H01L21/76898 , H01L21/8221 , H01L21/84 , H01L23/481 , H01L27/0688 , H01L2924/0002 , H01L2924/00
摘要： A stacked semiconductor device and a method for fabricating the stacked semiconductor device are disclosed. The stacked semiconductor device includes a first insulating interlayer having an opening that partially exposes a substrate, wherein the substrate includes single crystalline silicon, and a first seed pattern that fills the opening, wherein the first seed pattern has an upper portion disposed over the opening, and the upper portion is tapered away from the substrate. The stacked semiconductor device further includes a second insulating interlayer formed on the first insulating interlayer, wherein a trench that exposes the upper portion of the first seed pattern penetrates the second insulating interlayer, and a first single crystalline silicon structure that fills the trench.
摘要翻译：公开了一种叠层半导体器件及其制造方法。堆叠半导体器件包括具有部分地暴露衬底的开口的第一绝缘中间层，其中衬底包括单晶硅，以及填充开口的第一种子图案，其中第一种子图案具有设置在开口上方的上部，并且上部部分与基板成锥形。层叠半导体器件还包括形成在第一绝缘中间层上的第二绝缘中间层，其中暴露第一种子图案的上部的沟槽穿透第二绝缘夹层，以及填充沟槽的第一单晶硅结构。

4. 发明授权

US08419853B2 Stacked semiconductor device and related method 有权
标题翻译：叠层半导体器件及相关方法
公开(公告)号：US08419853B2
公开(公告)日：2013-04-16
申请号：US12623515
申请日：2009-11-23
申请人： Yun-Seung Kang , Eun-Kuk Chung , Joon Kim , Jin-Hong Kim , Suk-Chul Bang
发明人： Yun-Seung Kang , Eun-Kuk Chung , Joon Kim , Jin-Hong Kim , Suk-Chul Bang
IPC分类号： C30B21/04
CPC分类号： H01L29/66772 , H01L21/02381 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/28525 , H01L21/76879 , H01L21/76898 , H01L21/8221 , H01L21/84 , H01L23/481 , H01L27/0688 , H01L2924/0002 , H01L2924/00
摘要： A stacked semiconductor device and a method for fabricating the stacked semiconductor device are disclosed. The stacked semiconductor device includes a first insulating interlayer having an opening that partially exposes a substrate, wherein the substrate includes single crystalline silicon, and a first seed pattern that fills the opening, wherein the first seed pattern has an upper portion disposed over the opening, and the upper portion is tapered away from the substrate. The stacked semiconductor device further includes a second insulating interlayer formed on the first insulating interlayer, wherein a trench that exposes the upper portion of the first seed pattern penetrates the second insulating interlayer, and a first single crystalline silicon structure that fills the trench.
摘要翻译：公开了一种叠层半导体器件及其制造方法。堆叠半导体器件包括具有部分地暴露衬底的开口的第一绝缘中间层，其中衬底包括单晶硅和填充开口的第一种子图案，其中第一种子图案具有设置在开口上方的上部，并且上部部分与基板成锥形。层叠半导体器件还包括形成在第一绝缘中间层上的第二绝缘中间层，其中暴露第一种子图案的上部的沟槽穿透第二绝缘夹层，以及填充沟槽的第一单晶硅结构。

5. 发明授权

US07585757B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07585757B2
公开(公告)日：2009-09-08
申请号：US11446151
申请日：2006-06-05
申请人： Jong-Seon Ahn , Joon Kim , Jin-Hong Kim , Suk-Chul Bang , Eun-Kuk Chung , Hyung-Mo Yang , Chang-Yeon Yoo , Yun-Seung Kang , Kyung-Tae Jang
发明人： Jong-Seon Ahn , Joon Kim , Jin-Hong Kim , Suk-Chul Bang , Eun-Kuk Chung , Hyung-Mo Yang , Chang-Yeon Yoo , Yun-Seung Kang , Kyung-Tae Jang
IPC分类号： H01L21/44 , H01L23/48
CPC分类号： H01L23/53271 , H01L21/76802 , H01L21/76816 , H01L21/76829 , H01L21/76831 , H01L21/76832 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor device and method of manufacturing the semiconductor device, a punch-through prevention film pattern and a channel film pattern are formed on an insulation layer. The punch-through prevention pattern and the insulation layer may include nitride and oxide, respectively. The punch-through prevention pattern is located under the channel pattern.
摘要翻译：在制造半导体器件的半导体器件和方法中，在绝缘层上形成防穿透膜图案和沟道膜图案。穿透防止图案和绝缘层可以分别包括氮化物和氧化物。穿透防止图案位于通道图案下方。

6. 发明授权

US08058168B2 Method of fabricating semiconductor device having metal-semiconductor compound regions 有权
标题翻译：制造具有金属 - 半导体化合物区域的半导体器件的方法
公开(公告)号：US08058168B2
公开(公告)日：2011-11-15
申请号：US12656885
申请日：2010-02-18
申请人： Jong-Chul Park , Yun-Seung Kang
发明人： Jong-Chul Park , Yun-Seung Kang
IPC分类号： H01L21/44
CPC分类号： H01L29/7827 , H01L29/456 , H01L29/66666
摘要： Example embodiments relate to methods of fabricating a semiconductor device having a metal-semiconductor compound region. A method according to example embodiments may include forming semiconductor pillars on a semiconductor substrate. The semiconductor substrate between the semiconductor pillars may be etched to form a trench region. A dielectric isolation pattern partially filling the trench region may be formed, and dielectric sidewall spacers may be formed on sidewalls of the semiconductor pillars. Metal-semiconductor compound regions may be formed on sidewalls of a portion of the trench region that is not filled by the isolation pattern.
摘要翻译：示例性实施例涉及制造具有金属 - 半导体化合物区域的半导体器件的方法。根据示例性实施例的方法可以包括在半导体衬底上形成半导体柱。半导体柱之间的半导体衬底可以被蚀刻以形成沟槽区域。可以形成部分地填充沟槽区域的介电隔离图案，并且可以在半导体柱的侧壁上形成电介质侧壁间隔物。金属 - 半导体化合物区域可以形成在未被隔离图案填充的沟槽区域的一部分的侧壁上。

7. 发明申请

US20060281290A1 Semiconductor device and method of manufacturing the same 有权
公开(公告)号：US20060281290A1
公开(公告)日：2006-12-14
申请号：US11446151
申请日：2006-06-05
申请人： Jong-Seon Ahn , Joon Kim , Jin-Hong Kim , Suk-Chul Bang , Eun-Kuk Chung , Hyung-Mo Yang , Chang-Yeon Yoo , Yun-Seung Kang , Kyung-Tae Jang
发明人： Jong-Seon Ahn , Joon Kim , Jin-Hong Kim , Suk-Chul Bang , Eun-Kuk Chung , Hyung-Mo Yang , Chang-Yeon Yoo , Yun-Seung Kang , Kyung-Tae Jang
IPC分类号： H01L21/44 , H01L23/48
CPC分类号： H01L23/53271 , H01L21/76802 , H01L21/76816 , H01L21/76829 , H01L21/76831 , H01L21/76832 , H01L2924/0002 , H01L2924/00
摘要： In a semiconductor device and method of manufacturing the semiconductor device, a punch-through prevention film pattern and a channel film pattern are formed on an insulation layer. The punch-through prevention pattern and the insulation layer may include nitride and oxide, respectively. The punch-through prevention pattern is located under the channel pattern.

8. 发明申请

US20050287742A1 Method of manufacturing a nonvolatile semiconductor memory device 审中-公开
标题翻译：制造非易失性半导体存储器件的方法
公开(公告)号：US20050287742A1
公开(公告)日：2005-12-29
申请号：US11168178
申请日：2005-06-27
申请人： Yun-Seung Kang
发明人： Yun-Seung Kang
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/115
CPC分类号： H01L27/11521 , H01L27/115
摘要： In a method of manufacturing a nonvolatile semiconductor memory device, a preliminary floating gate is formed on a substrate having an active region and an inactive region that extend in a first direction. A dielectric layer and a control gate layer are formed on the substrate. A control gate, a dielectric layer, and a remaining pattern structure are formed by etching the control gate layer and the dielectric layer in a second direction until the preliminary floating gate is partially exposed. The floating gate is formed by etching the preliminary floating gate and the remaining pattern structure until the silicon substrate is exposed. The remaining pattern structure may prevent the isolation layer defining the inactive region from being damaged, thereby suppressing a leakage current in the nonvolatile semiconductor memory device.
摘要翻译：在制造非易失性半导体存储器件的方法中，在具有在第一方向上延伸的有源区和非活性区的衬底上形成预备浮栅。在基板上形成介电层和控制栅极层。通过在第二方向上蚀刻控制栅极层和电介质层直到预置浮栅部分露出来形成控制栅极，电介质层和剩余图案结构。通过蚀刻初步浮栅和剩余的图案结构直到硅衬底露出来形成浮栅。剩余的图案结构可以防止限定非活性区域的隔离层被损坏，从而抑制非易失性半导体存储器件中的漏电流。

9. 发明申请

US20100216289A1 Method of fabricating semiconductor device having metal-semiconductor compound regions 有权
标题翻译：制造具有金属 - 半导体化合物区域的半导体器件的方法
公开(公告)号：US20100216289A1
公开(公告)日：2010-08-26
申请号：US12656885
申请日：2010-02-18
申请人： Jong-Chul Park , Yun-Seung Kang
发明人： Jong-Chul Park , Yun-Seung Kang
IPC分类号： H01L21/336
CPC分类号： H01L29/7827 , H01L29/456 , H01L29/66666
摘要： Example embodiments relate to methods of fabricating a semiconductor device having a metal-semiconductor compound region. A method according to example embodiments may include forming semiconductor pillars on a semiconductor substrate. The semiconductor substrate between the semiconductor pillars may be etched to form a trench region. A dielectric isolation pattern partially filling the trench region may be formed, and dielectric sidewall spacers may be formed on sidewalls of the semiconductor pillars. Metal-semiconductor compound regions may be formed on sidewalls of a portion of the trench region that is not filled by the isolation pattern.
摘要翻译：示例性实施例涉及制造具有金属 - 半导体化合物区域的半导体器件的方法。根据示例性实施例的方法可以包括在半导体衬底上形成半导体柱。半导体柱之间的半导体衬底可以被蚀刻以形成沟槽区域。可以形成部分地填充沟槽区域的介电隔离图案，并且可以在半导体柱的侧壁上形成电介质侧壁间隔物。金属 - 半导体化合物区域可以形成在未被隔离图案填充的沟槽区域的一部分的侧壁上。

10. 发明申请

US20070023794A1 Stacked semiconductor device and related method 有权
标题翻译：叠层半导体器件及相关方法
公开(公告)号：US20070023794A1
公开(公告)日：2007-02-01
申请号：US11485323
申请日：2006-07-13
申请人： Yun-Seung Kang , Eun-Kuk Chung , Joon Kim , Jin-Hong Kim , Suk-Chul Bang
发明人： Yun-Seung Kang , Eun-Kuk Chung , Joon Kim , Jin-Hong Kim , Suk-Chul Bang
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L29/66772 , H01L21/02381 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/28525 , H01L21/76879 , H01L21/76898 , H01L21/8221 , H01L21/84 , H01L23/481 , H01L27/0688 , H01L2924/0002 , H01L2924/00
摘要： A stacked semiconductor device and a method for fabricating the stacked semiconductor device are disclosed. The stacked semiconductor device includes a first insulating interlayer having an opening that partially exposes a substrate, wherein the substrate includes single crystalline silicon, and a first seed pattern that fills the opening, wherein the first seed pattern has an upper portion disposed over the opening, and the upper portion is tapered away from the substrate. The stacked semiconductor device further includes a second insulating interlayer formed on the first insulating interlayer, wherein a trench that exposes the upper portion of the first seed pattern penetrates the second insulating interlayer, and a first single crystalline silicon structure that fills the trench.
摘要翻译：公开了一种叠层半导体器件及其制造方法。堆叠半导体器件包括具有部分地暴露衬底的开口的第一绝缘中间层，其中衬底包括单晶硅和填充开口的第一种子图案，其中第一种子图案具有设置在开口上方的上部，并且上部部分与基板成锥形。层叠半导体器件还包括形成在第一绝缘中间层上的第二绝缘中间层，其中暴露第一种子图案的上部的沟槽穿透第二绝缘夹层，以及填充沟槽的第一单晶硅结构。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式