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1. 发明授权

US07667221B2 Phase change memory devices and methods for fabricating the same 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US07667221B2
公开(公告)日：2010-02-23
申请号：US11708323
申请日：2007-02-21
申请人： Jong-Heui Song , Yong-Sun Ko , Jae-Seung Hwang , Jun Seo
发明人： Jong-Heui Song , Yong-Sun Ko , Jae-Seung Hwang , Jun Seo
IPC分类号： H01L47/00
CPC分类号： H01L45/1233 , H01L45/06 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1675 , Y10S438/90
摘要： In a phase change memory, an interlayer insulating layer is disposed on a substrate. A heater plug includes a lower portion disposed in a contact hole penetrating the interlayer insulating layer and an upper portion protruding upward over the top surface of the interlayer insulating layer. A phase change pattern is disposed on the interlayer insulating layer to cover the top surface and the side surface of the protruding portion of the heater plug. An insulating spacer is interposed between the phase change pattern and the side surface of the protruding portion of the heater plug. A capping electrode is disposed on the phase change pattern.
摘要翻译：在相变存储器中，在基板上设置层间绝缘层。加热器插头包括设置在穿过层间绝缘层的接触孔中的下部和在层间绝缘层的顶表面上方向上突出的上部。相变图案设置在层间绝缘层上，以覆盖加热器插头的突出部分的顶表面和侧表面。在相变图案和加热器插头的突出部分的侧表面之间插入绝缘间隔件。封盖电极设置在相变图案上。

2. 发明申请

US20070194294A1 Phase change memory devices and methods for fabricating the same 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US20070194294A1
公开(公告)日：2007-08-23
申请号：US11708323
申请日：2007-02-21
申请人： Jong-Heui Song , Yong-Sun Ko , Jae-Seung Hwang , Jun Seo
发明人： Jong-Heui Song , Yong-Sun Ko , Jae-Seung Hwang , Jun Seo
IPC分类号： H01L29/06
CPC分类号： H01L45/1233 , H01L45/06 , H01L45/126 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/1675 , Y10S438/90
摘要： In a phase change memory, an interlayer insulating layer is disposed on a substrate. A heater plug includes a lower portion disposed in a contact hole penetrating the interlayer insulating layer and an upper portion protruding upward over the top surface of the interlayer insulating layer. A phase change pattern is disposed on the interlayer insulating layer to cover the top surface and the side surface of the protruding portion of the heater plug. An insulating spacer is interposed between the phase change pattern and the side surface of the protruding portion of the heater plug. A capping electrode is disposed on the phase change pattern.
摘要翻译：在相变存储器中，在基板上设置层间绝缘层。加热器插头包括设置在穿过层间绝缘层的接触孔中的下部和在层间绝缘层的顶表面上方向上突出的上部。相变图案设置在层间绝缘层上，以覆盖加热器插头的突出部分的顶表面和侧表面。在相变图案和加热器插头的突出部分的侧表面之间插入绝缘间隔件。封盖电极设置在相变图案上。

3. 发明授权

US07745290B2 Methods of fabricating semiconductor device including fin-fet 失效
标题翻译：制造半导体器件的方法包括鳍片
公开(公告)号：US07745290B2
公开(公告)日：2010-06-29
申请号：US11773372
申请日：2007-07-03
申请人： Jun Seo , Jong-Heui Song , Jae-Seung Hwang , Min-Chul Chae , Woo-Jin Cho , Yun-Seung Kang , Young-Mi Lee
发明人： Jun Seo , Jong-Heui Song , Jae-Seung Hwang , Min-Chul Chae , Woo-Jin Cho , Yun-Seung Kang , Young-Mi Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/66795 , H01L29/7851
摘要： A method of fabricating a semiconductor device including a fin field effect transistor (Fin-FET) includes forming sacrificial bars on a semiconductor substrate, patterning the sacrificial bars to form sacrificial islands on the semiconductor substrate, forming a device isolation layer to fill a space between the sacrificial islands, selectively removing the sacrificial islands to expose the semiconductor substrate below the sacrificial islands, and anisotropically etching the exposed semiconductor substrate using the device isolation layer as an etch mask to form a recessed channel region. The recessed channel region allows the channel width and channel length of a transistor to be increased, thereby reducing the occurrence of short channel effects and narrow channel effects in highly integrated semiconductor devices.
摘要翻译：一种制造包括鳍状场效应晶体管（Fin-FET）的半导体器件的方法包括：在半导体衬底上形成牺牲棒，对牺牲棒进行构图以在半导体衬底上形成牺牲岛，形成器件隔离层以填充第牺牲岛，选择性地去除牺牲岛以将牺牲岛下方的半导体衬底暴露出来，并且使用器件隔离层作为蚀刻掩模来各向异性蚀刻暴露的半导体衬底以形成凹陷沟道区。凹陷沟道区域允许晶体管的沟道宽度和沟道长度增加，从而减少在高度集成的半导体器件中的短沟道效应和窄沟道效应的发生。

4. 发明申请

US20060286298A1 Thin layer structure and method of forming the same 失效
公开(公告)号：US20060286298A1
公开(公告)日：2006-12-21
申请号：US11449839
申请日：2006-06-09
申请人： Jae-Kyu Ha , Jun Seo , Min-Chul Chae , Yong-Sun Ko , Young-Mi Lee , Jae-Seung Hwang
发明人： Jae-Kyu Ha , Jun Seo , Min-Chul Chae , Yong-Sun Ko , Young-Mi Lee , Jae-Seung Hwang
IPC分类号： B05D5/00
CPC分类号： H01L21/84 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/02647 , H01L21/02667 , H01L21/76262 , H01L27/1203
摘要： In a thin layer structure and a method of forming the same, a first preliminary insulation pattern is formed on a substrate and includes a first opening exposing the substrate. One or more preliminary seed patterns including single crystalline silicon are formed in the first opening. A second insulation layer is formed on the first preliminary insulation pattern and the one or more preliminary seed patterns. A second insulation pattern, a first insulation pattern and one or more seed patterns are formed by etching the first and second insulation layers and the one or more preliminary seed patterns. The second insulation pattern includes a second opening having a flat bottom portion. A single crystalline silicon pattern is formed in the second opening, wherein a central thickness of the single crystalline silicon pattern is substantially identical to a peripheral thickness thereof, thereby reducing or preventing a thinning defect in a semiconductor device.

5. 发明授权

US07534704B2 Thin layer structure and method of forming the same 失效
标题翻译：薄层结构及其形成方法
公开(公告)号：US07534704B2
公开(公告)日：2009-05-19
申请号：US11449839
申请日：2006-06-09
申请人： Jae-Kyu Ha , Jun Seo , Min-Chul Chae , Yong-Sun Ko , Young-Mi Lee , Jae-Seung Hwang
发明人： Jae-Kyu Ha , Jun Seo , Min-Chul Chae , Yong-Sun Ko , Young-Mi Lee , Jae-Seung Hwang
IPC分类号： H01L21/20
CPC分类号： H01L21/84 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/02647 , H01L21/02667 , H01L21/76262 , H01L27/1203
摘要： In a thin layer structure and a method of forming the same, a first preliminary insulation pattern is formed on a substrate and includes a first opening exposing the substrate. One or more preliminary seed patterns including single crystalline silicon are formed in the first opening. A second insulation layer is formed on the first preliminary insulation pattern and the one or more preliminary seed patterns. A second insulation pattern, a first insulation pattern and one or more seed patterns are formed by etching the first and second insulation layers and the one or more preliminary seed patterns. The second insulation pattern includes a second opening having a flat bottom portion. A single crystalline silicon pattern is formed in the second opening, wherein a central thickness of the single crystalline silicon pattern is substantially identical to a peripheral thickness thereof, thereby reducing or preventing a thinning defect in a semiconductor device.
摘要翻译：在薄层结构及其形成方法中，在基板上形成第一预备绝缘图案，并且包括暴露基板的第一开口。在第一开口中形成包括单晶硅的一种或多种初步种子图案。在第一预备绝缘图案和一个或多个初步种子图案上形成第二绝缘层。通过蚀刻第一和第二绝缘层和一个或多个初步种子图案来形成第二绝缘图案，第一绝缘图案和一个或多个种子图案。第二绝缘图案包括具有平坦底部的第二开口。在第二开口中形成单晶硅图案，其中单晶硅图案的中心厚度与其周边厚度基本相同，从而减少或防止半导体器件中的变薄缺陷。

6. 发明申请

US20070210348A1 Phase-change memory device and methods of fabricating the same 审中-公开
标题翻译：相变存储器件及其制造方法
公开(公告)号：US20070210348A1
公开(公告)日：2007-09-13
申请号：US11643702
申请日：2006-12-22
申请人： JongHeui Song , Yong-Sun Ko , Jun Seo , Gyeo-Re Lee , Jae-Seung Hwang
发明人： JongHeui Song , Yong-Sun Ko , Jun Seo , Gyeo-Re Lee , Jae-Seung Hwang
IPC分类号： H01L47/00
CPC分类号： H01L45/06 , G11C2213/52 , H01L27/2436 , H01L45/1233 , H01L45/1273 , H01L45/143 , H01L45/144 , H01L45/1675
摘要： Example embodiments relate to a phase-change memory device and methods of fabricating the same. A phase-change memory device may include a lower electrode on a semiconductor substrate, a phase-change material layer on the lower electrode, a contact plug between the lower electrode and the phase-change material layer, wherein a first area of the contact plug in contact with a top of the lower electrode is greater than a second area of the contact plug in contact with a bottom of the phase-change material layer and an upper electrode on the phase-change material layer.
摘要翻译：示例实施例涉及相变存储器件及其制造方法。相变存储器件可以包括半导体衬底上的下电极，下电极上的相变材料层，下电极和相变材料层之间的接触插塞，其中接触插塞的第一区域与下电极的顶部接触大于与相变材料层的底部接触的接触插塞的第二区域和相变材料层上的上电极。

7. 发明申请

US20090090899A1 Phase change memory device and method of manufacturing the same 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US20090090899A1
公开(公告)日：2009-04-09
申请号：US12285531
申请日：2008-10-08
申请人： Young-Soo Lim , Yong-Sun Ko , Sung-Un Kwon , Jae-Seung Hwang
发明人： Young-Soo Lim , Yong-Sun Ko , Sung-Un Kwon , Jae-Seung Hwang
IPC分类号： H01L45/00
CPC分类号： H01L45/12 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1675
摘要： A method of manufacturing a phase change memory device includes forming at least one active device on a substrate, forming a bottom electrode electrically connected to the at least one active device, forming a phase change material layer and a top electrode on the bottom electrode, forming a capping layer on an upper surface of the top electrode and on side surfaces of the top electrode and phase change material layer, removing a portion of the capping layer overlapping the upper surface of the top electrode to define capping layer sidewall portions, forming an interlayer insulation film on the capping layer sidewall portions and on the top electrode, removing a portion of the interlayer insulation film from the top electrode to form a contact hole through the interlayer insulation film, and forming a contact plug in the contact hole.
摘要翻译：一种制造相变存储器件的方法包括在衬底上形成至少一个有源器件，形成与该至少一个有源器件电连接的底部电极，在底部电极上形成相变材料层和顶部电极，形成在顶部电极的上表面上以及顶部电极和相变材料层的侧表面上的覆盖层，去除与顶部电极的上表面重叠的覆盖层的一部分以限定覆盖层侧壁部分，形成中间层绝缘膜在顶盖电极上，从上电极去除一部分层间绝缘膜，以形成穿过层间绝缘膜的接触孔，并在接触孔中形成接触塞。

8. 发明申请

US20060292795A1 Method of manufacturing a flash memory device 失效
标题翻译：制造闪存装置的方法
公开(公告)号：US20060292795A1
公开(公告)日：2006-12-28
申请号：US11449848
申请日：2006-06-09
申请人： Sung-Un Kwon , Yong-Sun Ko , Jae-Seung Hwang
发明人： Sung-Un Kwon , Yong-Sun Ko , Jae-Seung Hwang
IPC分类号： H01L21/336
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11534 , H01L29/66825
摘要： In a method of manufacturing a flash memory device, an insulation layer pattern is formed on a substrate having cell and peripheral regions. Trenches formed in the substrate are converted into trench structures. A tunnel oxide layer is formed on the substrate. A space between the trench structures is filled with a first conductive layer. The trench structures are removed to form trench isolation structures and to convert the first conductive layer into a first conductive layer pattern. A dielectric layer is formed on the first conductive layer patterns and the trench isolation structures. An insulation layer is formed on the substrate in the peripheral region. A third conductive layer is formed on the second conductive layer, the insulation layer and the trench isolation layers. First and second gate structures are formed in the cell region and the peripheral region, respectively.
摘要翻译：在制造闪速存储器件的方法中，在具有单元和外围区域的衬底上形成绝缘层图案。在衬底中形成的沟槽被转换为沟槽结构。在衬底上形成隧道氧化物层。沟槽结构之间的空间填充有第一导电层。去除沟槽结构以形成沟槽隔离结构并将第一导电层转换成第一导电层图案。在第一导电层图案和沟槽隔离结构上形成介电层。在周边区域的基板上形成绝缘层。在第二导电层，绝缘层和沟槽隔离层上形成第三导电层。分别在单元区域和外围区域中形成第一和第二栅极结构。

9. 发明授权

US07659162B2 Phase change memory device and method of manufacturing the same 有权
标题翻译：相变存储器件及其制造方法
公开(公告)号：US07659162B2
公开(公告)日：2010-02-09
申请号：US12285531
申请日：2008-10-08
申请人： Young-Soo Lim , Yong-Sun Ko , Sung-Un Kwon , Jae-Seung Hwang
发明人： Young-Soo Lim , Yong-Sun Ko , Sung-Un Kwon , Jae-Seung Hwang
IPC分类号： H01L21/8242
CPC分类号： H01L45/12 , H01L27/2436 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1675
摘要： A method of manufacturing a phase change memory device includes forming at least one active device on a substrate, forming a bottom electrode electrically connected to the at least one active device, forming a phase change material layer and a top electrode on the bottom electrode, forming a capping layer on an upper surface of the top electrode and on side surfaces of the top electrode and phase change material layer, removing a portion of the capping layer overlapping the upper surface of the top electrode to define capping layer sidewall portions, forming an interlayer insulation film on the capping layer sidewall portions and on the top electrode, removing a portion of the interlayer insulation film from the top electrode to form a contact hole through the interlayer insulation film, and forming a contact plug in the contact hole.
摘要翻译：一种制造相变存储器件的方法包括在衬底上形成至少一个有源器件，形成与该至少一个有源器件电连接的底部电极，在底部电极上形成相变材料层和顶部电极，形成在顶部电极的上表面上和顶部电极和相变材料层的侧表面上的覆盖层，去除与顶部电极的上表面重叠的覆盖层的一部分以限定覆盖层侧壁部分，形成中间层绝缘膜在顶盖电极上，从上电极去除一部分层间绝缘膜，以形成穿过层间绝缘膜的接触孔，并在接触孔中形成接触塞。

10. 发明授权

US07452773B2 Method of manufacturing a flash memory device 失效
标题翻译：制造闪存装置的方法
公开(公告)号：US07452773B2
公开(公告)日：2008-11-18
申请号：US11449848
申请日：2006-06-09
申请人： Sung-Un Kwon , Yong-Sun Ko , Jae-Seung Hwang
发明人： Sung-Un Kwon , Yong-Sun Ko , Jae-Seung Hwang
IPC分类号： H01L21/336
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11534 , H01L29/66825
摘要： In a method of manufacturing a flash memory device, an insulation layer pattern is formed on a substrate having cell and peripheral regions. Trenches formed in the substrate are converted into trench structures. A tunnel oxide layer is formed on the substrate. A space between the trench structures is filled with a first conductive layer. The trench structures are removed to form trench isolation structures and to convert the first conductive layer into a first conductive layer pattern. A dielectric layer is formed on the first conductive layer patterns and the trench isolation structures. An insulation layer is formed on the substrate in the peripheral region. A third conductive layer is formed on the second conductive layer, the insulation layer and the trench isolation layers. First and second gate structures are formed in the cell region and the peripheral region, respectively.
摘要翻译：在制造闪速存储器件的方法中，在具有单元和外围区域的衬底上形成绝缘层图案。在衬底中形成的沟槽被转换为沟槽结构。在衬底上形成隧道氧化物层。沟槽结构之间的空间填充有第一导电层。去除沟槽结构以形成沟槽隔离结构并将第一导电层转换成第一导电层图案。在第一导电层图案和沟槽隔离结构上形成介电层。在周边区域的基板上形成绝缘层。在第二导电层，绝缘层和沟槽隔离层上形成第三导电层。分别在单元区域和外围区域中形成第一和第二栅极结构。

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