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41. 发明申请

US20090014786A1 Field Effect Transistors Having Protruded Active Regions and Methods of Fabricating Such Transistors 有权
标题翻译：具有突出活动区域的场效应晶体管和制造这种晶体管的方法
公开(公告)号：US20090014786A1
公开(公告)日：2009-01-15
申请号：US12170537
申请日：2008-07-10
申请人： Ji-Young Lee , Jun Seo
发明人： Ji-Young Lee , Jun Seo
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/1037 , H01L21/76229 , H01L27/105 , H01L29/66621 , H01L29/7834
摘要： Provided are a field effect transistor, a method of manufacturing the same, and an electronic device including the field effect transistor. The field effect transistor may have a structure in which a double gate field effect transistor and a recess channel array transistor are formed in a single transistor in order to improve a short channel effect which occurs as field effect transistors become more highly integrated, a method of manufacturing the same, and an electronic device including the field effect transistor. The field effect transistor can exhibit stable device characteristics even when more highly integrated in such a manner that both the length and width of a channel increase and particularly the channel can be significantly long, and can be manufactured simply.
摘要翻译：提供了场效应晶体管，其制造方法以及包括场效应晶体管的电子器件。场效应晶体管可以具有在单个晶体管中形成双栅极场效应晶体管和凹槽沟道阵列晶体管的结构，以便改善随着场效应晶体管变得更高度集成而发生的短沟道效应，制造它们，以及包括场效应晶体管的电子器件。即使当以通道的长度和宽度都增加并且特别是通道可以显着长的方式更高度集成时，场效应晶体管也可以表现出稳定的器件特性，并且可以简单地制造。

42. 发明申请

US20080113511A1 Method of forming fine patterns using double patterning process 有权
标题翻译：使用双重图案化工艺形成精细图案的方法
公开(公告)号：US20080113511A1
公开(公告)日：2008-05-15
申请号：US11730264
申请日：2007-03-30
申请人： Sang-joon Park , Yong-hyun Kwon , Jun Seo , Sung-il Cho , Chang-jin Kang , Jae-kyu Ha
发明人： Sang-joon Park , Yong-hyun Kwon , Jun Seo , Sung-il Cho , Chang-jin Kang , Jae-kyu Ha
IPC分类号： H01L21/311
CPC分类号： H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/76816 , H01L21/76897
摘要： A double pattern method of forming a plurality of contact holes in a material layer formed on a substrate is disclosed. The method forms a parallel plurality of first hard mask patterns separated by a first pitch in a first direction on the material layer, a self-aligned parallel plurality of second hard mask patterns interleaved with the first hard mask patterns and separated from the first hard mask patterns by a buffer layer to form composite mask patterns, and a plurality of upper mask patterns in a second direction intersecting the first direction to mask selected portions of the buffer layer in conjunction with the composite mask patterns. The method then etches non-selected portions of the buffer layer using the composite hard mask patterns and the upper mask patterns as an etch mask to form a plurality of hard mask holes exposing selected portions of the material layer, and then etches the selected portions of the material layer to form the plurality of contact holes.
摘要翻译：公开了一种在形成在基板上的材料层中形成多个接触孔的双重图案方法。该方法形成在材料层上沿第一方向以第一间距分开的平行多个第一硬掩模图案，与第一硬掩模图案交错并与第一硬掩模分离的自对准并行多个第二硬掩模图案通过缓冲层形成图案以形成复合掩模图案，以及与第一方向相交的第二方向的多个上掩模图案，以与复合掩模图案一起掩蔽缓冲层的选定部分。然后，该方法使用复合硬掩模图案和上掩模图案作为蚀刻掩模蚀刻缓冲层的未选择部分，以形成暴露材料层的选定部分的多个硬掩模孔，然后蚀刻所选择的部分所述材料层形成所述多个接触孔。

43. 发明授权

US07326619B2 Method of manufacturing integrated circuit device including recessed channel transistor 失效
标题翻译：集成电路器件制造方法，包括凹陷沟道晶体管
公开(公告)号：US07326619B2
公开(公告)日：2008-02-05
申请号：US10902642
申请日：2004-07-28
申请人： Jong-Chul Park , Jun Seo , Tae-Hyuk Ahn , Hyuk-Jin Kwon , Jong-Heui Song , Dae-Keun Kang
发明人： Jong-Chul Park , Jun Seo , Tae-Hyuk Ahn , Hyuk-Jin Kwon , Jong-Heui Song , Dae-Keun Kang
IPC分类号： H01L21/31 , H01L21/336
CPC分类号： H01L29/66553 , H01L29/66621 , H01L29/7834
摘要： A method according to some embodiments of the invention includes defining an active region by forming a trench device isolation region on an integrated substrate, forming a mask pattern that exposes a channel sub-region of the active region and the trench device isolation region adjacent to the channel sub-region, etching the trench device isolation region, which is exposed by the mask pattern, to be recessed to a first depth using the mask pattern as an etch mask, etching the channel sub-region to form a gate trench having a second depth that is deeper than the first depth using the mask pattern as an etch mask, and forming a recess gate that fills the gate trench.
摘要翻译：根据本发明的一些实施例的方法包括通过在集成衬底上形成沟槽器件隔离区域来限定有源区域，形成掩模图案，其暴露有源区域的沟道子区域和与该区域相邻的沟槽器件隔离区域使用掩模图案作为蚀刻掩模蚀刻由掩模图案曝光的沟槽器件隔离区域，以凹陷到第一深度，蚀刻沟道子区域以形成栅极沟槽，栅极沟道具有第二深度比使用掩模图案的第一深度深的蚀刻掩模，以及形成填充栅极沟槽的凹槽。

44. 发明授权

US07221023B2 Asymmetric source/drain transistor employing selective epitaxial growth (SEG) layer and method of fabricating same 失效
标题翻译：采用选择性外延生长（SEG）层的不对称源极/漏极晶体管及其制造方法
公开(公告)号：US07221023B2
公开(公告)日：2007-05-22
申请号：US11067410
申请日：2005-02-25
申请人： Hyeoung-Won Seo , Nak-Jin Son , Du-Heon Song , Jun Seo
发明人： Hyeoung-Won Seo , Nak-Jin Son , Du-Heon Song , Jun Seo
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L29/66636 , H01L29/78 , Y10S438/942
摘要： According to some embodiments of the invention, a method includes preparing a semiconductor substrate having an active region, doping channel ions in the active region, forming a planarized selective epitaxial growth (SEG) layer in a predetermined region of the active region doped with the channel ions, sequentially forming a gate insulating layer, a gate conductive layer and a gate hard mask layer on the semiconductor substrate having the planarized SEG layer, forming a gate pattern crossing the active region by sequentially patterning the gate hard mask layer and the gate conductive layer, the planarized SEG layer being located at one side of the gate pattern, and forming source/drain regions by implanting impurity ions using the gate pattern as an ion implantation mask. Accordingly, there is provided an asymmetric source/drain transistor capable of preventing a leakage current by diffusing the channel ions into the SEG layer.
摘要翻译：根据本发明的一些实施例，一种方法包括制备具有有源区的半导体衬底，在有源区中掺杂沟道离子，在掺杂有沟道的有源区的预定区域中形成平面化选择性外延生长（SEG）层离子，在具有平坦化SEG层的半导体衬底上依次形成栅极绝缘层，栅极导电层和栅极硬掩模层，通过顺序构图栅极硬掩模层和栅极导电层形成与有源区交叉的栅极图案，平面化SEG层位于栅极图案的一侧，并且通过使用栅极图案作为离子注入掩模注入杂质离子来形成源极/漏极区域。因此，提供了一种不对称源/漏晶体管，其能够通过将沟道离子扩散到SEG层中来防止漏电流。

45. 发明申请

US20070075325A1 High power light emitting diode package 审中-公开
标题翻译：大功率发光二极管封装
公开(公告)号：US20070075325A1
公开(公告)日：2007-04-05
申请号：US11541658
申请日：2006-10-03
申请人： Jong Baek , Je Park , Geun Ryo , Jun Seo , Jung Park
发明人： Jong Baek , Je Park , Geun Ryo , Jun Seo , Jung Park
IPC分类号： H01L33/00
CPC分类号： H01L25/0753 , F21K9/68 , H01L33/60 , H01L33/64 , H01L33/642 , H01L2224/48091 , H01L2224/48137 , H01L2924/00014 , H01L2924/00
摘要： The invention relates to a high power LED package having excellent light efficiency and heat dissipating characteristics. The LED package includes a base member, a reflector unit arranged on the base member and having a plurality of first reflectors, a plurality of LED chips mounted on the base member and surrounded by the first reflectors, and a connection unit arranged on the base member, for electrically connecting the LED chips to an outside. The reflector unit also includes a second reflector surrounding the first reflectors. The second reflector is arranged to surround the first reflectors in order to completely prevent any interference of emission lights and collect the emission lights together, thereby enabling excellent light efficiency. Furthermore, with the first reflectors surrounding the individual LED chips, it is possible to maximize heat dissipating efficiency of the lead frame, thereby stabilizing operating characteristics of the package.
摘要翻译：本发明涉及具有优异的光效率和散热特性的大功率LED封装。所述LED封装包括基底构件，布置在所述基底构件上并具有多个第一反射器的反射器单元，安装在所述基座构件上并被所述第一反射器包围的多个LED芯片，以及布置在所述基座构件上的连接单元，用于将LED芯片电连接到外部。反射器单元还包括围绕第一反射器的第二反射器。第二反射器被布置为围绕第一反射器以完全防止发射光的任何干扰并将发射光聚集在一起，从而实现优异的光效率。此外，通过围绕各个LED芯片的第一反射器，可以使引线框架的散热效率最大化，从而稳定封装的工作特性。

46. 发明申请

US20060163738A1 Dual damascene structure and methods of forming the same 失效
标题翻译：双镶嵌结构及其形成方法
公开(公告)号：US20060163738A1
公开(公告)日：2006-07-27
申请号：US11333110
申请日：2006-01-17
申请人： Jun Seo , Jong-Hyuk Kim , Jong-Heui Song , Yung-Jun Kim , Min-Chul Chae
发明人： Jun Seo , Jong-Hyuk Kim , Jong-Heui Song , Yung-Jun Kim , Min-Chul Chae
IPC分类号： H01L23/48
CPC分类号： H01L21/76876 , H01L21/02532 , H01L21/0262 , H01L21/02639 , H01L21/02645 , H01L21/28525 , H01L21/28562 , H01L21/76808 , H01L21/76831 , H01L21/76879 , H01L21/76895 , H01L29/66477 , Y10T428/24331
摘要： A dual damascene structure and a method of forming a dual damascene structure are disclosed. The dual damascene structure includes an insulation member, a single crystal member and a filling member. The insulation member has an opening having a dual damascene shape. The filling member is formed on a side face of the opening. The single crystal member contacts the filling member. The single crystal member fills up the opening. In order to form a dual damascene structure, an insulating member having an opening partially filled with a preliminary single crystal member is formed. The filling member is formed on a side face of the opening. The preliminary single crystal member epitaxially grows to fill up the opening. Because the filling member is positioned between the single crystal member and the insulation member, void formation may be reduced between the single crystal member and the insulation member.
摘要翻译：公开了一种双镶嵌结构和形成双镶嵌结构的方法。双镶嵌结构包括绝缘构件，单晶构件和填充构件。绝缘构件具有双镶嵌形状的开口。填充构件形成在开口的侧面上。单晶构件接触填充构件。单晶构件填充开口。为了形成双镶嵌结构，形成具有部分填充有初级单晶构件的开口的绝缘构件。填充构件形成在开口的侧面上。外延的初步单晶构件生长以填满开口。由于填充构件位于单晶构件和绝缘构件之间，所以在单晶构件和绝缘构件之间可能会减小空隙形成。

47. 发明申请

US20120285622A1 PLASMA DEVICE 审中-公开
标题翻译：等离子体装置
公开(公告)号：US20120285622A1
公开(公告)日：2012-11-15
申请号：US13419287
申请日：2012-03-13
申请人： Ji Man LIM , Jae-Woo Lee , Jun Seo , Dae Young Han
发明人： Ji Man LIM , Jae-Woo Lee , Jun Seo , Dae Young Han
IPC分类号： H01L21/3065
CPC分类号： H01J37/32091 , H01J37/32633
摘要： A plasma device includes: a reaction chamber; an upper electrode positioned upward in the reaction chamber; a lower electrode facing the upper electrode; a baffle plate enclosing the lower electrode and including a plurality of cutouts formed at the edge thereof, wherein a boundary line of the cutout is connected to a boundary line of the baffle plate, thereby forming a recess portion at the edge of the baffle plate. The cutouts of the baffle plate change the flow of the reactive gas in the chamber, helping achieve a more uniform etch.
摘要翻译：等离子体装置包括：反应室; 位于反应室中的上电极; 面向上电极的下电极; 封闭所述下电极并且在其边缘处形成有多个切口的挡板，其中所述切口的边界线连接到所述挡板的边界线，从而在所述挡板的边缘处形成凹部。挡板的切口改变了腔室中反应气体的流动，有助于实现更均匀的蚀刻。

48. 发明申请

US20110182111A1 ELECTROMECHANICAL SWITCH AND METHOD OF FORMING THE SAME 有权
标题翻译：电动开关及其形成方法
公开(公告)号：US20110182111A1
公开(公告)日：2011-07-28
申请号：US13082605
申请日：2011-04-08
申请人： Min-Sang Kim , Ji-Myoung Lee , Hyun-Jun Bae , Dong-Won Kim , Jun Seo , Weonwi Jang , Keun-Hwi Cho
发明人： Min-Sang Kim , Ji-Myoung Lee , Hyun-Jun Bae , Dong-Won Kim , Jun Seo , Weonwi Jang , Keun-Hwi Cho
IPC分类号： G11C11/24 , G11C11/50
CPC分类号： H01L28/40 , H01L27/10894
摘要： A memory device includes a storage node, a first electrode, and a second electrode formed in a memory cell, the storage node stores electrical charges, the first electrode comprising a first portion electrically connected to a second portion, the first portion moves to connect to the storage node when the second electrode is energized.
摘要翻译：存储装置包括存储节点，第一电极和形成在存储单元中的第二电极，所述存储节点存储电荷，所述第一电极包括电连接到第二部分的第一部分，所述第一部分移动以连接到当第二电极通电时的存储节点。

49. 发明申请

US20110095345A1 Methods of Fabricating Field Effect Transistors Having Protruded Active Regions 有权
标题翻译：制造具有突出活动区域的场效应晶体管的方法
公开(公告)号：US20110095345A1
公开(公告)日：2011-04-28
申请号：US12977811
申请日：2010-12-23
申请人： Ji-Young Lee , Jun Seo
发明人： Ji-Young Lee , Jun Seo
IPC分类号： H01L29/78
CPC分类号： H01L29/1037 , H01L21/76229 , H01L27/105 , H01L29/66621 , H01L29/7834
摘要： Provided are a field effect transistor, a method of manufacturing the same, and an electronic device including the field effect transistor. The field effect transistor may have a structure in which a double gate field effect transistor and a recess channel array transistor are formed in a single transistor in order to improve a short channel effect which occurs as field effect transistors become more highly integrated, a method of manufacturing the same, and an electronic device including the field effect transistor. The field effect transistor can exhibit stable device characteristics even when more highly integrated in such a manner that both the length and width of a channel increase and particularly the channel can be significantly long, and can be manufactured simply.
摘要翻译：提供了场效应晶体管，其制造方法以及包括场效应晶体管的电子器件。场效应晶体管可以具有在单个晶体管中形成双栅极场效应晶体管和凹槽沟道阵列晶体管的结构，以便改善随着场效应晶体管变得更高度集成而发生的短沟道效应，制造它们，以及包括场效应晶体管的电子器件。即使当以通道的长度和宽度都增加并且特别是通道可以显着长的方式更高度集成时，场效应晶体管也可以表现出稳定的器件特性，并且可以简单地制造。

50. 发明申请

US20100135064A1 SWITCH AND METHOD OF FORMING THE SAME 有权
标题翻译：开关及其形成方法
公开(公告)号：US20100135064A1
公开(公告)日：2010-06-03
申请号：US12533581
申请日：2009-07-31
申请人： Min-Sang Kim , Ji-Myoung Lee , Hyun-Jun Bae , Dong-Won Kim , Jun Seo , Yong-Hyun Kwon , Weon-Wi Jang , Keun-Hwi Cho
发明人： Min-Sang Kim , Ji-Myoung Lee , Hyun-Jun Bae , Dong-Won Kim , Jun Seo , Yong-Hyun Kwon , Weon-Wi Jang , Keun-Hwi Cho
IPC分类号： G11C11/24 , H01L27/108
CPC分类号： H01L27/101 , H01L27/108 , H01L27/10882 , H01L27/10885 , H01L27/10891 , H01L27/10897 , H01L28/40 , H01L29/685
摘要： A memory device includes a memory cell that includes a storage node, a first electrode, and a second electrode, the storage node stores an electrical charge, and the first electrode moves to connect to the storage node when the second electrode is energized.
摘要翻译：存储器件包括存储单元，其包括存储节点，第一电极和第二电极，所述存储节点存储电荷，并且当所述第二电极通电时，所述第一电极移动以连接到所述存储节点。

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