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31. 发明授权

US07843971B2 Modular expandable telecommunication system 有权
标题翻译：模块化可扩展电信系统
公开(公告)号：US07843971B2
公开(公告)日：2010-11-30
申请号：US09968915
申请日：2001-10-03
申请人： Xavier Penet
发明人： Xavier Penet
IPC分类号： H04J3/06
CPC分类号： H04Q1/10 , H04M7/006 , H04Q1/025 , H04Q3/625 , H04Q11/04 , H04Q2201/04 , H04Q2201/806 , H04Q2213/13003 , H04Q2213/13103 , H04Q2213/13106 , H04Q2213/13107 , H04Q2213/13178 , H04Q2213/13214 , H04Q2213/1322 , H04Q2213/13292 , H04Q2213/13299 , H04Q2213/13305 , H04Q2213/1332 , H04Q2213/13322 , H04Q2213/1336 , H04Q2213/13396
摘要： A modular expandable telecommunication system having a main cabinet and at least one expansion cabinet that are interconnected with each other to obtain an extended telecommunication system with increased connection possibilities for extensions and trunks. The main cabinet and each expansion cabinet have a transmission interface unit allowing connection of the expansion cabinet(s) to the main cabinet via a single transmission link conveying voice/data channels and low level signaling for mutual synchronization and clock recovery for all interconnected cabinets. The main cabinet has a master clock device, a CPU for running software applications and a DSP for routing the higher level messages issued by the CPU depending on the physical location of the expansion cabinet.
摘要翻译：一种具有主柜和至少一个扩展柜的模块化可扩展电信系统，其彼此互连以获得具有用于扩展和中继线的增加的连接可能性的扩展电信系统。主柜和每个扩展柜有一个传输接口单元，允许通过传输语音/数据通道的单个传输链路将扩展柜连接到主机柜，以及用于所有互连机柜的相互同步和时钟恢复的低电平信号。主柜具有主时钟设备，用于运行软件应用的CPU和用于根据扩展柜的物理位置路由CPU发出的较高级别消息的DSP。

32. 发明授权

US07697570B2 Method based on backboard transmitting time division multiplexing circuit data and a bridge connector 有权
标题翻译：基于背板传输时分复用电路数据和桥接器的方法
公开(公告)号：US07697570B2
公开(公告)日：2010-04-13
申请号：US10476407
申请日：2002-04-29
申请人： Zhenya Li , Guzheng Wu , Quan Yu , Shoubo Xie , Konggang Wei
发明人： Zhenya Li , Guzheng Wu , Quan Yu , Shoubo Xie , Konggang Wei
IPC分类号： H04J3/00
CPC分类号： H04Q11/04 , H04Q2213/13166 , H04Q2213/13214 , H04Q2213/13292 , H04Q2213/1336
摘要： A method for multi-path TDM data transmission includes: applying a plurality of high-speed serial lines to connect a center switch network board to a plurality of service boards; multiplexing multi-path TDM data from the center switch network board at transmitting side, and transmitting TDM data multiplexed in batch via one of the high-speed serial lines to one of the service boards; at receiving side, serial receiving the TDM data multiplexed and de-multiplexing the TDM data multiplexed to multiple TDM paths. The TDM bridge connector includes: a TDM high-speed serial transmitting adaptive circuit, and a TDM high-speed serial receiving adaptive circuit and a clock control circuit. The invention increases greatly transmission capacity and looses the requirement of clock synchronization, so the system reliability is greatly raised.
摘要翻译：一种用于多径TDM数据传输的方法包括：应用多条高速串行线路将中央交换网络板连接到多个业务板; 从发送侧的中心交换网络多路复用多路TDM数据，并通过一条高速串行线路批量发送TDM数据到其中一个业务板; 在接收侧，串行接收多路复用TDM多路复用TDM多路复用TDM数据的TDM数据并将其解复用。 TDM桥接器包括TDM高速串行传输自适应电路和TDM高速串行接收自适应电路和时钟控制电路。本发明大大提高了传输容量，不再需要时钟同步，因此系统可靠性大大提高。

33. 发明申请

US20080212574A1 Synchronization of Vodsl of Dslam Connected Only to Ethernet 有权
标题翻译： Dslam的Vodsl的同步仅连接到以太网
公开(公告)号：US20080212574A1
公开(公告)日：2008-09-04
申请号：US11913778
申请日：2005-05-11
申请人： Tore Andre , Anders Lindblad , Kenneth Johansson
发明人： Tore Andre , Anders Lindblad , Kenneth Johansson
IPC分类号： H04L12/66
CPC分类号： H03L7/091 , H03L7/0993 , H03L7/181 , H04J3/0632 , H04J3/0664 , H04J3/0697 , H04Q2213/13039 , H04Q2213/13199 , H04Q2213/13214 , H04Q2213/13292 , H04Q2213/13297 , H04Q2213/13298 , H04Q2213/1336 , H04Q2213/13389
摘要： A forwarding unit such as a DSLAM (8) receives (21) Ethernet packets and forwards information therein on digital subscriber lines (27). For forwarding voice information of received Ethernet packets a reference clock signal is generated by a clock device (28) and provided to modems (23) for the digital subscriber lines. The clock device includes an extraction unit (29) for selecting at least one stream of received Ethernet packets, and a clock signal generating unit, configured as an adaptive clock unit (31), for generating a reference clock signal according to arrival times of packet in selected packet stream or streams. The reference clock signal can be provided to time reference units (25) in the modems. The extraction unit can analyze received Ethernet packets to find streams of packets from one destination to one user, the packets of each of the streams carrying real time information belonging to a real time service and then select one or more streams to be used by the adaptive clock unit.
摘要翻译：诸如DSLAM（8）的转发单元在数字用户线路（27）上接收（21）以太网分组并转发其中的信息。为了转发接收到的以太网分组的语音信息，由时钟设备（28）产生参考时钟信号，并提供给用于数字用户线路的调制解调器（23）。时钟装置包括用于选择接收到的以太网分组的至少一个流的提取单元（29）和配置为自适应时钟单元（31）的时钟信号生成单元，用于根据分组的到达时间生成参考时钟信号在选定的分组流或流中。参考时钟信号可以提供给调制解调器中的时间基准单元（25）。提取单元可以分析接收到的以太网分组，以从一个目的地到一个用户查找分组的流，每个流的分组承载属于实时业务的实时信息，然后选择一个或多个要由自适应时钟单元

34. 发明授权

US07260092B2 Time slot interchanger 有权
标题翻译：时隙交换器
公开(公告)号：US07260092B2
公开(公告)日：2007-08-21
申请号：US09761539
申请日：2001-01-16
申请人： William J. Dally
发明人： William J. Dally
IPC分类号： H04L12/50
CPC分类号： H04Q11/06 , H04J2203/0003 , H04Q3/68 , H04Q11/0478 , H04Q2213/13076 , H04Q2213/13103 , H04Q2213/13213 , H04Q2213/13214 , H04Q2213/13292 , H04Q2213/13322 , H04Q2213/1336 , H04Q2213/13367 , H04Q2213/13393
摘要： A digital cross connect comprises plural switching stages. Each stage has plural switches which receive plural frames of time multiplexed input data and which switch the data in time and space. Configurations of the switches change in frame synchronization at the start of a synchronized data frame. Both the configuration data and a frame clock may be propagated through the plural stages from a master switch. First and last stages of the digital cross connect may be implemented on common chips having two framing time bases. Data may be aligned to a global frame clock and interchanged using a single random access memory in a time slot interchanger. The write address to the random access memory is generated from a local frame counter keyed to the input data frame while a read address is transformed from a global frame counter.
摘要翻译：数字交叉连接包括多个开关级。每个级具有多个开关，其接收多帧时间复用输入数据，并且在时间和空间上切换数据。在同步数据帧开始时，交换机的配置将在帧同步中改变。配置数据和帧时钟都可以从主交换机通过多级传播。可以在具有两个成帧时基的共同芯片上实现数字交叉连接的第一和最后阶段。数据可以与全局帧时钟对准，并且在时隙交换器中使用单个随机存取存储器互换。随机访问存储器的写入地址是从与输入数据帧相关联的本地帧计数器生成的，同时从全局帧计数器转换读地址。

35. 发明授权

US07079553B2 Method and system for embedding a first clock signal phase within a second signal 有权
公开(公告)号：US07079553B2
公开(公告)日：2006-07-18
申请号：US10122506
申请日：2002-04-15
申请人： John H. Bond , Robert S. Gammenthaler, Jr. , James C. McKinley
发明人： John H. Bond , Robert S. Gammenthaler, Jr. , James C. McKinley
IPC分类号： H04J3/07
CPC分类号： H04Q3/0025 , H04J3/0691 , H04Q2213/13176 , H04Q2213/13214
摘要： A technique for embedding a first clock phase within a second signal is described. In one embodiment, the invention comprises a method of embedding a phase of a first signal within a second signal comprising the steps of monitoring a first signal for a frame event, responsive to detection of a frame event in the first clock signal, determining a position of the frame event relative to a current segment of a second signal, and embedding in the current segment of the second signal a value representative of the relative position of the detected frame event.

36. 发明申请

US20060093130A1 Automated access network cross-connect system 审中-公开
标题翻译：自动接入网交叉连接系统
公开(公告)号：US20060093130A1
公开(公告)日：2006-05-04
申请号：US11261826
申请日：2005-10-28
申请人： Timothy Kelliher
发明人： Timothy Kelliher
IPC分类号： H04M3/00 , H04M5/00 , H04M1/00 , H04M7/00 , H04M9/00
CPC分类号： H04Q3/5455 , H04Q11/0067 , H04Q2011/0033 , H04Q2011/0039 , H04Q2213/1302 , H04Q2213/1304 , H04Q2213/13076 , H04Q2213/13106 , H04Q2213/13141 , H04Q2213/13214 , H04Q2213/13292 , H04Q2213/13302 , H04Q2213/1332 , H04Q2213/13322 , H04Q2213/1336
摘要： A system for automating cross connections in an access network. The automated cross connect system comprises of a plurality of upstream line interface circuits adapted for connection to upstream communication links, and a plurality of downstream line interface circuits adapted for connection to downstream communication links. The upstream and downstream line interface circuits are interconnected by an automated cross connect switch that selectively couples particular upstream line interface circuits to particular downstream line interface circuits, in response to routing commands sent from a command center. Thus, the automated cross connect system selectively establishes a bi-directional communication path between the upstream line interface circuits and the downstream line interface circuits, thereby providing a communication path between a selected upstream communication link and downstream communication link. The automated cross connect switch may be implemented in either a space or time multiplexing devices, such as a physical layer router, which comprises an array of cross connected multiplexers, or a time domain multiplexer switch, which composes an array of serializers connected to a time division multiplexed bus.
摘要翻译：用于在接入网络中自动化交叉连接的系统。自动交叉连接系统包括适于连接到上游通信链路的多个上游线路接口电路以及适于连接到下游通信链路的多个下游线路接口电路。上游和下游线路接口电路通过自动交叉连接交换机互连，自动交叉连接交换机响应于从命令中心发送的路由命令，将特定的上游线路接口电路选择性地耦合到特定的下游线路接口电路。因此，自动交叉连接系统选择性地在上游线路接口电路和下游线路接口电路之间建立双向通信路径，从而在所选择的上游通信链路和下游通信链路之间提供通信路径。自动交叉连接开关可以在空间或时间复用设备中实现，例如物理层路由器，其包括交叉连接的多路复用器阵列或时域多路复用器开关，其构成连接到时间的串行器阵列分多路复用总线。

37. 发明授权

US07028134B2 Crossbar integrated circuit with parallel channels for a communication device 有权
标题翻译：具有用于通信设备的并行通道的交叉开关集成电路
公开(公告)号：US07028134B2
公开(公告)日：2006-04-11
申请号：US09750629
申请日：2000-12-28
申请人： Yuanlong Wang , Kewei Yang , Daniel Fu , Feng Cheng Lin
发明人： Yuanlong Wang , Kewei Yang , Daniel Fu , Feng Cheng Lin
IPC分类号： G06F13/00
CPC分类号： H04Q3/521 , H04J3/0685 , H04Q2213/1302 , H04Q2213/13036 , H04Q2213/1304 , H04Q2213/1308 , H04Q2213/13103 , H04Q2213/13174 , H04Q2213/13214 , H04Q2213/1325 , H04Q2213/13322 , H04Q2213/1336 , H04Q2213/13367 , H04Q2213/13393
摘要： Communication circuitry is comprised of processing circuitry, parallel channels, and crossbar integrated circuits. The processing circuitry exchanges the communications between communication links and the parallel channels. The parallel channels transfer the communications in parallel with a clock signal. The crossbar integrated circuits receive the communications and the clock signal over the parallel channels, switch the communications based on the clock signal, and transfer the switched communications to the parallel channels.
摘要翻译：通信电路由处理电路，并行通道和交叉开关集成电路组成。处理电路交换通信链路和并行信道之间的通信。并行通道与时钟信号并行传输通信。交叉开关集成电路通过并行通道接收通信和时钟信号，基于时钟信号切换通信，并将交换通信传送到并行通道。

38. 发明申请

US20040208299A1 Voice-data telephonic interface control system 审中-公开
标题翻译：语音数据电话接口控制系统
公开(公告)号：US20040208299A1
公开(公告)日：2004-10-21
申请号：US10838440
申请日：2004-05-03
发明人： Ronald A. Katz
IPC分类号： G06F015/00 , G06F015/76 , H04M001/64 , H04M015/00 , H04M001/56
CPC分类号： H04Q3/665 , A63F2003/086 , G07C11/00 , G07C15/005 , G07C15/006 , H04M3/36 , H04M3/38 , H04M3/42042 , H04M3/42059 , H04M3/436 , H04M3/46 , H04M3/493 , H04M3/51 , H04M3/5166 , H04M11/00 , H04M2201/40 , H04M2203/2016 , H04M2242/22 , H04Q3/002 , H04Q3/54533 , H04Q3/5455 , H04Q3/54591 , H04Q3/72 , H04Q3/74 , H04Q2213/13034 , H04Q2213/13072 , H04Q2213/1309 , H04Q2213/13091 , H04Q2213/13093 , H04Q2213/13095 , H04Q2213/13096 , H04Q2213/13097 , H04Q2213/13103 , H04Q2213/13106 , H04Q2213/13107 , H04Q2213/1313 , H04Q2213/13141 , H04Q2213/1316 , H04Q2213/13173 , H04Q2213/13174 , H04Q2213/13175 , H04Q2213/13178 , H04Q2213/13204 , H04Q2213/13213 , H04Q2213/13214 , H04Q2213/13216 , H04Q2213/1322 , H04Q2213/13256 , H04Q2213/1328 , H04Q2213/1332 , H04Q2213/1333 , H04Q2213/13349 , H04Q2213/1337 , H04Q2213/13375 , H04Q2213/13376 , H04Q2213/13377 , H04Q2213/13405
摘要： In an audio-digital telephone interface system, selective operation prompts a caller with oral instructions to provide: digital control signals, digital data signals (numeric) or audio signals. Inbound and outbound operations are involved and inbound callers are qualified as by automatic number identification (ANI) signals and consumable key operation. A data cell is loaded in accordance with an operating program and the resulting data packet is flagged depending on the presence of audio signals. Data packets are returned to storage, as for subsequent addressing to call up, as to process or cue a caller. The illustrative format receives and organizes order data for goods or services or to isolate a subset or a sub-subset of callers.
摘要翻译：在音频数字电话接口系统中，选择性操作通过口头指令提示呼叫者提供：数字控制信号，数字数据信号（数字）或音频信号。入站和出站操作涉及，入站呼叫者通过自动号码识别（ANI）信号和消耗键操作进行限定。根据操作程序加载数据单元，并且根据音频信号的存在标记所得到的数据分组。将数据包返回到存储器，以便后续寻址以调用，以便处理或提示呼叫者。说明性格式接收并组织货物或服务的订单数据或隔离呼叫者的子集或子子集。

39. 发明申请

US20040151209A1 Asynchronous system-on-a-chip interconnect 有权
标题翻译：异步片上系统互连
公开(公告)号：US20040151209A1
公开(公告)日：2004-08-05
申请号：US10634597
申请日：2003-08-04
申请人： Fulcrum Microsystems Inc. A California Corporation
发明人： Uri Cummings , Andrew Lines
IPC分类号： H04J003/06
CPC分类号： G06F13/423 , G06F1/12 , G06F2213/0038 , H04L7/005 , H04L7/02 , H04L49/101 , H04L2012/5674 , H04Q3/0004 , H04Q2213/13034 , H04Q2213/13214 , H04Q2213/13322 , H04Q2213/13361 , H04Q2213/13362
摘要： Methods and apparatus are described relating to a system-on-a-chip which includes a plurality of synchronous modules, each synchronous module having an associated clock domain characterized by a data rate, the data rates comprising a plurality of different data rates. The system-on-a-chip also includes a plurality of clock domain converters. Each clock domain converter is coupled to a corresponding one of the synchronous modules, and is operable to convert data between the clock domain of the corresponding synchronous module and an asynchronous domain characterized by transmission of data according to an asynchronous handshake protocol. An asynchronous crossbar is coupled to the plurality of clock domain converters, and is operable in the asynchronous domain to implement a first-in-first-out (FIFO) channel between any two of the clock domain converters, thereby facilitating communication between any two of the synchronous modules.
摘要翻译：描述了涉及包括多个同步模块的片上系统的方法和装置，每个同步模块具有由数据速率表征的相关联的时钟域，数据速率包括多个不同的数据速率。片上系统还包括多个时钟域转换器。每个时钟域转换器被耦合到对应的一个同步模块，并且可操作以在对应的同步模块的时钟域和根据异步握手协议的数据传输特征的异步域之间转换数据。异步交叉开关耦合到多个时钟域转换器，并且可在异步域中操作以实现任何两个时钟域转换器之间的先进先出（FIFO）通道，从而促进任何两个时钟域转换器之间的通信同步模块。

40. 发明授权

US06643791B1 Clock distribution scheme in a signaling server 失效
标题翻译：信令服务器中的时钟分配方案
公开(公告)号：US06643791B1
公开(公告)日：2003-11-04
申请号：US09541002
申请日：2000-03-31
申请人： Val Teodorescu
发明人： Val Teodorescu
IPC分类号： G06F104
CPC分类号： G06F1/10 , H04J3/0685 , H04J3/0688 , H04Q3/0016 , H04Q2213/13176 , H04Q2213/13214 , H04Q2213/1336
摘要： A multi-stage clock distribution scheme for use in a signaling server organized into a plurality of uniquely addressable shelves. The signaling server includes a system timing generator, one or more clock distribution modules arranged in a nested hierarchical manner, and a plurality of bus control modules, wherein each bus control module interfaces with at least a portion of line cards disposed in a shelf. The system timing generator provides a framed serial control signal, SFI, for controlling the operation of the multi-stage clock distribution scheme. The SFI signal encodes the IDs of the clock distribution modules and bus control modules whereby a system clock generated by the system timing generator based on a select reference input is successively fanned-out by the intermediate clock distribution modules based on address and ID information encoded in select fields of the SFI frames until the fanned-out system clocks are received by the bus control modules. Thereafter, each bus control module provides a copy of the system clock to the line cards controlled by it based on the SFI signal.
摘要翻译：一种多阶段时钟分配方案，用于组织成多个唯一可寻址的货架的信令服务器。信令服务器包括系统定时发生器，以嵌套分级方式布置的一个或多个时钟分配模块以及多个总线控制模块，其中每个总线控制模块与布置在架子中的线卡的至少一部分相连接。系统定时发生器提供成帧串行控制信号SFI，用于控制多级时钟分配方案的操作。 SFI信号对时钟分配模块和总线控制模块的ID进行编码，由此基于选择参考输入的系统定时发生器产生的系统时钟由中间时钟分配模块基于地址和ID信息编码选择SFI帧的字段，直到总线控制模块接收到扇出系统时钟。此后，每个总线控制模块基于SFI信号向其控制的线路卡提供系统时钟的副本。

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