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1. 发明授权

US07028134B2 Crossbar integrated circuit with parallel channels for a communication device 有权
标题翻译：具有用于通信设备的并行通道的交叉开关集成电路
公开(公告)号：US07028134B2
公开(公告)日：2006-04-11
申请号：US09750629
申请日：2000-12-28
申请人： Yuanlong Wang , Kewei Yang , Daniel Fu , Feng Cheng Lin
发明人： Yuanlong Wang , Kewei Yang , Daniel Fu , Feng Cheng Lin
IPC分类号： G06F13/00
CPC分类号： H04Q3/521 , H04J3/0685 , H04Q2213/1302 , H04Q2213/13036 , H04Q2213/1304 , H04Q2213/1308 , H04Q2213/13103 , H04Q2213/13174 , H04Q2213/13214 , H04Q2213/1325 , H04Q2213/13322 , H04Q2213/1336 , H04Q2213/13367 , H04Q2213/13393
摘要： Communication circuitry is comprised of processing circuitry, parallel channels, and crossbar integrated circuits. The processing circuitry exchanges the communications between communication links and the parallel channels. The parallel channels transfer the communications in parallel with a clock signal. The crossbar integrated circuits receive the communications and the clock signal over the parallel channels, switch the communications based on the clock signal, and transfer the switched communications to the parallel channels.
摘要翻译：通信电路由处理电路，并行通道和交叉开关集成电路组成。处理电路交换通信链路和并行信道之间的通信。并行通道与时钟信号并行传输通信。交叉开关集成电路通过并行通道接收通信和时钟信号，基于时钟信号切换通信，并将交换通信传送到并行通道。

2. 发明授权

US06292705B1 Method and apparatus for address transfers, system serialization, and centralized cache and transaction control, in a symetric multiprocessor system 有权
标题翻译：在对称多处理器系统中的地址传输，系统序列化和集中式缓存和事务控制的方法和装置
公开(公告)号：US06292705B1
公开(公告)日：2001-09-18
申请号：US09163294
申请日：1998-09-29
申请人： Yuanlong Wang , Zong Yu , Xiaofan Wei , Earl T. Cohen , Brian R. Baird , Daniel Fu
发明人： Yuanlong Wang , Zong Yu , Xiaofan Wei , Earl T. Cohen , Brian R. Baird , Daniel Fu
IPC分类号： G05B1918
CPC分类号： G06F12/0822
摘要： A preferred embodiment of a symmetric multiprocessor system includes a switched fabric (switch matrix) for data transfers that provides multiple concurrent buses that enable greatly increased bandwidth between processors and shared memory. A Transaction Controller, Transaction Bus, and Transaction Status Bus are used for serialization, centralized cache control, and highly pipelined address transfers. The shared Transaction Controller serializes transaction requests from Initiator devices that can include CPU/Cache modules and Peripheral Bus modules. The Transaction Bus of an illustrative embodiment is implemented using segmented buses, distributed muxes, point-to-point wiring, and supports transaction processing at a rate of one transaction per clock cycle. The Transaction Controller monitors the Transaction Bus, maintains a set of duplicate cache-tags for all CPU/Cache modules, maps addresses to Target devices, performs centralized cache control for all CPU/Cache modules, filters unnecessary Cache transactions, and routes necessary transactions to Target devices over the Transaction Status Bus. The Transaction Status Bus includes both busbased and point-to-point control of the target devices. A modified rotating priority scheme is used to provide Starvation-free support for Locked buses and memory resources via backoff operations. Speculative memory operations are supported to further enhance performance.
摘要翻译：对称多处理器系统的优选实施例包括用于数据传输的交换结构（交换矩阵），其提供多个并行总线，其能够在处理器和共享存储器之间大大增加带宽。交易控制器，事务总线和事务状态总线用于串行化，集中式缓存控制和高流水线地址传输。共享的交易控制器将来自启动器设备的事务请求序列化，其中可能包括CPU /缓存模块和外设总线模块。说明性实施例的事务总线使用分段总线，分布式多路复用器，点对点布线来实现，并且以每个时钟周期的一个事务的速率支持事务处理。事务控制器监视事务总线，为所有CPU / Cache模块维护一组重复的缓存标签，将地址映射到目标设备，对所有CPU /缓存模块执行集中式缓存控制，过滤不必要的缓存事务，并将必要的事务路由到在事务状态总线上的目标设备。事务状态总线包括目标设备的基于总线和点到点的控制。改进的旋转优先级方案用于通过退避操作为锁定总线和存储器资源提供无饥饿的支持。支持推测性内存操作，以进一步提高性能。

3. 发明授权

US06466825B1 Method and apparatus for address transfers, system serialization, and centralized cache and transaction control, in a symetric multiprocessor system 有权
标题翻译：在对称多处理器系统中的地址传输，系统序列化和集中式缓存和事务控制的方法和装置
公开(公告)号：US06466825B1
公开(公告)日：2002-10-15
申请号：US09927717
申请日：2001-08-10
申请人： Yuanlong Wang , Zong Yu , Xiaofan Wei , Earl T. Cohen , Brian R. Baird , Daniel Fu
发明人： Yuanlong Wang , Zong Yu , Xiaofan Wei , Earl T. Cohen , Brian R. Baird , Daniel Fu
IPC分类号： G05B1918
CPC分类号： G06F12/0822
摘要： A preferred embodiment of a symmetric multiprocessor system includes a switched fabric (switch matrix) for data transfers that provides multiple concurrent buses that enable greatly increased bandwidth between processors and shared memory. A Transaction Controller, Transaction Bus, and Transaction Status Bus are used for serialization, centralized cache control, and highly pipelined address transfers. The shared Transaction Controller serializes transaction requests from Initiator devices that can include CPU/Cache modules and Peripheral Bus modules. The Transaction Bus of an illustrative embodiment is implemented using segmented buses, distributed muxes, point-to-point wiring, and supports transaction processing at a rate of one transaction per clock cycle. The Transaction Controller monitors the Transaction Bus, maintains a set of duplicate cache-tags for all CPU/Cache modules, maps addresses to Target devices, performs centralized cache control for all CPU/Cache modules, filters unnecessary Cache transactions, and routes necessary transactions to Target devices over the Transaction Status Bus. The Transaction Status Bus includes both bus-based based and point-to-point control of the target devices. A modified rotating priority scheme is used to provide Starvation-free support for Locked buses and memory resources via backoff operations. Speculative memory operations are supported to further enhance performance.
摘要翻译：对称多处理器系统的优选实施例包括用于数据传输的交换结构（交换矩阵），其提供多个并行总线，其能够在处理器和共享存储器之间大大增加带宽。交易控制器，事务总线和事务状态总线用于串行化，集中式缓存控制和高流水线地址传输。共享的交易控制器将来自启动器设备的事务请求序列化，其中可能包括CPU /缓存模块和外设总线模块。说明性实施例的事务总线使用分段总线，分布式多路复用器，点对点布线来实现，并且以每个时钟周期的一个事务的速率支持事务处理。事务控制器监视事务总线，为所有CPU / Cache模块维护一组重复的缓存标签，将地址映射到目标设备，对所有CPU /缓存模块执行集中式缓存控制，过滤不必要的缓存事务，并将必要的事务路由到在事务状态总线上的目标设备。事务状态总线包括目标设备的基于总线的和点到点的控制。改进的旋转优先级方案用于通过退避操作为锁定总线和存储器资源提供无饥饿的支持。支持推测性内存操作，以进一步提高性能。

4. 发明授权

US06516442B1 Channel interface and protocols for cache coherency in a scalable symmetric multiprocessor system 有权
标题翻译：可扩展对称多处理器系统中的高速缓存一致性的通道接口和协议
公开(公告)号：US06516442B1
公开(公告)日：2003-02-04
申请号：US09281749
申请日：1999-03-30
申请人： Yuanlong Wang , Brian R. Biard , Daniel Fu , Earl T. Cohen , Carl G. Amdahl
发明人： Yuanlong Wang , Brian R. Biard , Daniel Fu , Earl T. Cohen , Carl G. Amdahl
IPC分类号： H03M1300
CPC分类号： G06F12/0822 , G06F12/0813 , G06F15/17375
摘要： A preferred embodiment of a symmetric multiprocessor system includes a switched fabric (switch matrix) for data transfers that provides multiple concurrent buses that enable greatly increased bandwidth between processors and shared memory. A high-speed point-to-point Channel couples command initiators and memory with the switch matrix and with I/O subsystems. Each end of a channel is connected to a Channel Interface Block (CIB). The CIB presents a logical interface to the Channel, providing a communication path to and from a CIB in another IC. CIB logic presents a similar interface between the CIB and the core-logic and between the CIB and the Channel transceivers. A channel transport protocol is is implemented in the CIB to reliably transfer data from one chip to another in the face of errors and limited buffering.
摘要翻译：对称多处理器系统的优选实施例包括用于数据传输的交换结构（交换矩阵），其提供多个并行总线，其能够在处理器和共享存储器之间大大增加带宽。高速点对点通道将命令启动器和内存与交换机矩阵和I / O子系统耦合起来。通道的每一端连接到通道接口块（CIB）。 CIB提供了一个到该通道的逻辑接口，为另一个IC提供了一条来自CIB的通信路径。 CIB逻辑在CIB和核心逻辑之间以及CIB和Channel收发器之间呈现类似的接口。在CIB中实现了信道传输协议，以便在错误和有限缓冲的情况下将数据从一个芯片可靠地传送到另一个芯片。

5. 发明授权

US06949423B1 MOSFET-fused nonvolatile read-only memory cell (MOFROM) 有权
标题翻译： MOSFET熔接的非易失性只读存储单元（MOFROM）
公开(公告)号：US06949423B1
公开(公告)日：2005-09-27
申请号：US10723004
申请日：2003-11-26
申请人： Pingxi Ma , Daniel Fu
发明人： Pingxi Ma , Daniel Fu
IPC分类号： G11C17/16 , H01L21/28 , H01L21/8247 , H01L23/525 , H01L23/58 , H01L27/115
CPC分类号： H01L23/5256 , G11C17/16 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： With directly biasing drain to source in a floating-gate N-MOSFET, a new MOSFET-fused nonvolatile ROM cell (MOFROM) is provided by tunneling-induced punch through of the drain junction to the source. The MOFROM is completely compatible with the mainstream standard CMOS process. The standard MOSFET presents an “OFF” state before the burning and an “ON” state with a stable low-resistance path after the burning.
摘要翻译：通过在浮栅N-MOSFET中直接偏置漏极到源极，通过隧道引起的穿通漏极连接到源极的MOSFET熔断非易失性ROM单元（MOFROM）提供了新的MOSFET熔合非易失性ROM单元（MOFROM）。 MOFROM与主流标准CMOS工艺完全兼容。标准MOSFET在燃烧之前呈现“OFF”状态，在燃烧后具有稳定的低电阻路径的“ON”状态。

6. 发明授权

US06633945B1 Fully connected cache coherent multiprocessing systems 有权
标题翻译：完全连接的缓存一致多处理系统
公开(公告)号：US06633945B1
公开(公告)日：2003-10-14
申请号：US09349641
申请日：1999-07-08
申请人： Daniel Fu , Carlton T. Amdahl , Walstein Bennett Smith, III
发明人： Daniel Fu , Carlton T. Amdahl , Walstein Bennett Smith, III
IPC分类号： G06F1300
CPC分类号： G06F12/0813 , G06F12/0822 , G06F15/17375
摘要： Fully connected multiple FCU-based architectures reduce requirements for Tag SRAM size and memory read latencies. A preferred embodiment of a symmetric multiprocessor system includes a switched fabric (switch matrix) for data transfers that provides multiple concurrent buses that enable greatly increased bandwidth between processors and shared memory. A high-speed point-to-point Channel couples command initiators and memory with the switch matrix and with I/O subsystems.
摘要翻译：完全连接的多个基于FCU的架构降低了标签SRAM大小和内存读取延迟的要求。对称多处理器系统的优选实施例包括用于数据传输的交换结构（交换矩阵），其提供多个并行总线，其能够在处理器和共享存储器之间大大增加带宽。高速点对点通道将命令启动器和存储器与开关矩阵和I / O子系统耦合起来。

7. 发明授权

US07324524B2 Pseudo synchronous machine 有权
标题翻译：伪同步机
公开(公告)号：US07324524B2
公开(公告)日：2008-01-29
申请号：US10284494
申请日：2002-10-29
申请人： Axel K. Kloth , Paul Bergantino , Moshe De-Leon , Daniel Fu , Stephen M. Mills , Jeremy Bicknell , Warner Andrews
发明人： Axel K. Kloth , Paul Bergantino , Moshe De-Leon , Daniel Fu , Stephen M. Mills , Jeremy Bicknell , Warner Andrews
IPC分类号： H04L12/56 , H04L12/44
CPC分类号： H04J3/0632 , Y10S370/907
摘要： A method and apparatus is disclosed for interfacing an asynchronous network with a synchronous network and in particular for efficiently utilizing available bandwidth of a synchronous network transmit opportunity. In one embodiment asynchronous traffic arrives via an asynchronous network at a network device, such as a switch, for transmission over a synchronous network. The traffic is parsed into cells and after switching, a reassembly unit is provided for processing one or more cells buckets. Write operations occur based on an ingress pointer while read operations are controlled by an egress pointer. Upon occurrence of a transmit opportunity on the synchronous network, the entire bandwidth of the transmit opportunity is utilized by loading awaiting cells from bucket memory on to the synchronous network. Sufficient cells are stored in memory between the memory locations identified by the ingress pointer and the egress pointer to insure total utilization of transmit opportunity bandwidth.
摘要翻译：公开了一种用于将异步网络与同步网络接口的方法和装置，特别是用于有效地利用同步网络发送机会的可用带宽。在一个实施例中，异步业务经由网络设备（例如交换机）上的异步网络来到达，用于通过同步网络传输。流量被解析为单元格，并且在切换之后，提供了用于处理一个或多个单元格桶的重组单元。写入操作基于入口指针发生，而读取操作由出口指针控制。在同步网络上发生发送机会时，通过将等待小区从桶存储器加载到同步网络来利用发送机会的整个带宽。足够的单元被存储在由入口指针和出口指针标识的存储器位置之间的存储器中，以确保发送机会带宽的总利用率。

8. 发明授权

US07286471B2 Dynamic bandwidth allocation for wide area networks 有权
标题翻译：广域网的动态带宽分配
公开(公告)号：US07286471B2
公开(公告)日：2007-10-23
申请号：US10106670
申请日：2002-03-23
申请人： Axel K. Kloth , Warner Andrews , Paul Bergantino , Jeremy Bicknell , Daniel Fu , Moshe De-Leon , Stephen M. Mills
发明人： Axel K. Kloth , Warner Andrews , Paul Bergantino , Jeremy Bicknell , Daniel Fu , Moshe De-Leon , Stephen M. Mills
IPC分类号： H04L12/66 , G06F15/173
CPC分类号： H04L47/822 , H04L41/0896 , H04L47/15 , H04L47/70 , H04L47/765 , H04L47/781
摘要： System and method for dynamically altering bandwidth allocation to each region serviced by a network. Each region is allocated an initial estimated bandwidth on the network and compares instantaneous demand against the allocation. When demand falls below the allocation, the region releases bandwidth so other regions can take advantage of that bandwidth. When demand exceeds the allocation, the region takes advantage of bandwidth released by other regions.
摘要翻译：用于动态地改变由网络服务的每个区域的带宽分配的系统和方法。每个区域在网络上分配初始估计带宽，并将瞬时需求与分配进行比较。当需求低于分配时，该区域释放带宽，以便其他区域可以利用该带宽。当需求超过分配时，该地区利用其他地区发布的带宽。

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