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31. 发明授权

US06034394A Methods and arrangements for forming a floating gate in non-volatile memory semiconductor devices 失效
标题翻译：在非易失性存储器半导体器件中形成浮置栅极的方法和装置
公开(公告)号：US06034394A
公开(公告)日：2000-03-07
申请号：US992950
申请日：1997-12-18
申请人： Mark Ramsbey , Tuan D. Pham , Yu Sun , Kenneth W. Au
发明人： Mark Ramsbey , Tuan D. Pham , Yu Sun , Kenneth W. Au
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324
摘要： Methods and arrangements are provided to increase the process control during the fabrication of the floating/control gate configuration in a non-volatile memory semiconductor device. The methods and arrangements effectively reduce the severity of the topology attributable to the space between adjacent floating gates, by advantageously reducing the thickness of the floating gates. The altered topology allows a subsequently formed control gate to be formed without significant surface depressions. Significant surface depressions in the control gate can lead to cracks in the silicide layer that is formed on the control gate. The cracking usually occurs during subsequent thermal processing of the semiconductor device. Thus the disclosed methods and arrangements prevent cracking of the silicide layer on the control gate, which can affect the performance of the semiconductor device by increasing the resistance of the control gate arrangement.
摘要翻译：提供了在非易失性存储器半导体器件中制造浮置/控制栅极配置期间增加处理控制的方法和装置。通过有利地减小浮动栅极的厚度，这些方法和布置有效地降低了归因于相邻浮动栅极之间的空间的拓扑的严重性。改变的拓扑允许随后形成的控制栅极形成而没有显着的表面凹陷。控制栅中的显着的表面凹陷可能导致在控制栅上形成的硅化物层中的裂纹。裂纹通常发生在半导体器件的随后热处理期间。因此，所公开的方法和布置防止了控制栅极上的硅化物层的破裂，这可以通过增加控制栅极布置的电阻来影响半导体器件的性能。

32. 发明授权

US5907781A Process for fabricating an integrated circuit with a self-aligned contact 失效
公开(公告)号：US5907781A
公开(公告)日：1999-05-25
申请号：US49517
申请日：1998-03-27
申请人： Hung-Sheng Chen , Unsoon Kim , Yu Sun , Chi Chang , Mark Ramsbey , Mark Randolph , Tatsuya Kajita , Angela Hui , Fei Wang , Mark Chang
发明人： Hung-Sheng Chen , Unsoon Kim , Yu Sun , Chi Chang , Mark Ramsbey , Mark Randolph , Tatsuya Kajita , Angela Hui , Fei Wang , Mark Chang
IPC分类号： H01L21/60 , H01L21/768 , H01L21/8247 , H01L27/115 , H01L21/335
CPC分类号： H01L21/76897 , H01L21/76895
摘要： A method of forming a contact in a flash memory device utilizes a local interconnect process technique. The local interconnect process technique allows the contact to butt against or overlap a stacked gate associated with the memory cell. The contact can include tungsten. The stacked gate is covered by a barrier layer which also covers the insulative spacers.

33. 发明授权

US5869385A Selectively oxidized field oxide region 失效
标题翻译：选择性氧化场氧化物区域
公开(公告)号：US5869385A
公开(公告)日：1999-02-09
申请号：US569704
申请日：1995-12-08
申请人： Yuan Tang , Mark Ramsbey
发明人： Yuan Tang , Mark Ramsbey
IPC分类号： H01L21/762 , H01L21/8234 , H01L21/76
CPC分类号： H01L21/823481 , H01L21/76213 , Y10S148/138 , Y10S438/964
摘要： A field oxide region is formed with a reduced bird's beak by selectively implanting impurity atoms into the semiconductor substrate to increase the oxidation rate of the substrate and thermally oxidizing the implanted region of the semiconductor substrate. In another embodiment, a gate oxide layer having a differential thickness is formed by implanting impurity atoms into the semiconductor substrate in a selected region wherein a thick portion of the gate oxide is to be formed and thermally oxidizing the semiconductor substrate.
摘要翻译：通过选择性地将杂质原子注入到半导体衬底中以增加衬底的氧化速率并对半导体衬底的注入区域进行热氧化，形成具有缩小的鸟嘴的场氧化物区域。在另一个实施例中，通过在要形成栅极氧化物的厚部分并对半导体衬底进行热氧化的选定区域中将杂质原子注入到半导体衬底中，形成具有差分厚度的栅氧化层。

34. 发明申请

US20070029604A1 Using thin undoped TEOS with BPTEOS ILD or BPTEOS ILD alone to improve charge loss and contact resistance in multi-bit memory devices 审中-公开
标题翻译：使用薄的未掺杂TEOS与BPTEOS ILD或BPTEOS ILD单独改善多位存储器件中的电荷损失和接触电阻
公开(公告)号：US20070029604A1
公开(公告)日：2007-02-08
申请号：US11546688
申请日：2006-10-12
申请人： Ning Cheng , Minh Ngo , Hirokazu Tokuno , Lu You , Angela Hui , Yi He , Brian Mooney , Joan Yang , Mark Ramsbey
发明人： Ning Cheng , Minh Ngo , Hirokazu Tokuno , Lu You , Angela Hui , Yi He , Brian Mooney , Joan Yang , Mark Ramsbey
IPC分类号： H01L29/788
CPC分类号： H01L27/115 , H01L27/11568
摘要： The present invention facilitates dual bit memory devices and operation of dual bit memory device by providing systems and methods that employ a relatively thin undoped TEOS liner during fabrication, instead of a relatively thick TEOS layer that is conventionally used. Employment of the relatively thin liner facilitates dual bit memory device operation by mitigating charge loss and contact resistance while providing protection against unwanted dopant diffusion. The present invention includes utilizing a relatively thin undoped TEOS liner that is formed on wordlines and portions of a charge trapping dielectric layer. The relatively thin undoped TEOS liner is formed with a thickness of less than about 400 Angstroms so that contact resistance and charge loss are improved and yet providing suitable protection for operation of the device. Additionally, the present invention includes foregoing with an undoped TEOS liner altogether.
摘要翻译：本发明通过提供在制造期间使用相对薄的未掺杂TEOS衬垫的系统和方法而不是通常使用的相对较厚的TEOS层来便于双位存储器件和双位存储器件的操作。使用相对薄的衬垫通过减轻电荷损失和接触电阻而提供双位存储器件操作，同时提供防止不期望的掺杂剂扩散的保护。本发明包括利用形成在字线和电荷捕获电介质层的部分上的相对薄的未掺杂的TEOS衬垫。相对薄的未掺杂的TEOS衬垫形成有小于约400埃的厚度，使得接触电阻和电荷损失得到改善，并且为器件的操作提供适当的保护。此外，本发明包括前述的未掺杂的TEOS衬垫。

35. 发明授权

US06989319B1 Methods for forming nitrogen-rich regions in non-volatile semiconductor memory devices 有权
标题翻译：在非易失性半导体存储器件中形成富氮区的方法
公开(公告)号：US06989319B1
公开(公告)日：2006-01-24
申请号：US10718707
申请日：2003-11-24
申请人： Mark Ramsbey , Sameer Haddad , Vei-Han Chan , Yu Sun , Chi Chang
发明人： Mark Ramsbey , Sameer Haddad , Vei-Han Chan , Yu Sun , Chi Chang
IPC分类号： H01L21/265
CPC分类号： H01L21/265 , H01L21/28176 , H01L21/28273
摘要： Methods and arrangements are provided for significantly reducing electron trapping in semiconductor devices having a polysilicon feature and an overlying dielectric layer. The methods and arrangements employ a nitrogen-rich region within the polysilicon feature near the interface to the overlying dielectric layer. The methods include selectively implanting nitrogen ions through at least a portion of the overlying dielectric layer and into the polysilicon feature to form an initial nitrogen concentration profile within the polysilicon feature. Next, the temperature within the polysilicon feature is raised to an adequately high temperature, for example using rapid thermal anneal (RTA) techniques, which cause the initial nitrogen concentration profile to change due to the migration of the majority of the nitrogen towards either the interface with the overlying dielectric layer or the interface with an underlying layer. Consequently, the polysilicon feature has a first nitrogen-rich region near the interface to the overlying dielectric layer and a second nitrogen-rich region near the interface to the underlying layer. The migration of nitrogen further forms a contiguous reduced-nitrogen region located between the first nitrogen-rich region and the second nitrogen-rich region. The contiguous reduced-nitrogen region has a lower concentration of nitrogen than does the first nitrogen-rich region and the second nitrogen-rich region. The first nitrogen-rich region has been found to reduce electron trapping within the polysilicon feature. Thus, for example, in a non-volatile memory device wherein the polysilicon feature is a floating gate, false programming of the memory device can be significantly avoided by reducing the number of trapped electrons in the floating gate.
摘要翻译：提供了用于显着减少具有多晶硅特征和上覆电介质层的半导体器件中的电子俘获的方法和装置。所述方法和装置在靠近覆盖的介电层的界面附近使用多晶硅特征内的富氮区域。所述方法包括通过至少部分上覆介质层选择性地注入氮离子并进入多晶硅特征以在多晶硅特征内形成初始氮浓度分布。接下来，将多晶硅特征中的温度升高到足够高的温度，例如使用快速热退火（RTA）技术，其使得初始氮浓度分布由于大部分氮朝着界面迁移而改变与上层电介质层或与下层的界面。因此，多晶硅特征具有在与上覆电介质层的界面附近的第一富氮区域和与下层的界面附近的第二富氮区域。氮的迁移进一步形成位于第一富氮区和第二富氮区之间的连续的还原氮区。连续的还原氮区域具有比第一富氮区域和第二富氮区域低的氮浓度。已发现第一富氮区域减少多晶硅特征内的电子俘获。因此，例如，在其中多晶硅特征是浮动栅极的非易失性存储器件中，可以通过减少浮置栅极中的俘获电子的数量来显着地避免存储器件的伪编程。

36. 发明申请

US20050153508A1 Pocket implant for complementary bit disturb improvement and charging improvement of SONOS memory cell 有权
公开(公告)号：US20050153508A1
公开(公告)日：2005-07-14
申请号：US10755740
申请日：2004-01-12
申请人： Emmanuil Lingunis , Nga-Ching Wong , Sameer Haddad , Mark Randolph , Mark Ramsbey , Ashot Melik-Martirosian , Edward Runnion , Yi He
发明人： Emmanuil Lingunis , Nga-Ching Wong , Sameer Haddad , Mark Randolph , Mark Ramsbey , Ashot Melik-Martirosian , Edward Runnion , Yi He
IPC分类号： H01L21/265 , H01L21/336 , H01L21/8234 , H01L21/8246 , H01L27/115 , H01L29/10 , H01L29/792
CPC分类号： H01L27/11568 , H01L21/26586 , H01L27/115 , H01L29/1083 , H01L29/66833 , Y10S438/959
摘要： A technique for forming at least part of an array of a dual bit memory core is disclosed. Initially, a portion of a charge trapping dielectric layer is formed over a substrate and a resist is formed over the portion of the charge trapping dielectric layer. The resist is patterned and a pocket implant is performed at an angle to establish pocket implants within the substrate. A bitline implant is then performed to establish buried bitlines within the substrate. The patterned resist is then removed and the remainder of the charge trapping dielectric layer is formed. A wordline material is formed over the remainder of the charge trapping dielectric layer and patterned to form wordlines that overlie the bitlines. The pocket implants serve to mitigate, among other things, complementary bit disturb (CBD) that can result from semiconductor scaling. As such, semiconductor devices can be made smaller and increased packing densities can be achieved by virtue of the inventive concepts set forth herein.

37. 发明授权

US06399446B1 Process for fabricating high density memory cells using a metallic hard mask 有权
标题翻译：使用金属硬掩模制造高密度记忆单元的方法
公开(公告)号：US06399446B1
公开(公告)日：2002-06-04
申请号：US09429722
申请日：1999-10-29
申请人： Bharath Rangarajan , David K. Foote , Fei Wang , Dawn M. Hopper , Stephen K. Park , Jack Thomas , Mark Chang , Mark Ramsbey
发明人： Bharath Rangarajan , David K. Foote , Fei Wang , Dawn M. Hopper , Stephen K. Park , Jack Thomas , Mark Chang , Mark Ramsbey
IPC分类号： H01L218247
CPC分类号： H01L27/11568 , H01L27/115 , Y10S438/945
摘要： A process for fabricating a memory cell in a two-bit EEPROM device including forming an ONO layer overlying a semiconductor substrate, depositing a hard mask overlying the ONO layer, and patterning the hard mask. The hard mask is made from tungsten, titanium, or titanium nitride. The process further includes doping the semiconductor substrate with boron causing p-type regions to form in the semiconductor substrate, and doping the semiconductor substrate with n-type dopants, such as arsenic, causing n-type regions to form in the semiconductor substrate. The exposed ONO layer is then etched to expose part of the semiconductor substrate, and a bit-line oxide region is formed overlying the semiconductor substrate. The hard mask is then stripped, preferably using an H2O2 solution.
摘要翻译：一种用于在二位EEPROM器件中制造存储单元的方法，包括形成覆盖在半导体衬底上的ONO层，沉积覆盖在ONO层上的硬掩模，以及对该硬掩模进行构图。硬掩模由钨，钛或氮化钛制成。该工艺还包括用硼掺杂导致在半导体衬底中形成p型区域的半导体衬底，并且用诸如砷的n型掺杂剂掺杂半导体衬底，从而在半导体衬底中形成n型区域。然后对暴露的ONO层进行蚀刻以暴露半导体衬底的一部分，并且在半导体衬底上形成位线氧化物区域。然后将硬掩模剥离，优选使用H 2 O 2溶液。

38. 发明授权

US06251717B1 Viable memory cell formed using rapid thermal annealing 有权
标题翻译：使用快速热退火形成的可行存储单元
公开(公告)号：US06251717B1
公开(公告)日：2001-06-26
申请号：US09163315
申请日：1998-09-30
申请人： Mark Ramsbey , Daniel Sobek , Nicholas H. Trispas
发明人： Mark Ramsbey , Daniel Sobek , Nicholas H. Trispas
IPC分类号： H01L218242
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method for forming viable floating gate memory cells in a semiconductor substrate. At various points within the memory cell manufacturing process rapid thermal annealing is used to repair any damage that may be caused to the crystals in the substrate by various processing steps. By quickly repairing any damage to the crystals of the substrate, the rate and amount of overall transient enhanced diffusion of the various dopants within the substrate can be greatly reduced, thereby allowing the production of a viable memory cell. Specifically, the present invention uses rapid thermal annealing during and following the formation of the source and drain regions and the interconnection regions effecting electrical connection between the source regions. This desensitizes the erase rates of the semiconductor device to the etching conditions employed to form the connections.
摘要翻译：一种用于在半导体衬底中形成可行浮栅存储器单元的方法。在存储单元制造过程中的各个点，使用快速热退火来通过各种处理步骤修复可能对基板中的晶体造成的任何损坏。通过快速修复对基板的晶体的任何损坏，可以大大降低衬底内的各种掺杂剂的总体瞬态增强扩散的速率和量，从而允许生产可行的存储单元。具体地说，本发明在形成源极区和漏极区之间和之后使用快速热退火以及实现源区之间的电连接的互连区。这使得半导体器件的擦除速率与用于形成连接的蚀刻条件脱敏。

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