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1. 发明授权

US5885869A Method for uniformly doping hemispherical grain polycrystalline silicon 失效
标题翻译：均匀掺杂半球状晶粒多晶硅的方法
公开(公告)号：US5885869A
公开(公告)日：1999-03-23
申请号：US528183
申请日：1995-09-14
申请人： Charles Turner , Randhir P. S. Thakur
发明人： Charles Turner , Randhir P. S. Thakur
IPC分类号： H01L21/22 , H01L21/02 , H01L21/3215 , H01L21/334 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108 , H01L21/20
CPC分类号： H01L28/84 , H01L21/32155 , H01L27/10808 , H01L29/66181 , Y10S148/014 , Y10S148/122 , Y10S148/138
摘要： A method is disclosed for uniformly doping HSG polycrystalline silicon independent of the other layers of the semiconductor substrate. A semiconductor substrate having a silicon dioxide layer formed superjacent a polysilicon layer is provided in a chamber. A doped rough silicon layer is formed in situ superjacent the silicon dioxide layer. This is accomplished by depositing the silicon layer superjacent the silicon dioxide layer and exposing the silicon layer to a source gas, a dopant gas, and energy, preferably in situ to thereby form uniformly doped silicon layer and roughened polysilicon layer using rapid thermal chemical vapor deposition techniques or low pressure chemical vapor deposition.Alternatively, a uniformly doped roughened polysilicon layer is formed superjacent the silicon dioxide layer in situ. This formation is achieved by depositing an amorphous silicon layer superjacent the silicon dioxide layer and roughening the amorphous silicon layer in situ. The step of roughening is achieved by vacuum annealing the amorphous silicon layer using rapid thermal chemical vapor deposition techniques or low pressure chemical vapor deposition. The roughened amorphous silicon layer is doped by exposing to a source gas, a dopant gas and energy.
摘要翻译：公开了与半导体衬底的其他层无关的均匀掺杂HSG多晶硅的方法。具有在多晶硅层之上形成的二氧化硅层的半导体衬底设置在室中。掺杂的粗硅层原位形成在二氧化硅层的上方。这是通过沉积超过二氧化硅层的硅层并将硅层暴露于源气体，掺杂剂气体和能量，优选在原位，由此形成均匀掺杂的硅层和使用快速热化学气相沉积的粗糙多晶硅层技术或低压化学气相沉积。或者，原位形成在二氧化硅层之上的均匀掺杂的粗糙多晶硅层。通过沉积位于二氧化硅层之上的非晶硅层并原位粗化非晶硅层来实现该形成。通过使用快速热化学气相沉积技术或低压化学气相沉积对非晶硅层进行真空退火来实现粗糙化的步骤。粗糙化的非晶硅层通过暴露于源气体，掺杂剂气体和能量而被掺杂。

2. 发明授权

US5670406A Method of making a tooth shaped capacitor 失效
标题翻译：制造牙形电容器的方法
公开(公告)号：US5670406A
公开(公告)日：1997-09-23
申请号：US791505
申请日：1997-01-30
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108 , H01L21/70
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/92 , Y10S148/138 , Y10S438/947
摘要： A method of manufacturing a capacitor for use in semiconductor memories is disclosed herein. The present invention includes forming anti-oxidizing regions from dot silicon for use as an oxidation mask to oxidize a polysilicon layer. Further, a silicon oxide layer is used as an etching mask to form a bottom storage node of a capacitor. An etching process is performed to etch a portion of the first polysilicon layer. Next, the silicon oxide layer is removed to define the bottom storage node. Utilizing the bottom storage node structure, the present invention can be used to increase the surface area of the capacitor.
摘要翻译：本文公开了制造用于半导体存储器的电容器的方法。本发明包括从点硅形成抗氧化区域以用作氧化掩模以氧化多晶硅层。此外，使用氧化硅层作为蚀刻掩模来形成电容器的底部存储节点。执行蚀刻工艺以蚀刻第一多晶硅层的一部分。接下来，去除氧化硅层以限定底部存储节点。利用底部存储节点结构，本发明可以用于增加电容器的表面积。

3. 发明授权

US5639685A Semiconductor processing method of providing a conductively doped layer of hemispherical grain polysilicon 失效
标题翻译：提供半导体晶粒多晶硅的导电掺杂层的半导体加工方法
公开(公告)号：US5639685A
公开(公告)日：1997-06-17
申请号：US539851
申请日：1995-10-06
申请人： John K. Zahurak , Klaus F. Schuegraf , Randhir P. S. Thakur
发明人： John K. Zahurak , Klaus F. Schuegraf , Randhir P. S. Thakur
IPC分类号： H01L21/02 , H01L21/70
CPC分类号： H01L28/84 , Y10S148/138
摘要： A semiconductor processing method of providing a conductively doped layer of hemispherical grain polysilicon over a substrate includes, a) providing a layer of conductively doped silicon over the substrate to a thickness greater than about 200 Angstroms; b) depositing an undoped layer of non-polycrystalline silicon over the doped silicon layer to a thickness of from 100 Angstroms to about 400 Angstroms; c) positioning the substrate with the doped silicon and undoped non-polycrystalline silicon layers within a chemical vapor deposition reactor; d) with the substrate therein, lowering pressure within the chemical vapor deposition reactor to a first pressure at or below about 200 mTorr; e) with the substrate therein, raising pressure within the chemical vapor deposition reactor from the first pressure and flushing the reactor with a purging gas; f) with the substrate therein ceasing flow of the purging gas and lowering pressure within the chemical vapor deposition reactor to a second pressure at or below about 200 mTorr; and g) annealing the substrate having the deposited non-polycrystalline silicon layer in the presence of a conductivity enhancing impurity gas at an annealing temperature of from about 350.degree. C. to about 600.degree. C. and at an annealing pressure of from about 10.sup.-4 Torr to about 80 Torr to in situ both diffuse conductivity enhancing impurity into the non-polycrystalline silicon layer and transform the non-polycrystalline silicon layer into a conductively doped hemispherical grain polysilicon layer.
摘要翻译：在衬底上提供半球形晶粒多晶硅的导电掺杂层的半导体处理方法包括：a）在衬底上提供厚度大于约200埃的导电掺杂硅层; b）在掺杂硅层上沉积未掺杂的非多晶硅层至厚度为100埃至约400埃; c）将衬底与掺杂的硅和未掺杂的非多晶硅层定位在化学气相沉积反应器内; d）与其中的基底，将化学气相沉积反应器内的压力降低到等于或低于约200mTorr的第一压力; e）与其中的基板，从第一压力升高化学气相沉积反应器内的压力并用净化气体冲洗反应器; f）其中衬底在其中停止清洗气体的流动并且将化学气相沉积反应器内的压力降低至等于或低于约200mTorr的第二压力; 以及g）在约350℃至约600℃的退火温度和约10℃的退火温度下，在导电性增强杂质气体存在下退火具有沉积的非多晶硅层的衬底， 4乇至约80乇原位扩散导电性增强杂质进入非多晶硅层，并将非多晶硅层转变为导电掺杂半球形晶粒多晶硅层。

4. 发明授权

US5670405A Method of making a tooth shaped capacitor using ion implantation 失效
标题翻译：使用离子注入制造牙形电容器的方法
公开(公告)号：US5670405A
公开(公告)日：1997-09-23
申请号：US791504
申请日：1997-01-30
申请人： Horng-Huei Tseng
发明人： Horng-Huei Tseng
IPC分类号： H01L21/02 , H01L21/70
CPC分类号： H01L28/92 , Y10S148/138
摘要： A method of manufacturing a capacitor for use in semiconductor memories is disclosed herein. The present invention includes forming a silicon oxide layer as an etching mask to etch a polysilicon layer to form a bottom storage node of a capacitor. The silicon oxide layer is formed from the thermal annealing of oxygen doped dot silicon.
摘要翻译：本文公开了制造用于半导体存储器的电容器的方法。本发明包括形成氧化硅层作为蚀刻掩模以蚀刻多晶硅层以形成电容器的底部存储节点。氧化硅层由氧掺杂点硅的热退火形成。

5. 发明授权

US5372962A Method of making a semiconductor integrated circuit device having a capacitor with a porous surface of an electrode 失效
标题翻译：制造具有电极多孔表面的电容器的半导体集成电路器件的方法
公开(公告)号：US5372962A
公开(公告)日：1994-12-13
申请号：US11855
申请日：1993-02-01
申请人： Toshiyuki Hirota , Ichirou Honma , Hirohito Watanabe , Masanobu Zenke
发明人： Toshiyuki Hirota , Ichirou Honma , Hirohito Watanabe , Masanobu Zenke
IPC分类号： H01L21/8242 , H01L27/108 , H01L21/70
CPC分类号： H01L27/10852 , H01L27/10808 , Y10S148/138 , Y10S438/964
摘要： A capacitor incorporated in a semiconductor integrated circuit device is expected to have a large amount of capacitance without increase of the occupation area, and has a lower electrode increased in surface area by using a roughening technique selected from the group consisting of an anodizing technique, an anodic oxidation, a wet etching and a dry etching so that a surface of the lower electrode becomes porous, thereby increasing the capacitance.
摘要翻译：期望并入半导体集成电路器件中的电容器具有大量的电容而不增加占用面积，并且通过使用选自以下的粗糙化技术，具有增加表面积的下电极，所述粗糙化技术包括阳极氧化技术，阳极氧化，湿蚀刻和干蚀刻，使得下电极的表面变多孔，从而增加电容。

6. 发明授权

US5094967A Method for manufacturing semiconductor device having a non-volatile memory cell and logic regions by using a CVD second insulating film 失效
标题翻译：使用CVD第二绝缘膜制造具有非易失性存储单元和逻辑区域的半导体器件的方法
公开(公告)号：US5094967A
公开(公告)日：1992-03-10
申请号：US620701
申请日：1990-12-03
申请人： Kazuyoshi Shinada , Masayuki Yoshida , Takahide Mizutani , Naoki Hanada
发明人： Kazuyoshi Shinada , Masayuki Yoshida , Takahide Mizutani , Naoki Hanada
IPC分类号： H01L21/82 , H01L21/8234 , H01L21/8247 , H01L27/088 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , H01L21/82 , H01L27/115 , H01L27/11539 , Y10S148/138
摘要： A method for manufacturing a semiconductor substrate device having a non-volatile memory cell region and a logic region including MOS transistors. A first insulating film and a first electrode layer are formed on a semiconductor substrate. Only those portions of the first insulating film and first electrode layer which are located in the logic region are removed, without removing those portions of the first insulating film and first electrode layer which are located in the non-volatile memory cell region. A sacrificial film is deposited for insulation over the entire surface of the memory cell region and logic region, and then a resist film is coated on the sacrificial film. Subsequently, impurity ions are implanted into a desired channel region located in the logic region. The resist film and sacrificial film are removed, and thereafter a second insulating film and a second electrode layer are formed.

7. 发明授权

US10486391B2 Bonded structure and method for manufacturing the same 有权
公开(公告)号：US10486391B2
公开(公告)日：2019-11-26
申请号：US15849925
申请日：2017-12-21
申请人： HONDA MOTOR CO., LTD.
发明人： Katsuyuki Awano , Yasuhiko Saijo , Yoichi Toyooka , Masaaki Nishi
IPC分类号： B32B3/30 , B32B15/04 , B29C65/00 , B23K26/352 , C09J5/02 , B62D29/00 , B62D21/11 , B32B7/12 , B23B3/30 , B29C65/54 , B29L31/30 , B62D27/02 , B23K26/324 , B23B3/26 , B32B15/18 , B23K26/00 , B23K103/10 , B23K26/354 , B29L9/00 , B29C65/48 , B29C65/52
CPC分类号： B32B7/12 , B23B3/30 , B23K26/352 , B23K26/355 , B23K26/3568 , B29C65/54 , B29C65/542 , B29C66/028 , B29C66/303 , B29C66/30325 , B29C66/721 , B29C66/73162 , B29C66/73771 , B29C66/742 , B32B15/04 , B62D21/11 , B62D29/005 , C09J5/02 , B23B3/26 , B23K26/0006 , B23K26/324 , B23K26/354 , B23K2103/10 , B29C65/48 , B29C65/52 , B29C66/112 , B29C66/43 , B29C66/73185 , B29C66/7422 , B29L2009/003 , B29L2031/30 , B29L2031/3002 , B32B15/18 , B32B2260/00 , B32B2305/00 , B32B2307/702 , B32B2307/752 , B32B2310/0806 , B32B2311/24 , B32B2605/00 , B62D27/026 , C09J2205/31 , C09J2400/166 , Y10S148/138 , Y10S148/903 , Y10T29/49906 , Y10T428/24545 , Y10T428/24612
摘要： An amorphous structure layer is formed on a surface layer of a bonded portion of each of side brackets. A bottomed hole layer including a plurality of bottomed holes is formed on a surface layer of the amorphous structure layer. Each of the bottomed holes has a reverse-tapered shape, which has, between an opening portion and a bottom portion of each of the bottomed holes, a bulged portion having a larger inner circumference than the opening portion. An adhesive is injected into the bottomed holes. An outer circumferential surface of the bonded portion of each of the side brackets and an inner circumferential surface of an end portion of a center beam face toward each other with the adhesive interposed therebetween.

8. 发明授权

US5877063A Method of forming rough polysilicon surfaces 失效
标题翻译：形成粗多晶硅表面的方法
公开(公告)号：US5877063A
公开(公告)日：1999-03-02
申请号：US502906
申请日：1995-07-17
申请人： Robin Lee Gilchrist
发明人： Robin Lee Gilchrist
IPC分类号： H01L21/02 , H01L21/20
CPC分类号： H01L28/82 , Y10S148/138
摘要： A semiconductor processing method of providing a polysilicon film having induced outer surface roughness includes, a) providing a polysilicon layer over a substrate, the polysilicon layer having an outer surface of a first degree of roughness; b) providing a layer of a refractory metal silicide over the outer surface of the polysilicon layer, the refractory metal silicide preferably being WSi.sub.x where "x" is initially from 1.0 to 2.5, the WSi.sub.x layer and the polysilicon layer outer surface defining a first interface therebetween; c) annealing the substrate at a temperature and for a time period which are effective to transform the WSi.sub.x into a tetragonal crystalline structure and to transform the first interface into a different second interface, the WSi.sub.x layer not being in a tetragonal crystalline state prior to the anneal, the WSi.sub.x at the second interface having an increased value of "x" from the initial value of "x"; and d) etching the WSi.sub.x layer from the polysilicon layer at least to the second interface to leave an outer polysilicon surface having a second degree of roughness, the second degree of roughness being greater than the first degree of roughness. A capacitor having a conductive plate comprising a polysilicon film produced by the process is also disclosed.
摘要翻译：提供具有诱导外表面粗糙度的多晶硅膜的半导体处理方法包括：a）在衬底上提供多晶硅层，所述多晶硅层具有第一粗糙度的外表面; b）在多晶硅层的外表面上提供难熔金属硅化物层，难熔金属硅化物优选为WSix，其中“x”最初为1.0至2.5，所述WSix层和多晶硅层外表面限定第一界面之间; c）在有效将WSix转变成四方晶体结构并将第一界面转变成不同的第二界面的温度和时间段退火衬底，WSix层在第四界面之前不处于四方晶状态在第二接口处的WSix与初始值“x”具有增加的值“x”; 以及d）至少将所述WSix层从所述多晶硅层蚀刻到所述第二界面以留下具有第二程度粗糙度的外多晶硅表面，所述第二粗糙度大于所述第一粗糙度。还公开了一种具有包括通过该工艺生产的多晶硅膜的导电板的电容器。

9. 发明授权

US5597760A Process of fabricating semiconductor device having capacitor increased in capacitance by roughening surface of accumulating electrode 失效
标题翻译：制造具有电容器的半导体器件的工艺通过累积电极的粗糙化表面增加电容
公开(公告)号：US5597760A
公开(公告)日：1997-01-28
申请号：US589268
申请日：1996-01-22
申请人： Toshiyuki Hirota
发明人： Toshiyuki Hirota
IPC分类号： H01L27/04 , H01L21/02 , H01L21/205 , H01L21/306 , H01L21/318 , H01L21/822 , H01L21/8242 , H01L27/108 , H01L21/70
CPC分类号： H01L28/84 , Y10S148/014 , Y10S148/138 , Y10S438/964
摘要： Boundary layers of silicon nitride not greater than 1 nanometer thick are inserted between adjacent two phosphorous-doped polysilicon layers forming parts of an accumulating electrode of a capacitor so as to decrease the grain size of the polysilicon and, accordingly, increase the grain boundaries exposed to the surfaces of the phosphorous-doped polysilicon layers, and hot phosphoric acid selectively etches the grain boundaries, thereby increasing the surface area of the phosphorous-doped polysilicon layers.
摘要翻译：在相邻的两个掺磷多晶硅层之间插入不大于1纳米厚的氮化硅的边界层，以形成电容器的累积电极的一部分，从而降低多晶硅的晶粒尺寸，并因此增加暴露于磷掺杂多晶硅层的表面和热磷酸选择性地蚀刻晶界，从而增加磷掺杂多晶硅层的表面积。

10. 发明授权

US5543347A Method of forming silicon film having jagged surface 失效
标题翻译：形成具有锯齿状表面的硅膜的方法
公开(公告)号：US5543347A
公开(公告)日：1996-08-06
申请号：US363941
申请日：1994-12-27
申请人： Hideo Kawano , Keiji Shiotani , Masao Mikami , Tatsuya Suzuki , Seiichi Shishiguchi
发明人： Hideo Kawano , Keiji Shiotani , Masao Mikami , Tatsuya Suzuki , Seiichi Shishiguchi
IPC分类号： H01L21/302 , H01L21/02 , H01L21/20 , H01L21/3065 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/10 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L28/84 , Y10S148/138 , Y10S438/964
摘要： First, a metal layer is deposited on a silicon film surface to form a silicide layer in an interface between the silicon film and the metal layer. Subsequently, the metal layer is all removed by etching such that silicide islands are left on the surface of the silicon film, and then the exposed silicon film surface is dry-etched by using the silicide islands as a selective mask.
摘要翻译：首先，在硅膜表面上沉积金属层，以在硅膜和金属层之间的界面中形成硅化物层。随后，通过蚀刻去除金属层，使得硅膜的表面上留下硅化物岛，然后通过使用硅化物岛作为选择性掩模来干蚀刻暴露的硅膜表面。

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