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1. 发明授权

US06034394A Methods and arrangements for forming a floating gate in non-volatile memory semiconductor devices 失效
标题翻译：在非易失性存储器半导体器件中形成浮置栅极的方法和装置
公开(公告)号：US06034394A
公开(公告)日：2000-03-07
申请号：US992950
申请日：1997-12-18
申请人： Mark Ramsbey , Tuan D. Pham , Yu Sun , Kenneth W. Au
发明人： Mark Ramsbey , Tuan D. Pham , Yu Sun , Kenneth W. Au
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324
摘要： Methods and arrangements are provided to increase the process control during the fabrication of the floating/control gate configuration in a non-volatile memory semiconductor device. The methods and arrangements effectively reduce the severity of the topology attributable to the space between adjacent floating gates, by advantageously reducing the thickness of the floating gates. The altered topology allows a subsequently formed control gate to be formed without significant surface depressions. Significant surface depressions in the control gate can lead to cracks in the silicide layer that is formed on the control gate. The cracking usually occurs during subsequent thermal processing of the semiconductor device. Thus the disclosed methods and arrangements prevent cracking of the silicide layer on the control gate, which can affect the performance of the semiconductor device by increasing the resistance of the control gate arrangement.
摘要翻译：提供了在非易失性存储器半导体器件中制造浮置/控制栅极配置期间增加处理控制的方法和装置。通过有利地减小浮动栅极的厚度，这些方法和布置有效地降低了归因于相邻浮动栅极之间的空间的拓扑的严重性。改变的拓扑允许随后形成的控制栅极形成而没有显着的表面凹陷。控制栅中的显着的表面凹陷可能导致在控制栅上形成的硅化物层中的裂纹。裂纹通常发生在半导体器件的随后热处理期间。因此，所公开的方法和布置防止了控制栅极上的硅化物层的破裂，这可以通过增加控制栅极布置的电阻来影响半导体器件的性能。

2. 发明授权

US06274433B1 Methods and arrangements for forming a floating gate in non-volatile memory semiconductor devices 有权
标题翻译：在非易失性存储器半导体器件中形成浮置栅极的方法和装置
公开(公告)号：US06274433B1
公开(公告)日：2001-08-14
申请号：US09476121
申请日：2000-01-03
申请人： Mark Ramsbey , Tuan D. Pham , Yu Sun , Kenneth W. Au
发明人： Mark Ramsbey , Tuan D. Pham , Yu Sun , Kenneth W. Au
IPC分类号： H01L218247
CPC分类号： H01L27/11521 , H01L27/115 , H01L29/42324
摘要： Methods and arrangements are provided to increase the process control during the fabrication of the floating/control gate configuration in a non-volatile memory semiconductor device. The methods and arrangements effectively reduce the severity of the topology attributable to the space between adjacent floating gates, by advantageously reducing the thickness of the floating gates. The altered topology allows a subsequently formed control gate to be formed without significant surface depressions. Significant surface depressions in the control gate can lead to cracks in the silicide layer that is formed on the control gate. The cracking usually occurs during subsequent thermal processing of the semiconductor device. Thus the disclosed methods and arrangements prevent cracking of the silicide layer on the control gate, which can affect the performance of the semiconductor device by increasing the resistance of the control gate arrangement.
摘要翻译：提供了在非易失性存储器半导体器件中制造浮置/控制栅极配置期间增加处理控制的方法和装置。通过有利地减小浮动栅极的厚度，这些方法和布置有效地降低了归因于相邻浮动栅极之间的空间的拓扑的严重性。改变的拓扑允许随后形成的控制栅极形成而没有显着的表面凹陷。控制栅中的显着的表面凹陷可能导致在控制栅上形成的硅化物层中的裂纹。裂纹通常发生在半导体器件的随后热处理期间。因此，所公开的方法和布置防止了控制栅极上的硅化物层的破裂，这可以通过增加控制栅极布置的电阻来影响半导体器件的性能。

3. 发明授权

US07012008B1 Dual spacer process for non-volatile memory devices 有权
标题翻译：用于非易失性存储器件的双间隔器工艺
公开(公告)号：US07012008B1
公开(公告)日：2006-03-14
申请号：US09728554
申请日：2000-12-01
申请人： Jeffrey A. Shields , Tuan D. Pham , Mark T. Ramsbey , Yu Sun , Angela T. Hui , Maria Chow Chan
发明人： Jeffrey A. Shields , Tuan D. Pham , Mark T. Ramsbey , Yu Sun , Angela T. Hui , Maria Chow Chan
IPC分类号： H01L21/31
CPC分类号： H01L27/11568 , H01L27/11526 , H01L27/11531
摘要： In a two-step spacer fabrication process for a non-volatile memory device, a thin oxide layer is deposited on a wafer substrate leaving a gap in the core of the non-volatile memory device. Implantation and/or oxide-nitride-oxide removal can be accomplished through this gap. After implantation, a second spacer is deposited. After the second spacer deposition, a periphery spacer etch is performed. By the above method, a spacer is formed.
摘要翻译：在用于非易失性存储器件的两步间隔件制造工艺中，薄的氧化物层沉积在晶片衬底上，在非易失性存储器件的芯中留下间隙。可通过该间隙实现植入和/或氧化氮化物 - 氧化物去除。植入后，沉积第二间隔物。在第二间隔物沉积之后，执行外围间隔物蚀刻。通过上述方法，形成间隔物。

4. 发明授权

US5966618A Method of forming dual field isolation structures 失效
标题翻译：形成双场隔离结构的方法
公开(公告)号：US5966618A
公开(公告)日：1999-10-12
申请号：US36288
申请日：1998-03-06
申请人： Yu Sun , Tuan D. Pham , Mark T. Ramsbey , Chi Chang
发明人： Yu Sun , Tuan D. Pham , Mark T. Ramsbey , Chi Chang
IPC分类号： H01L21/316 , H01L21/76 , H01L21/762 , H01L27/08 , H01L27/105
CPC分类号： H01L21/76221 , H01L27/105
摘要： A method of providing thick and thin oxide structures reduces step changes between a core region and a peripheral region on an integrated circuit. Thin LOCOS structures are provided in a core region of a flash memory device, and thick LOCOS structures are provided in a peripheral region of the flash memory device. The device and process are not as susceptible to "race track" problems, "oxide" bump problems, and "stringer" problems. The process utilizes two separate nitride or hard mask layers.
摘要翻译：提供厚且薄的氧化物结构的方法减小了集成电路上的芯区域和周边区域之间的阶跃变化。在闪速存储器件的核心区域中提供了薄的LOCOS结构，并且在闪速存储器件的外围区域中提供了厚的LOCOS结构。设备和过程不容易受到“赛道”问题，“氧化物”碰撞问题和“纵梁”问题的影响。该方法利用两个分开的氮化物或硬掩模层。

5. 发明授权

US06808996B1 Method for protecting gate edges from charge gain/loss in semiconductor device 有权
标题翻译：在半导体器件中保护栅极边缘免受电荷增益/损耗的方法
公开(公告)号：US06808996B1
公开(公告)日：2004-10-26
申请号：US09376659
申请日：1999-08-18
申请人： Tuan D. Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui , Yu Sun , Chi Chang
发明人： Tuan D. Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui , Yu Sun , Chi Chang
IPC分类号： H01L21336
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method for making a ULSI MOSFET includes covering core gate stacks with a first protective layer, etching away the first layer such that intended source regions of the substrate are exposed, and implanting dopant into the source regions. A second protective layer is then deposited over the first layer and is etched back to conform to the first layer, covering only the sides of the gate stacks, and exposing intended drain regions of the substrate. Dopant is then implanted into the drain regions. During subsequent manufacturing steps including ILD formation and metallization, mobile ions and other process-induced charges are blocked from entering the floating gates of the gate stacks by the protective layers, thereby preventing unwanted charge gain/loss.
摘要翻译：制造ULSI MOSFET的方法包括用第一保护层覆盖芯栅极叠层，蚀刻掉第一层，使得衬底的预期源极区域暴露，并将掺杂剂注入到源极区域中。然后在第一层上沉积第二保护层，并将其回蚀刻以符合第一层，仅覆盖栅极堆叠的侧面，并暴露衬底的预期漏极区域。然后将掺杂剂注入漏区。在包括ILD形成和金属化的后续制造步骤期间，阻止移动离子和其它工艺感应电荷被保护层进入栅极堆叠的浮置栅极，从而防止不必要的电荷增益/损耗。

6. 发明授权

US06455373B1 Semiconductor device having gate edges protected from charge gain/loss 有权
标题翻译：具有防止电荷增益/损耗的栅极边缘的半导体器件
公开(公告)号：US06455373B1
公开(公告)日：2002-09-24
申请号：US09834419
申请日：2001-04-12
申请人： Tuan D. Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui , Yu Sun , Chi Chang
发明人： Tuan D. Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui , Yu Sun , Chi Chang
IPC分类号： H01L21336
CPC分类号： H01L27/11526 , H01L21/823468 , H01L27/105 , H01L27/11536
摘要： A plurality of core gate stacks and periphery gates on the substrate, each core gate stack and periphery gate having at least one side and first and second protective shoulders formed on said plurality of core gate stacks and periphery gates, such that a dopant can be implanted sequentially into source and drain regions of a substrate supporting the stacks to establish transistors and such that charge migration into said at least one side of the gate stacks during interlayer dielectric (ILD) formation and device metallization is prevented, at least the second shoulder being frabricated from at least one material selected from a group consisting essentially of nitride and silicon oxynitride (SiON).
摘要翻译：在基板上的多个核心栅极叠层和周边栅极，每个芯栅极叠层和周边栅极具有形成在所述多个芯栅极叠层和外围栅极上的至少一个侧面和第一和第二保护肩部，使得掺杂剂可被植入顺序地进入支撑堆叠的衬底的源极和漏极区域以建立晶体管，并且防止在层间电介质（ILD）形成和器件金属化期间电荷迁移到栅极叠层的所述至少一个侧面，至少第二肩部被破坏选自由氮化物和氮氧化硅（SiON）组成的组中的至少一种材料。

7. 发明授权

US06248627B1 Method for protecting gate edges from charge gain/loss in semiconductor device 有权
标题翻译：在半导体器件中保护栅极边缘免受电荷增益/损耗的方法
公开(公告)号：US06248627B1
公开(公告)日：2001-06-19
申请号：US09376658
申请日：1999-08-18
申请人： Tuan D. Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui , Yu Sun , Chi Chang
发明人： Tuan D. Pham , Mark T. Ramsbey , Sameer S. Haddad , Angela T. Hui , Yu Sun , Chi Chang
IPC分类号： H01L21336
CPC分类号： H01L27/11526 , H01L21/823468 , H01L27/105 , H01L27/11536
摘要： A method for making a ULSI MOSFET includes covering core gate stacks with a first protective layer, etching away the first layer such that intended source regions of the substrate are exposed, and implanting dopant into the source regions. A second protective layer is then deposited over the first layer and is etched back to conform to the first layer, covering only the sides of the gate stacks, and exposing intended drain regions of the substrate. Dopant is then implanted into the drain regions. During subsequent manufacturing steps including ILD formation and metallization, mobile ions and other process-induced charges are blocked from entering the floating gates of the gate stacks by the protective layers, thereby preventing unwanted charge gain/loss.
摘要翻译：制造ULSI MOSFET的方法包括用第一保护层覆盖芯栅极叠层，蚀刻掉第一层，使得衬底的预期源极区域暴露，并将掺杂剂注入到源极区域中。然后在第一层上沉积第二保护层，并将其回蚀刻以符合第一层，仅覆盖栅极堆叠的侧面，并暴露衬底的预期漏极区域。然后将掺杂剂注入漏区。在包括ILD形成和金属化的后续制造步骤期间，阻止移动离子和其它工艺感应电荷被保护层进入栅极堆叠的浮置栅极，从而防止不必要的电荷增益/损耗。

8. 发明授权

US5920786A Method for fabricating shallow isolation trenches using angular photoresist profiles to create sloped isolation trench walls 失效
标题翻译：使用角度光致抗蚀剂轮廓制造浅隔离沟槽以产生倾斜的隔离沟壁的方法
公开(公告)号：US5920786A
公开(公告)日：1999-07-06
申请号：US60894
申请日：1998-05-14
申请人： Tuan D. Pham , Michael K. Templeton
发明人： Tuan D. Pham , Michael K. Templeton
IPC分类号： G03F7/00 , G03F7/20 , H01L21/3065 , H01L21/308 , H01L21/762 , H01L29/68 , G03C5/00 , G03F9/00
CPC分类号： H01L21/3086 , G03F7/0035 , G03F7/201 , H01L21/3065 , H01L21/76232
摘要： The present invention provides a method of constructing trenches for use in microelectronic circuit structures. A photolithographic method is used to create trenches with sloped walls shaping the photoresist masks into sloped profiles. These photoresist masks effectively shape the underlying substrate during subsequent etch steps producing sloped wall trenches. These trenches can be used as shallow trench isolation structures to isolate microelectronic circuit structures from each other.
摘要翻译：本发明提供一种构建用于微电子电路结构的沟槽的方法。使用光刻方法来产生具有将光致抗蚀剂掩模成形为倾斜轮廓的倾斜壁的沟槽。这些光致抗蚀剂掩模在随后的蚀刻步骤中有效地塑造下面的衬底，产生倾斜的壁沟槽。这些沟槽可以用作浅沟槽隔离结构，以隔离微电子电路结构。

9. 发明申请

US20080144384A1 METHODS FOR ACTIVE BOOSTING TO MINIMIZE CAPACITIVE COUPLING EFFECT BETWEEN ADJACENT GATES OF FLASH MEMORY DEVICES 有权
标题翻译：用于主动加速以最小化闪存存储器件相邻栅极之间的电容耦合效应的方法
公开(公告)号：US20080144384A1
公开(公告)日：2008-06-19
申请号：US12031640
申请日：2008-02-14
申请人： Tuan D. Pham , Masaaki Higashitani , Hao Fang , Gerrit Jan Hemink
发明人： Tuan D. Pham , Masaaki Higashitani , Hao Fang , Gerrit Jan Hemink
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , H01L23/5222 , H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11534 , H01L2924/0002 , H01L2924/00
摘要： A NAND flash memory device incorporates a unique booster plate design. The booster plate is biased during read and program operations and the coupling to the floating gates in many cases reduces the voltage levels necessary to program and read the charge stored in the gates. The booster plate also shields against unwanted coupling between floating gates. Self boosting, local self boosting, and erase area self boosting modes used with the unique booster plate further improve read/write reliability and accuracy. A more compact and reliable memory device can hence be realized according to the present invention.
摘要翻译： NAND闪存器件采用独特的增压板设计。升压板在读取和编程操作期间被偏置，并且在许多情况下与浮动栅极的耦合降低了编程和读取存储在栅极中的电荷所需的电压电平。升压板还屏蔽浮动栅极之间的不必要的耦合。自升压，局部自升压，以及独特升压板使用的擦除区域自升压模式，进一步提高了读/写可靠性和精度。因此，根据本发明可以实现更紧凑和可靠的存储器件。

10. 发明申请

US20090155967A1 METHOD OF FORMING MEMORY WITH FLOATING GATES INCLUDING SELF-ALIGNED METAL NANODOTS USING A COUPLING LAYER 有权
标题翻译：使用耦合层形成包含自对准金属纳米线的浮动栅的存储器的方法
公开(公告)号：US20090155967A1
公开(公告)日：2009-06-18
申请号：US11958941
申请日：2007-12-18
申请人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai , Tuan D. Pham
发明人： Vinod Robert Purayath , George Matamis , Takashi Orimoto , James Kai , Tuan D. Pham
IPC分类号： H01L21/336
CPC分类号： H01L21/28273 , B82Y10/00 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/42332 , Y10S438/962 , Y10S977/72 , Y10S977/81 , Y10S977/943
摘要： Techniques are provided for fabricating memory with metal nanodots as charge-storing elements. In an example approach, a coupling layer such as an amino functional silane group is provided on a gate oxide layer on a substrate. The substrate is dip coated in a colloidal solution having metal nanodots, causing the nanodots to attach to sites in the coupling layer. The coupling layer is then dissolved such as by rinsing or nitrogen blow drying, leaving the nanodots on the gate oxide layer. The nanodots react with the coupling layer and become negatively charged and arranged in a uniform monolayer, repelling a deposition of an additional monolayer of nanodots. In a configuration using a control gate over a high-k dielectric floating gate which includes the nanodots, the control gates may be separated by etching while the floating gate dielectric extends uninterrupted since the nanodots are electrically isolated from one another.
摘要翻译：提供了用于制造具有金属纳米点作为电荷存储元件的存储器的技术。在示例性方法中，在基板上的栅极氧化物层上提供诸如氨基官能的硅烷基团之类的耦合层。将基底浸渍在具有金属纳米点的胶体溶液中，使得纳米点附着到偶联层中的位置。然后通过漂洗或氮吹干燥将溶剂层溶解，将纳米点留在栅极氧化物层上。纳米点与偶联层反应并变成负电荷并排列成均匀的单层，排斥另外的单层纳米点的沉积。在使用包括纳米点的高k电介质浮动栅极上的控制栅极的配置中，可以通过蚀刻来分离控制栅极，同时浮栅绝缘体不间断延伸，因为纳米点彼此电隔离。

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