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31. 发明授权

US5852572A Small-sized static random access memory cell 失效
标题翻译：小型静态随机存取存储单元
公开(公告)号：US5852572A
公开(公告)日：1998-12-22
申请号：US906270
申请日：1997-08-05
申请人： Soon-moon Jung , Yun-seung Shin
发明人： Soon-moon Jung , Yun-seung Shin
IPC分类号： G11C11/413 , G11C11/412 , H01L21/8244 , H01L27/11 , G11C11/34
CPC分类号： G11C11/412
摘要： A SRAM cell includes a single line used as both a word line and a power supply voltage line, a first and a second load element, a first and a second NMOS driver transistor, and a first and a second PMOS access transistor. Each of the two load elements is connected between the line and one of two storage nodes. The first load element is connected between the single line and a first storage node. The second load element is connected between the single line and a second storage node. The first NMOS driver transistor is connected between the first storage node and ground. The second driver transistor is connected between the second storage node and ground. The first access transistor is connected between the first storage node and a bit line and the second access transistor is connected between the second storage node and a complementary bit line. The first and second access transistors have gates commonly connected to the single line. The layout of the SRAM cell is simplified and the cell layout area is reduced because a single line is used as both the power supply voltage line and the word line.
摘要翻译： SRAM单元包括用作字线和电源电压线，第一和第二负载元件，第一和第二NMOS驱动晶体管以及第一和第二PMOS存取晶体管的单线。两个负载元件中的每一个连接在线路和两个存储节点中的一个之间。第一负载元件连接在单线和第一存储节点之间。第二负载元件连接在单线和第二存储节点之间。第一个NMOS驱动晶体管连接在第一个存储节点和地之间。第二驱动晶体管连接在第二存储节点和地之间。第一存取晶体管连接在第一存储节点和位线之间，第二存取晶体管连接在第二存储节点和互补位线之间。第一和第二存取晶体管具有通常连接到单线的门。由于单电源线作为电源电压线和字线，因此简化了SRAM单元的布局，并且单元布局面积减小。

32. 发明授权

US5414302A Semiconductor device with a multilayered contact structure having a boro-phosphate silicate glass planarizing layer 失效
标题翻译：具有多孔接触结构的半导体器件，其具有硼磷酸盐硅酸盐玻璃平坦化层
公开(公告)号：US5414302A
公开(公告)日：1995-05-09
申请号：US188113
申请日：1994-01-28
申请人： Yun-seung Shin , Sung-nam Chang
发明人： Yun-seung Shin , Sung-nam Chang
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/485 , H01L27/10 , H01L23/48 , H01L29/10 , H01L29/44 , H01L29/52
CPC分类号： H01L21/76802 , H01L23/485 , H01L24/05 , H01L2924/00014 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01033 , H01L2924/13091
摘要： A high-density semiconductor memory device has a self-aligning contact structure for electrical connection between lower and upper conductive layers, and an inter-insulating layer with a via for forming the contact structure. The contact structure has a contact pad including a first conductive layer electrically connected with the lower conductive layer within the via and formed on a predetermined portion of the inter-insulating layer around the groove, a planarizing material filling up the groove formed on the first conductive layer, and second conductive layers formed on the planarizing material and exposed first conductive layer.
摘要翻译：高密度半导体存储器件具有用于下导电层和上导电层之间的电连接的自对准接触结构，以及具有用于形成接触结构的通孔的绝缘层。所述接触结构具有接触焊盘，所述接触焊盘包括与所述通路内的所述下导电层电连接并形成在所述槽周围的所述绝缘层的预定部分上的第一导电层，填充形成在所述第一导电层和形成在平坦化材料上并暴露的第一导电层的第二导电层。

33. 发明授权

US4948990A BiCMOS inverter circuit 失效
标题翻译： BiCMOS逆变电路
公开(公告)号：US4948990A
公开(公告)日：1990-08-14
申请号：US292883
申请日：1989-01-03
申请人： Yun-Seung Shin , Sung-Ki Min
发明人： Yun-Seung Shin , Sung-Ki Min
IPC分类号： H03K17/567 , H03K19/00 , H03K19/013 , H03K19/08 , H03K19/0944
CPC分类号： H03K19/09448 , H03K19/0136
摘要： A BiCMOS inverter circuit having complementary MOS transistors and complementary bipolar transistors enables a high speed inverting operation as well as high degree of integration when it is fabricated on a semiconductor chip. The inverter circuit may further include another complementary MOS transistors to allow the logic output to be advantageously full switched in the range of V.sub.cc -0 V keeping the high speed operation.
摘要翻译：具有互补MOS晶体管和互补双极晶体管的BiCMOS逆变器电路在半导体芯片上制造时能够实现高速反相操作以及高集成度。逆变器电路还可以包括另一个互补MOS晶体管，以允许逻辑输出有利地在保持高速操作的Vcc-0V的范围内全切换。

34. 发明授权

US08284129B2 Light emitting pixel and apparatus for driving the same 有权
标题翻译：发光像素及其驱动装置
公开(公告)号：US08284129B2
公开(公告)日：2012-10-09
申请号：US13174008
申请日：2011-06-30
申请人： Yun Seung Shin , Jong Hak Baek
发明人： Yun Seung Shin , Jong Hak Baek
IPC分类号： G09G3/30 , G09G3/10
CPC分类号： G09G3/2022 , G09G3/3258 , G09G2300/0852 , G09G2300/0866 , G09G2310/0256 , G09G2320/043 , G09G2330/021
摘要： A light emitting pixel includes a first organic light emitting diode (OLED) and a capacitor supplying to the first OLED current generated by an electric charge corresponding to a difference between a first voltage supplied to a first electrode of the capacitor and a second voltage supplied to a second electrode of the capacitor. The light emitting pixel further include a second OLED to supply the first voltage to the first electrode. The light emitting pixel further includes a voltage supply device to supply the first voltage to the first electrode in response to the second voltage.
摘要翻译：发光像素包括第一有机发光二极管（OLED）和向由电荷产生的电荷产生的第一OLED电流供应的电容，所述电荷对应于提供给电容器的第一电极的第一电压与提供给电容器的第一电极的第二电压之间的差，电容器的第二电极。发光像素还包括向第一电极提供第一电压的第二OLED。发光像素还包括电压供应装置，用于响应于第二电压向第一电极提供第一电压。

35. 发明申请

US20110261044A1 LIGHT EMITTING PIXEL AND APPARATUS FOR DRIVING THE SAME 有权
标题翻译：发光像素及其驱动装置
公开(公告)号：US20110261044A1
公开(公告)日：2011-10-27
申请号：US13174008
申请日：2011-06-30
申请人： YUN-SEUNG SHIN , Yong Hak Baek
发明人： YUN-SEUNG SHIN , Yong Hak Baek
IPC分类号： G06F3/038 , G09G3/32
CPC分类号： G09G3/2022 , G09G3/3258 , G09G2300/0852 , G09G2300/0866 , G09G2310/0256 , G09G2320/043 , G09G2330/021
摘要： A light emitting pixel includes a first organic light emitting diode (OLED) and a capacitor supplying to the first OLED current generated by an electric charge corresponding to a difference between a first voltage supplied to a first electrode of the capacitor and a second voltage supplied to a second electrode of the capacitor. The light emitting pixel further include a second OLED to supply the first voltage to the first electrode. The light emitting pixel further includes a voltage supply device to supply the first voltage to the first electrode in response to the second voltage.
摘要翻译：发光像素包括第一有机发光二极管（OLED）和向由电荷产生的电荷产生的第一OLED电流供应的电容，所述电荷对应于提供给电容器的第一电极的第一电压与提供给电容器的第一电极的第二电压之间的差，电容器的第二电极。发光像素还包括向第一电极提供第一电压的第二OLED。发光像素还包括电压供应装置，用于响应于第二电压向第一电极提供第一电压。

36. 发明授权

US07851878B2 Magnetic memory device and method of fabricating the same 失效
标题翻译：磁记忆装置及其制造方法
公开(公告)号：US07851878B2
公开(公告)日：2010-12-14
申请号：US12507504
申请日：2009-07-22
申请人： Woo-Yeong Cho , Yun-Seung Shin , Hyun-Geun Byun , Choong-Keun Kwak
发明人： Woo-Yeong Cho , Yun-Seung Shin , Hyun-Geun Byun , Choong-Keun Kwak
IPC分类号： H01L29/82 , G11C11/02
CPC分类号： H01L27/224 , B82Y10/00 , G11C11/161 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： A magnetic memory device includes a common line; a first write-in diode, a readout diode and a second write-in diode being connected to the common line in parallel. The magnetic memory device further includes a magnetic tunnel junction structure connected to the readout diode, first and second write-in conductors disposed at both sides of the magnetic tunnel junction structure and connected to the first and second write-in diodes, respectively and a first write-in line, a readout line and a second write-in line, which are connected to the first write-in conductor, the magnetic tunnel injection structure, and the second write-in conductor, respectively.
摘要翻译：磁存储器件包括公共线; 第一写入二极管，读出二极管和第二写入二极管并联连接到公共线。磁存储器件还包括连接到读出二极管的磁隧道结结构，分别设置在磁隧道结结构的两侧并连接到第一和第二写入二极管的第一和第二写入导体，写入线，读出线和第二写入线，分别连接到第一写入导体，磁隧道注入结构和第二写入导体。

37. 发明授权

US07791929B2 Magnetoresistive RAM and associated methods 失效
标题翻译：磁阻RAM及相关方法
公开(公告)号：US07791929B2
公开(公告)日：2010-09-07
申请号：US11902711
申请日：2007-09-25
申请人： Woo-yeong Cho , Yun-seung Shin
发明人： Woo-yeong Cho , Yun-seung Shin
IPC分类号： G11C11/00
CPC分类号： G11C11/1675 , G11C11/1655 , G11C11/1659 , Y10S977/935
摘要： A magnetoresistive random access memory (RAM) may include a plurality of variable resistance devices, a plurality of read bitlines electrically connected to respective variable resistance devices, and a plurality of write bitlines alternating with the read bitlines. The magnetoresistive RAM may be configured to apply a first write current through a first write bitline adjacent to a first variable resistance device when writing a first data to the first variable resistance device, and apply a first inhibition current through a second write bitline adjacent to a second variable resistance device, the second variable resistance device being adjacent to the first write bitline, and between the first write bitline and the second write bitline, and the first write current and the first inhibition current flowing in a same direction.
摘要翻译：磁阻随机存取存储器（RAM）可以包括多个可变电阻器件，电连接到相应的可变电阻器件的多个读位线以及与读位线交替的多个写位线。磁阻RAM可以被配置为当向第一可变电阻器件写入第一数据时，通过与第一可变电阻器件相邻的第一写入位线施加第一写入电流，并且将第一写入电流施加到与第一可写入位置相邻的第二写入位置第二可变电阻器件，第二可变电阻器件与第一写入位线相邻，第一写入位线和第二写入位线之间以及第一写入电流和第一抑制电流沿相同的方向流动。

38. 发明申请

US20090325374A1 Methods of Fabricating Nonvolatile Memory Devices 审中-公开
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US20090325374A1
公开(公告)日：2009-12-31
申请号：US12556757
申请日：2009-09-10
申请人： Jung-Dal Choi , Yun-Seung Shin , Jong-Sun Sel
发明人： Jung-Dal Choi , Yun-Seung Shin , Jong-Sun Sel
IPC分类号： H01L21/28
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11531
摘要： Methods of fabricating nonvolatile memory devices are provided. An isolation layer is formed on a substrate. The substrate has a memory region and a well contact region and the isolation layer defines an active region of the substrate. A gate insulating layer is formed on the active region. The gate insulating layer is patterned to define an opening therein. The opening exposes at least a portion of the well contact region of the substrate and acts as a charge pathway for charges generated during a subsequent etch of the isolation layer. Related memory device are also provided.
摘要翻译：提供制造非易失性存储器件的方法。在基板上形成隔离层。衬底具有存储区和阱接触区，并且隔离层限定衬底的有源区。在有源区上形成栅极绝缘层。栅极绝缘层被图案化以在其中限定开口。开口暴露衬底的阱接触区域的至少一部分，并且充当用于隔离层的后续蚀刻期间产生的电荷的电荷路径。还提供了相关的存储器件。

39. 发明授权

US07595747B2 Digital-to-analog converter, and method thereof 失效
标题翻译：数模转换器及其方法
公开(公告)号：US07595747B2
公开(公告)日：2009-09-29
申请号：US11971320
申请日：2008-01-09
申请人： Yun Seung Shin , Ji Woon Jung , Myung Hee Lee
发明人： Yun Seung Shin , Ji Woon Jung , Myung Hee Lee
IPC分类号： H03M1/66
CPC分类号： H03M1/0607 , G09G3/3688 , G09G3/3696 , G09G2310/027 , H03M1/662 , H03M1/682
摘要： A digital-to-analog converter (DAC) and a digital-to-analog converting method are provided. The DAC includes a first capacitor, an operation amplifier having a first input terminal connected to the first capacitor, a second input terminal, and an output terminal, where the first input terminal is a (−) input terminal and the second input terminal is a (+) input terminal; and a switching circuit having a plurality of switches each being switched in response to a corresponding switching signal from among a plurality of switching signals. The switching circuit performs switching so that the difference between a first voltage and a second voltage can be stored in the first capacitor connected to the operation amplifier during a first period, and performs switching so that an output signal can be output by reflecting a third voltage in the difference stored in the first capacitor during a second period.
摘要翻译：提供了数模转换器（DAC）和数模转换方法。 DAC包括第一电容器，具有连接到第一电容器的第一输入端子的运算放大器，第二输入端子和输出端子，其中第一输入端子是（ - ）输入端子，第二输入端子是（+）输入端子; 以及具有多个开关的开关电路，每个开关响应于来自多个开关信号的相应的开关信号而被切换。开关电路进行开关，使得第一电压和第二电压之间的差可以在第一时段期间存储在连接到运算放大器的第一电容器中，并且执行开关，使得可以通过反映第三电压来输出输出信号在第二时段期间存储在第一电容器中的差值。

40. 发明授权

US07582941B2 Magnetic memory device and method of fabricating the same 失效
标题翻译：磁记忆装置及其制造方法
公开(公告)号：US07582941B2
公开(公告)日：2009-09-01
申请号：US11480242
申请日：2006-06-30
申请人： Woo-Yeong Cho , Yun-Seung Shin , Hyun-Geun Byun , Choong-Keun Kwak
发明人： Woo-Yeong Cho , Yun-Seung Shin , Hyun-Geun Byun , Choong-Keun Kwak
IPC分类号： H01L29/82 , G11C11/02
CPC分类号： H01L27/224 , B82Y10/00 , G11C11/161 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： A magnetic memory device includes a common line; a first write-in diode, a readout diode and a second write-in diode being connected to the common line in parallel. The magnetic memory device further includes a magnetic tunnel junction structure connected to the readout diode, first and second write-in conductors disposed at both sides of the magnetic tunnel junction structure and connected to the first and second write-in diodes, respectively and a first write-in line, a readout line and a second write-in line, which are connected to the first write-in conductor, the magnetic tunnel injection structure, and the second write-in conductor, respectively.
摘要翻译：磁存储器件包括公共线; 第一写入二极管，读出二极管和第二写入二极管并联连接到公共线。磁存储器件还包括连接到读出二极管的磁隧道结结构，分别设置在磁隧道结结构的两侧并连接到第一和第二写入二极管的第一和第二写入导体，写入线，读出线和第二写入线，分别连接到第一写入导体，磁隧道注入结构和第二写入导体。

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