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1. 发明授权

US07151696B2 Integrated circuit memory devices having hierarchical bit line selection circuits therein 失效
公开(公告)号：US07151696B2
公开(公告)日：2006-12-19
申请号：US11041675
申请日：2005-01-24
申请人： Young-Ho Suh , Hyun-Geun Byun
发明人： Young-Ho Suh , Hyun-Geun Byun
IPC分类号： G11C11/34
CPC分类号： G11C7/12 , G11C7/18 , G11C2207/002 , H01L27/0688 , H01L27/1108
摘要： Integrated circuit memory devices include a first column of memory cells electrically coupled to a first pair of bit lines and a bit line precharge and selection circuit. This bit line precharge and selection circuit includes at least one stacked arrangement of thin-film transistors. These thin-film transistors include a first PMOS thin-film pull-up transistor and a first NMOS thin-film pass transistor. These thin-film transistors are electrically coupled to one of the first pair of bit lines. The first column of memory cells includes a column of TFT SRAM cells.

2. 发明授权

US08043869B2 Magnetic memory device and method of fabricating the same 失效
标题翻译：磁记忆装置及其制造方法
公开(公告)号：US08043869B2
公开(公告)日：2011-10-25
申请号：US12915335
申请日：2010-10-29
申请人： Woo-Yeong Cho , Yun-Seung Shin , Hyun-Geun Byun , Choong-Keun Kwak
发明人： Woo-Yeong Cho , Yun-Seung Shin , Hyun-Geun Byun , Choong-Keun Kwak
IPC分类号： H01L29/82
CPC分类号： H01L27/224 , B82Y10/00 , G11C11/161 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： A magnetic memory device includes a common line; a first write-in diode, a readout diode and a second write-in diode being connected to the common line in parallel. The magnetic memory device further includes a magnetic tunnel junction structure connected to the readout diode, first and second write-in conductors disposed at both sides of the magnetic tunnel junction structure and connected to the first and second write-in diodes, respectively and a first write-in line, a readout line and a second write-in line, which are connected to the first write-in conductor, the magnetic tunnel injection structure, and the second write-in conductor, respectively.
摘要翻译：磁存储器件包括公共线; 第一写入二极管，读出二极管和第二写入二极管并联连接到公共线。磁存储器件还包括连接到读出二极管的磁隧道结结构，分别设置在磁隧道结结构的两侧并连接到第一和第二写入二极管的第一和第二写入导体，写入线，读出线和第二写入线，分别连接到第一写入导体，磁隧道注入结构和第二写入导体。

3. 发明申请

US20070047295A1 Magnetic memory device and method of fabricating the same 失效
标题翻译：磁记忆装置及其制造方法
公开(公告)号：US20070047295A1
公开(公告)日：2007-03-01
申请号：US11480242
申请日：2006-06-30
申请人： Woo-Yeong Cho , Yun-Seung Shin , Hyun-Geun Byun , Choong-Keun Kwak
发明人： Woo-Yeong Cho , Yun-Seung Shin , Hyun-Geun Byun , Choong-Keun Kwak
IPC分类号： G11C11/00
CPC分类号： H01L27/224 , B82Y10/00 , G11C11/161 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： A magnetic memory device includes a common line; a first write-in diode, a readout diode and a second write-in diode being connected to the common line in parallel. The magnetic memory device further includes a magnetic tunnel junction structure connected to the readout diode, first and second write-in conductors disposed at both sides of the magnetic tunnel junction structure and connected to the first and second write-in diodes, respectively and a first write-in line, a readout line and a second write-in line, which are connected to the first write-in conductor, the magnetic tunnel injection structure, and the second write-in conductor, respectively.
摘要翻译：磁存储器件包括公共线; 第一写入二极管，读出二极管和第二写入二极管并联连接到公共线。磁存储器件还包括连接到读出二极管的磁隧道结结构，分别设置在磁隧道结结构的两侧并连接到第一和第二写入二极管的第一和第二写入导体，写入线，读出线和第二写入线，分别连接到第一写入导体，磁隧道注入结构和第二写入导体。

4. 发明申请

US20060062061A1 Integrated circuit memory devices having hierarchical bit line selection circuits therein 失效
标题翻译：具有分层位线选择电路的集成电路存储器件
公开(公告)号：US20060062061A1
公开(公告)日：2006-03-23
申请号：US11041675
申请日：2005-01-24
申请人： Young-Ho Suh , Hyun-Geun Byun
发明人： Young-Ho Suh , Hyun-Geun Byun
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/18 , G11C2207/002 , H01L27/0688 , H01L27/1108
摘要： Integrated circuit memory devices include a first column of memory cells electrically coupled to a first pair of bit lines and a bit line precharge and selection circuit. This bit line precharge and selection circuit includes at least one stacked arrangement of thin-film transistors. These thin-film transistors include a first PMOS thin-film pull-up transistor and a first NMOS thin-film pass transistor. These thin-film transistors are electrically coupled to one of the first pair of bit lines. The first column of memory cells includes a column of TFT SRAM cells.
摘要翻译：集成电路存储器件包括电耦合到第一对位线的第一列存储器单元和位线预充电和选择电路。该位线预充电和选择电路包括薄膜晶体管的至少一个堆叠布置。这些薄膜晶体管包括第一PMOS薄膜上拉晶体管和第一NMOS薄膜通过晶体管。这些薄膜晶体管电耦合到第一对位线之一。存储单元的第一列包括一列TFT SRAM单元。

5. 发明授权

US06594818B2 Memory architecture permitting selection of storage density after fabrication of active circuitry 有权
公开(公告)号：US06594818B2
公开(公告)日：2003-07-15
申请号：US09814565
申请日：2001-03-21
申请人： Su-Chul Kim , Hyun-Geun Byun , Kwang-Jin Lee , Jong-Cheol Lee , Uk-Rae Cho
发明人： Su-Chul Kim , Hyun-Geun Byun , Kwang-Jin Lee , Jong-Cheol Lee , Uk-Rae Cho
IPC分类号： G06F1750
CPC分类号： H01L27/0207 , H01L21/82 , H01L27/10897
摘要： A generic wafer includes memory units separated by scribe lanes. Memory chips of different storage capacities can be produced from different numbers of memory units on the generic wafer by forming one or more interconnect layer specialized according to a desired storage capacity and cutting the wafer using a sawing pattern according to the desired storage capacity. The specialized layer can be formed using different masks sets that form a different conductive pattern for each storage capacity or forming a generic interconnect structure with fuses that are cut to select the storage capacity of the memory chips

6. 发明授权

US07851878B2 Magnetic memory device and method of fabricating the same 失效
标题翻译：磁记忆装置及其制造方法
公开(公告)号：US07851878B2
公开(公告)日：2010-12-14
申请号：US12507504
申请日：2009-07-22
申请人： Woo-Yeong Cho , Yun-Seung Shin , Hyun-Geun Byun , Choong-Keun Kwak
发明人： Woo-Yeong Cho , Yun-Seung Shin , Hyun-Geun Byun , Choong-Keun Kwak
IPC分类号： H01L29/82 , G11C11/02
CPC分类号： H01L27/224 , B82Y10/00 , G11C11/161 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： A magnetic memory device includes a common line; a first write-in diode, a readout diode and a second write-in diode being connected to the common line in parallel. The magnetic memory device further includes a magnetic tunnel junction structure connected to the readout diode, first and second write-in conductors disposed at both sides of the magnetic tunnel junction structure and connected to the first and second write-in diodes, respectively and a first write-in line, a readout line and a second write-in line, which are connected to the first write-in conductor, the magnetic tunnel injection structure, and the second write-in conductor, respectively.
摘要翻译：磁存储器件包括公共线; 第一写入二极管，读出二极管和第二写入二极管并联连接到公共线。磁存储器件还包括连接到读出二极管的磁隧道结结构，分别设置在磁隧道结结构的两侧并连接到第一和第二写入二极管的第一和第二写入导体，写入线，读出线和第二写入线，分别连接到第一写入导体，磁隧道注入结构和第二写入导体。

7. 发明授权

US07582941B2 Magnetic memory device and method of fabricating the same 失效
标题翻译：磁记忆装置及其制造方法
公开(公告)号：US07582941B2
公开(公告)日：2009-09-01
申请号：US11480242
申请日：2006-06-30
申请人： Woo-Yeong Cho , Yun-Seung Shin , Hyun-Geun Byun , Choong-Keun Kwak
发明人： Woo-Yeong Cho , Yun-Seung Shin , Hyun-Geun Byun , Choong-Keun Kwak
IPC分类号： H01L29/82 , G11C11/02
CPC分类号： H01L27/224 , B82Y10/00 , G11C11/161 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： A magnetic memory device includes a common line; a first write-in diode, a readout diode and a second write-in diode being connected to the common line in parallel. The magnetic memory device further includes a magnetic tunnel junction structure connected to the readout diode, first and second write-in conductors disposed at both sides of the magnetic tunnel junction structure and connected to the first and second write-in diodes, respectively and a first write-in line, a readout line and a second write-in line, which are connected to the first write-in conductor, the magnetic tunnel injection structure, and the second write-in conductor, respectively.
摘要翻译：磁存储器件包括公共线; 第一写入二极管，读出二极管和第二写入二极管并联连接到公共线。磁存储器件还包括连接到读出二极管的磁隧道结结构，分别设置在磁隧道结结构的两侧并连接到第一和第二写入二极管的第一和第二写入导体，写入线，读出线和第二写入线，分别连接到第一写入导体，磁隧道注入结构和第二写入导体。

8. 发明申请

US20080303016A1 PHASE CHANGE MEMORY DEVICES EMPLOYING CELL DIODES AND METHODS OF FABRICATING THE SAME 有权
标题翻译：使用单元的相变存储器件及其制造方法
公开(公告)号：US20080303016A1
公开(公告)日：2008-12-11
申请号：US12196137
申请日：2008-08-21
申请人： Woo-Yeong Cho , Du-Eung Kim , Yun-Seung Shin , Hyun-Geun Byun , Sang-Beom Kang , Beak-Hyung Cho , Choong-Keun Kwak
发明人： Woo-Yeong Cho , Du-Eung Kim , Yun-Seung Shin , Hyun-Geun Byun , Sang-Beom Kang , Beak-Hyung Cho , Choong-Keun Kwak
IPC分类号： H01L45/00
CPC分类号： G11C13/0004 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1675
摘要： Phase change memory devices having cell diodes and related methods are provided, where the phase change memory devices include a semiconductor substrate of a first conductivity type and a plurality of parallel word lines disposed on the semiconductor substrate, the word lines have a second conductivity type different from the first conductivity type and have substantially flat top surfaces, a plurality of first semiconductor patterns are one-dimensionally arrayed on each word line along a length direction of the word line, the first semiconductor patterns have the first conductivity type or the second conductivity type, second semiconductor patterns having the first conductivity type are stacked on the first semiconductor patterns, an insulating layer is provided on the substrate having the second semiconductor patterns, the insulating layer fills gap regions between the word lines, gap regions between the first semiconductor patterns and gap regions between the second semiconductor patterns, a plurality of phase change material patterns are two-dimensionally arrayed on the insulating layer, and the phase change material patterns are electrically connected to the second semiconductor patterns, respectively.
摘要翻译：提供具有单元二极管和相关方法的相变存储器件，其中相变存储器件包括第一导电类型的半导体衬底和设置在半导体衬底上的多个平行字线，字线具有不同的第二导电类型从第一导电类型并且具有基本上平坦的顶表面，沿着字线的长度方向在每个字线上一维地排列多个第一半导体图案，第一半导体图案具有第一导电类型或第二导电类型具有第一导电类型的第二半导体图案堆叠在第一半导体图案上，在具有第二半导体图案的基板上设置绝缘层，绝缘层填充字线之间的间隙区域，第一半导体图案之间的间隙区域和第二半导体之间的间隙区域多个相变材料图案被二维排列在绝缘层上，并且相变材料图案分别电连接到第二半导体图案。

9. 发明授权

US07427531B2 Phase change memory devices employing cell diodes and methods of fabricating the same 有权
标题翻译：使用单元二极管的相变存储器件及其制造方法
公开(公告)号：US07427531B2
公开(公告)日：2008-09-23
申请号：US11324112
申请日：2005-12-30
申请人： Woo-Yeong Cho , Du-Eung Kim , Yun-Seung Shin , Hyun-Geun Byun , Sang-Beom Kang , Beak-Hyung Cho , Choong-Keun Kwak
发明人： Woo-Yeong Cho , Du-Eung Kim , Yun-Seung Shin , Hyun-Geun Byun , Sang-Beom Kang , Beak-Hyung Cho , Choong-Keun Kwak
IPC分类号： H01L21/06
CPC分类号： G11C13/0004 , G11C2213/72 , H01L27/2409 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/1675
摘要： Phase change memory devices having cell diodes and related methods are provided, where the phase change memory devices include a semiconductor substrate of a first conductivity type and a plurality of parallel word lines disposed on the semiconductor substrate, the word lines have a second conductivity type different from the first conductivity type and have substantially flat top surfaces, a plurality of first semiconductor patterns are one-dimensionally arrayed on each word line along a length direction of the word line, the first semiconductor patterns have the first conductivity type or the second conductivity type, second semiconductor patterns having the first conductivity type are stacked on the first semiconductor patterns, an insulating layer is provided on the substrate having the second semiconductor patterns, the insulating layer fills gap regions between the word lines, gap regions between the first semiconductor patterns and gap regions between the second semiconductor patterns, a plurality of phase change material patterns are two-dimensionally arrayed on the insulating layer, and the phase change material patterns are electrically connected to the second semiconductor patterns, respectively.
摘要翻译：提供具有单元二极管和相关方法的相变存储器件，其中相变存储器件包括第一导电类型的半导体衬底和设置在半导体衬底上的多个平行字线，字线具有不同的第二导电类型从第一导电类型并且具有基本上平坦的顶表面，沿着字线的长度方向在每个字线上一维地排列多个第一半导体图案，第一半导体图案具有第一导电类型或第二导电类型具有第一导电类型的第二半导体图案堆叠在第一半导体图案上，在具有第二半导体图案的基板上设置绝缘层，绝缘层填充字线之间的间隙区域，第一半导体图案之间的间隙区域和第二半导体之间的间隙区域多个相变材料图案被二维排列在绝缘层上，并且相变材料图案分别电连接到第二半导体图案。

10. 发明授权

US5754487A Bit line precharge circuit 失效
标题翻译：位线预充电电路
公开(公告)号：US5754487A
公开(公告)日：1998-05-19
申请号：US749277
申请日：1996-11-13
申请人： Du-Eung Kim , Choong-Keun Kwak , Young-Ho Suh , Hyun-Geun Byun
发明人： Du-Eung Kim , Choong-Keun Kwak , Young-Ho Suh , Hyun-Geun Byun
IPC分类号： G11C11/41 , G11C7/12 , G11C11/407 , G11C7/00
CPC分类号： G11C7/12
摘要： An SRAM, which includes a plurality of bit line pairs, a memory cell connected between each pair of the bit lines, and an address transition detection circuit for detecting transition of the externally applied address signal to generate a detection pulse signal, is provided with an improved bit line precharge circuit requiring only two transistors per bit line pair. The new precharge circuit is controlled by a bit line precharge control signal generator for generating a control signal determined by a ratio of impedances connected between a source voltage and ground voltage.
摘要翻译：包括多个位线对的SRAM，连接在每对位线之间的存储单元，以及用于检测外部施加的地址信号的转换以产生检测脉冲信号的地址转换检测电路，改进的位线预充电电路每位线对只需要两个晶体管。新的预充电电路由位线预充电控制信号发生器控制，用于产生由源电压和接地电压之间连接的阻抗比确定的控制信号。

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