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21. 发明授权

US5867433A Semiconductor memory with a novel column decoder for selecting a redundant array 失效
标题翻译：具有用于选择冗余阵列的新型列解码器的半导体存储器
公开(公告)号：US5867433A
公开(公告)日：1999-02-02
申请号：US893642
申请日：1997-07-11
申请人： Chiun-Chi Shen , Yen-Tai Lin , Jiang-Hong Ho , Jack-Lian Kuo , Howard Clayton Kirsch
发明人： Chiun-Chi Shen , Yen-Tai Lin , Jiang-Hong Ho , Jack-Lian Kuo , Howard Clayton Kirsch
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/785 , G11C29/832
摘要： Circuits and a method are described that integrate memory arrays, a redundant memory array, their associated decoders, sense amplifiers, and outputs into one module. This integration is achieved through the use of a column decoder with a fuse, which, when blown, permanently deselects the failing array and selects the redundant array. By OR'ing the redundant column select line of each column decoder, any column decoder can select the redundant array. Higher level array structures are produced by replication of the lower level array structure. The system output is generated by OR'ing together the respective data outputs of each array.
摘要翻译：描述了将存储器阵列，冗余存储器阵列，其相关解码器，读出放大器和输出集成到一个模块中的电路和方法。通过使用具有保险丝的列解码器来实现这种集成，当熔断器被熔断时，永久地取消选择故障阵列并选择冗余阵列。通过对每列解码器的冗余列选择行进行OR运算，任何列解码器都可以选择冗余阵列。较高级别的阵列结构是通过复制下层阵列结构产生的。系统输出是通过将每个阵列的各个数据输出进行OR组合来产生的。

22. 发明授权

US5786709A Integrated circuit output driver incorporating power distribution noise suppression circuitry 失效
标题翻译：集成电路输出驱动器，并入功率分配噪声抑制电路
公开(公告)号：US5786709A
公开(公告)日：1998-07-28
申请号：US738214
申请日：1996-10-25
申请人： Howard C. Kirsch , Yen-Tai Lin , Chiun-chi Shen , Jiang-Hong Ho , Jack-Lian Kuo
发明人： Howard C. Kirsch , Yen-Tai Lin , Chiun-chi Shen , Jiang-Hong Ho , Jack-Lian Kuo
IPC分类号： H03K17/16 , H03K19/003 , H03K19/0948
CPC分类号： H03K17/165 , H03K17/167 , H03K19/00361
摘要： A circuit for the control of a power or ground distribution transient voltage or power bounce or ground bounce is described. The circuit has a driver transistor of a first conductivity type and a driver transistor of a second conductivity type connected so as to be able to transfer a voltage to a data output terminal from a I/O voltage distribution network or a I/O ground distribution network. As the output terminal changes from a logic 1 to a logic 0 the driver transistor of the first conductivity type will conduct and a ground distribution voltage transient will begin to appear. A suppression transistor of the first conductivity type that will begin to conduct to begin cessation of conduction of the driver transistor of the first conductivity type decreasing the slew rate of the driver transistor of the first conductivity type. As the output terminal changes from a logic 0 to a logic 1 the driver transistor of the second conductivity type will conduct and a power distribution voltage transient will begin to appear. A suppression transistor of the second conductivity type that will begin to conduct to begin cessation of conduction of the driver transistor of the second conductivity type decreasing the slew rate of the driver transistor of the second conductivity type. The transistors may be PMOS, NMOS, NPN bipolar, or PNP bipolar integrated upon a silicon or compound semiconductor substrate.
摘要翻译：描述了用于控制电源或地面分配瞬态电压或电源反弹或地面反弹的电路。电路具有第一导电类型的驱动晶体管和第二导电类型的驱动晶体管，其连接成能够将电压从I / O电压分配网络或I / O地面分布传递到数据输出端子网络。当输出端从逻辑1变为逻辑0时，第一导电类型的驱动晶体管将导通，并且开始接地配电电压瞬变。第一导电类型的抑制晶体管将开始导通以开始停止第一导电类型的驱动晶体管的导通，从而降低第一导电类型的驱动晶体管的转换速率。当输出端子从逻辑0变为逻辑1时，第二导电类型的驱动晶体管将导通，并且将开始出现配电电压瞬变。第二导电类型的抑制晶体管将开始导通以开始停止第二导电类型的驱动晶体管的导通，从而降低第二导电类型的驱动晶体管的转换速率。晶体管可以是集成在硅或化合物半导体衬底上的PMOS，NMOS，NPN双极或PNP双极。

23. 发明申请

US20120268188A1 VOLATGE LEVEL SHIFTING APPARATUS 有权
公开(公告)号：US20120268188A1
公开(公告)日：2012-10-25
申请号：US13090283
申请日：2011-04-20
申请人： Chen-Hao Po , Yen-Tai Lin , Way-Chen Wu , Ching-Shan Chien
发明人： Chen-Hao Po , Yen-Tai Lin , Way-Chen Wu , Ching-Shan Chien
IPC分类号： H03L5/00
CPC分类号： H03K3/356182
摘要： A voltage level shifting apparatus is disclosed. The voltage level shifting apparatus has a cross-coupled transistor pair, a plurality of transistor pairs, a first diode string, a second diode string and an input transistor pair. One of the transistor pairs is coupled to the cross-coupled transistor pair, and the transistor pairs are controlled by a plurality of reference voltages. The first and the second diode strings are coupled between two of the transistor pairs. Each of the first and the second diode strings has at least one diode. The input transistor pair receives a first and a second input voltage, and the first and second input voltages are complementary signals. The cross-coupled transistor pair generates and outputs a first output voltage and a second output voltage by shifting the voltage level of the first and the second input voltage.
摘要翻译：公开了一种电压电平转换装置。电压电平移位装置具有交叉耦合晶体管对，多个晶体管对，第一二极管串，第二二极管串和输入晶体管对。晶体管对中的一个耦合到交叉耦合晶体管对，并且晶体管对由多个参考电压控制。第一和第二二极管串耦合在两个晶体管对之间。第一和第二二极管串中的每一个具有至少一个二极管。输入晶体管对接收第一和第二输入电压，第一和第二输入电压是互补信号。交叉耦合晶体管对通过移位第一和第二输入电压的电压电平来产生并输出第一输出电压和第二输出电压。

24. 发明授权

US07558119B2 Operating method of P-channel non-volatile memory 失效
标题翻译： P通道非易失性存储器的操作方法
公开(公告)号：US07558119B2
公开(公告)日：2009-07-07
申请号：US12046477
申请日：2008-03-12
申请人： Yen-Tai Lin
发明人： Yen-Tai Lin
IPC分类号： G11C16/06
CPC分类号： H01L27/115
摘要： A P-channel non-volatile memory is described. The P-channel non-volatile memory includes a substrate, a first memory cell, and second memory cell. An N-well is disposed over the substrate, and the first cell and the second cell are disposed over the N-well. The first memory cell includes a first gate, a first charge storage structure, a first doped region and a second doped region. The first doped region and the second doped region are disposed in the substrate on the respective sides of the first gate. The second cell includes a second gate, a second charge storage structure, a third doped region, and the second doped region. The third doped region and the second doped region are disposed in the substrate on the respective sides of the second gate. The second cell and the first cell share the second doped region.
摘要翻译：描述P沟道非易失性存储器。 P沟道非易失性存储器包括衬底，第一存储单元和第二存储单元。在衬底上设置N阱，并且将第一电池和第二电池设置在N阱上。第一存储单元包括第一栅极，第一电荷存储结构，第一掺杂区和第二掺杂区。第一掺杂区域和第二掺杂区域设置在第一栅极的相应侧面上的衬底中。第二单元包括第二栅极，第二电荷存储结构，第三掺杂区和第二掺杂区。第三掺杂区域和第二掺杂区域设置在第二栅极的相应侧上的衬底中。第二单元和第一单元共享第二掺杂区。

25. 发明授权

US07427889B2 Voltage regulator outputting positive and negative voltages with the same offsets 有权
标题翻译：电压调节器输出具有相同偏移量的正负电压
公开(公告)号：US07427889B2
公开(公告)日：2008-09-23
申请号：US11380661
申请日：2006-04-28
申请人： Yen-Tai Lin , Ching-Yuan Lin
发明人： Yen-Tai Lin , Ching-Yuan Lin
IPC分类号： G05F1/10
CPC分类号： H02M3/07 , G11C5/145 , H02M2001/009 , H02M2003/071
摘要： A voltage regulator has a first charge circuit, a second charge circuit, and a control circuit. The control circuit has five input terminals and two output terminals. The five input terminals are respectively coupled to a reference voltage, a first voltage source, a second voltage source, an output terminal of the first charge circuit, and an output terminal of the second charge circuit. The control circuit equalizes a voltage difference between the output terminal of the first charge circuit and the first voltage source and a voltage difference between the second voltage source and the output terminal of the second charge circuit.
摘要翻译：电压调节器具有第一充电电路，第二充电电路和控制电路。控制电路有五个输入端和两个输出端。五个输入端子分别耦合到参考电压，第一电压源，第二电压源，第一充电电路的输出端子和第二充电电路的输出端子。控制电路使第一充电电路的输出端和第一电压源之间的电压差与第二电压源与第二充电电路的输出端之间的电压差相等。

26. 发明申请

US20080218252A1 VOLTAGE REGULATOR OUTPUTTING POSITIVE AND NEGATIVE VOLTAGES WITH THE SAME OFFSETS 有权
标题翻译：电压调节器输出具有相同偏置的正负电压
公开(公告)号：US20080218252A1
公开(公告)日：2008-09-11
申请号：US12116229
申请日：2008-05-07
申请人： Yen-Tai Lin , Ching-Yuan Lin
发明人： Yen-Tai Lin , Ching-Yuan Lin
IPC分类号： G05F1/10
CPC分类号： H02M3/07 , G11C5/145 , H02M2001/009 , H02M2003/071
摘要： A voltage regulator has a first charge circuit, a second charge circuit, and a control circuit. The control circuit has five input terminals and two output terminals. The five input terminals are respectively coupled to a reference voltage, a first voltage source, a second voltage source, an output terminal of the first charge circuit, and an output terminal of the second charge circuit. The control circuit equalizes a voltage difference between the output terminal of the first charge circuit and the first voltage source and a voltage difference between the second voltage source and the output terminal of the second charge circuit.
摘要翻译：电压调节器具有第一充电电路，第二充电电路和控制电路。控制电路有五个输入端和两个输出端。五个输入端子分别耦合到参考电压，第一电压源，第二电压源，第一充电电路的输出端子和第二充电电路的输出端子。控制电路使第一充电电路的输出端和第一电压源之间的电压差与第二电压源与第二充电电路的输出端之间的电压差相等。

27. 发明申请

US20080056013A1 Method and Related Apparatus Capable of Improving Endurance of Memory 审中-公开
标题翻译：能够提高记忆力的方法和相关装置
公开(公告)号：US20080056013A1
公开(公告)日：2008-03-06
申请号：US11936095
申请日：2007-11-07
申请人： Ching-Yuan Lin , Yen-Tai Lin
发明人： Ching-Yuan Lin , Yen-Tai Lin
IPC分类号： G11C16/04
CPC分类号： G11C16/349 , G11C16/102 , G11C16/3495
摘要： A method capable of improving endurance of memory includes detecting whether a record cell is the last non-programmed record cell of a set of record cells that includes the record cell. The method includes erasing the corresponding set of multi-time programmable memory blocks and erasing the set of record cells, if the record cell is the last non-programmed record cell of the set of record cells that includes the record cell. The method further includes programming the record cell corresponding to a first non-programmed record cell in the set of record cells if the non-programmed record cell is not the last non-programmed record cell of the set of record cells.
摘要翻译：能够提高存储器耐久性的方法包括检测记录单元是否是包括记录单元的一组记录单元的最后一个非编程记录单元。如果记录单元是包括记录单元的记录单元组的最后一个未编程的记录单元，则该方法包括擦除相应的多次可编程存储器块组并擦除记录单元组。该方法还包括如果非编程记录单元不是该组记录单元的最后一个非编程记录单元，则编程对应于记录单元组中的第一非编程记录单元的记录单元。

28. 发明授权

US06775189B2 Option fuse circuit using standard CMOS manufacturing process 有权
标题翻译：选件保险丝电路采用标准CMOS制造工艺
公开(公告)号：US06775189B2
公开(公告)日：2004-08-10
申请号：US10248194
申请日：2002-12-25
申请人： Yen-Tai Lin , Jie-Hau Huang
发明人： Yen-Tai Lin , Jie-Hau Huang
IPC分类号： G11C700
CPC分类号： G11C17/16
摘要： An option fuse circuit using standard CMOS manufacturing processes includes a latch for latching signals, which includes a first node and a second node. The option fuse circuit also includes a comparator, which includes two input nodes and an output node. The comparator receives signals input at the two input nodes from the first and the second nodes, and compares the two signals in order to output a comparison signal. The option fuse circuit further includes two logic cells for storing non-volatile data. The logic cells include a word line node and a bit line node. The word line nodes are electrically connected to the output node of the comparator, while the bit line nodes are electrically connected to the first and the second nodes, respectively.
摘要翻译：使用标准CMOS制造工艺的选项熔丝电路包括用于锁存信号的锁存器，其包括第一节点和第二节点。选项保险丝电路还包括一个比较器，它包括两个输入节点和一个输出节点。比较器从第一和第二节点接收在两个输入节点处输入的信号，并比较两个信号以输出比较信号。选项保险丝电路还包括用于存储非易失性数据的两个逻辑单元。逻辑单元包括字线节点和位线节点。字线节点电连接到比较器的输出节点，而位线节点分别电连接到第一和第二节点。

29. 发明授权

US06580658B1 Method using a word line driver for driving a word line 失效
标题翻译：使用字线驱动程序来驱动字线的方法
公开(公告)号：US06580658B1
公开(公告)日：2003-06-17
申请号：US10065661
申请日：2002-11-07
申请人： Yu-Ming Hsu , Yen-Tai Lin , Chien-Hung Ho
发明人： Yu-Ming Hsu , Yen-Tai Lin , Chien-Hung Ho
IPC分类号： G11C800
CPC分类号： G11C8/08 , G11C16/08
摘要： A word line driver includes an address decoder having a first circuit and a second circuit for selecting the word line, and a control end disposed between the first circuit and the second circuit. In addition, the word line driver has a level shift circuit for shifting a voltage level of the word line, and the level shift circuit has an input end connected to the second circuit of the address decoder. A method of driving a word line includes shifting a voltage level of the control end while turning on the second circuit so as to shift a voltage level of the input end of the level shift circuit, and shifting a voltage level of at least one of the first and second power supplies and using the second circuit to isolate the voltage level of the control end from the voltage level of the word line.
摘要翻译：字线驱动器包括具有第一电路的地址解码器和用于选择字线的第二电路，以及设置在第一电路和第二电路之间的控制端。此外，字线驱动器具有用于移位字线的电压电平的电平移位电路，并且电平移位电路具有连接到地址解码器的第二电路的输入端。一种驱动字线的方法包括：在接通第二电路的同时移动控制端的电压电平，以便移位电平移位电路的输入端的电压电平，并移位至少一个第一和第二电源，并使用第二电路将控制端的电压电平与字线的电压电平隔离开。

30. 发明授权

US06580645B1 Page buffer of a flash memory 失效
标题翻译： Flash存储器的页面缓冲区
公开(公告)号：US06580645B1
公开(公告)日：2003-06-17
申请号：US10065660
申请日：2002-11-07
申请人： Yen-Tai Lin , Chien-Hung Ho
发明人： Yen-Tai Lin , Chien-Hung Ho
IPC分类号： G11C1600
CPC分类号： G11C16/10 , G11C2216/14
摘要： A page buffer for a flash memory has a power supply, a latch circuit, and a plurality of switches. Initially the switches are controlled for resetting a first terminal and a second terminal of the latch circuit to a respective predetermined voltage. If a memory cell is not to be programmed, the voltage levels of the first terminal and the second terminal remain unchanged when the power supply outputs a programming voltage. If the memory cell is to be programmed, the voltage levels of the first terminal and the second terminal are changed when the power supply outputs the programming voltage. Each of the first terminal and the second terminal will regain the predetermined voltage after the memory cell is completely programmed to store a predetermined binary digit.
摘要翻译：闪存的页缓冲器具有电源，锁存电路和多个开关。最初，开关被控制用于将锁存电路的第一端子和第二端子复位到相应的预定电压。如果不编程存储单元，则当电源输出编程电压时，第一端子和第二端子的电压电平保持不变。如果要对存储器单元进行编程，则当电源输出编程电压时，第一端子和第二端子的电压电平发生变化。在存储器单元被完全编程以存储预定二进制数位之后，第一端子和第二端子中的每一个将重新获得预定电压。

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