专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5786709A Integrated circuit output driver incorporating power distribution noise suppression circuitry 失效
标题翻译：集成电路输出驱动器，并入功率分配噪声抑制电路
公开(公告)号：US5786709A
公开(公告)日：1998-07-28
申请号：US738214
申请日：1996-10-25
申请人： Howard C. Kirsch , Yen-Tai Lin , Chiun-chi Shen , Jiang-Hong Ho , Jack-Lian Kuo
发明人： Howard C. Kirsch , Yen-Tai Lin , Chiun-chi Shen , Jiang-Hong Ho , Jack-Lian Kuo
IPC分类号： H03K17/16 , H03K19/003 , H03K19/0948
CPC分类号： H03K17/165 , H03K17/167 , H03K19/00361
摘要： A circuit for the control of a power or ground distribution transient voltage or power bounce or ground bounce is described. The circuit has a driver transistor of a first conductivity type and a driver transistor of a second conductivity type connected so as to be able to transfer a voltage to a data output terminal from a I/O voltage distribution network or a I/O ground distribution network. As the output terminal changes from a logic 1 to a logic 0 the driver transistor of the first conductivity type will conduct and a ground distribution voltage transient will begin to appear. A suppression transistor of the first conductivity type that will begin to conduct to begin cessation of conduction of the driver transistor of the first conductivity type decreasing the slew rate of the driver transistor of the first conductivity type. As the output terminal changes from a logic 0 to a logic 1 the driver transistor of the second conductivity type will conduct and a power distribution voltage transient will begin to appear. A suppression transistor of the second conductivity type that will begin to conduct to begin cessation of conduction of the driver transistor of the second conductivity type decreasing the slew rate of the driver transistor of the second conductivity type. The transistors may be PMOS, NMOS, NPN bipolar, or PNP bipolar integrated upon a silicon or compound semiconductor substrate.
摘要翻译：描述了用于控制电源或地面分配瞬态电压或电源反弹或地面反弹的电路。电路具有第一导电类型的驱动晶体管和第二导电类型的驱动晶体管，其连接成能够将电压从I / O电压分配网络或I / O地面分布传递到数据输出端子网络。当输出端从逻辑1变为逻辑0时，第一导电类型的驱动晶体管将导通，并且开始接地配电电压瞬变。第一导电类型的抑制晶体管将开始导通以开始停止第一导电类型的驱动晶体管的导通，从而降低第一导电类型的驱动晶体管的转换速率。当输出端子从逻辑0变为逻辑1时，第二导电类型的驱动晶体管将导通，并且将开始出现配电电压瞬变。第二导电类型的抑制晶体管将开始导通以开始停止第二导电类型的驱动晶体管的导通，从而降低第二导电类型的驱动晶体管的转换速率。晶体管可以是集成在硅或化合物半导体衬底上的PMOS，NMOS，NPN双极或PNP双极。

2. 发明授权

US6091264A Schmitt trigger input stage 失效
标题翻译：施密特触发输入级
公开(公告)号：US6091264A
公开(公告)日：2000-07-18
申请号：US85613
申请日：1998-05-27
申请人： Howard C. Kirsch , Yen-Tai Lin , Yu-Ming Hsu
发明人： Howard C. Kirsch , Yen-Tai Lin , Yu-Ming Hsu
IPC分类号： H03K19/00 , H03K19/0175 , H03K19/094
CPC分类号： H03K19/0013
摘要： A circuit and a method are disclosed for a Schmitt trigger stage which converts transistor-transistor logic (TTL) into metal oxide semiconductor (MOS) logic signal levels using all MOS devices. The circuit reduces the standby current of the n-channel transistor of the input section of the Schmitt trigger stage by adding a MOS diode to the bottom the input section. When higher than normal supply voltages are used, the standby current of the p-channel transistor of the input section can be reduced by adding a MOS diode to the top of the input section. In addition, a small MOS transistor, connected across the output Schmitt trigger inverter, eliminates leakage currents in that inverter.
摘要翻译：公开了用于施密特触发级的电路和方法，其使用所有MOS器件将晶体管晶体管逻辑（TTL）转换为金属氧化物半导体（MOS）逻辑信号电平。该电路通过向输入部分的底部添加MOS二极管来降低施密特触发级的输入部分的n沟道晶体管的待机电流。当使用高于正常电源电压时，可以通过向输入部分的顶部添加MOS二极管来减小输入部分的p沟道晶体管的待机电流。另外，一个连接在输出施密特触发器上的小型MOS晶体管消除了该逆变器的漏电流。

3. 发明授权

US5896344A Local word line decoder for memory with 2 1/2 MOS devices 失效
标题翻译：具有2 1/2 MOS器件的存储器的本地字线解码器
公开(公告)号：US5896344A
公开(公告)日：1999-04-20
申请号：US944771
申请日：1997-10-06
申请人： Howard C. Kirsch , Yen-Tai Lin
发明人： Howard C. Kirsch , Yen-Tai Lin
IPC分类号： G11C8/10 , G11C8/00 , G11C7/00
CPC分类号： G11C8/10
摘要： A method, a circuit, and a structure are disclosed by which the semiconductor area is reduced that a local word line decoder for a memory array requires. This reduction in area size has been achieved by eliminating one transistor of a three transistor local wordline decoder and introducing a fifth transistor which is shared by two local wordline decoders. The area occupied by the two eliminated transistors is no longer needed because the fifth transistor can be fitted between two existing transistors without an increase in area.
摘要翻译：公开了一种减少半导体区域的方法，电路和结构，即存储阵列的局部字线解码器需要。通过消除三晶体管本地字线解码器的一个晶体管并引入由两个本地字线解码器共享的第五晶体管，实现了面积尺寸的减小。不再需要由两个消除的晶体管占据的面积，因为第五晶体管可以安装在两个现有的晶体管之间，而不增加面积。

4. 发明授权

US5867445A Local word line decoder for memory with 2 MOS devices 失效
标题翻译：具有2个MOS器件的存储器的本地字线解码器
公开(公告)号：US5867445A
公开(公告)日：1999-02-02
申请号：US944571
申请日：1997-10-06
申请人： Howard C. Kirsch , Yen-Tai Lin
发明人： Howard C. Kirsch , Yen-Tai Lin
IPC分类号： G11C8/08 , G11C8/00 , G11C16/04
CPC分类号： G11C8/08
摘要： A method and a circuit are disclosed by which the semiconductor area is reduced that a local word line decoder for a memory array requires. This reduction in area size has been achieved by eliminating one transistor of a three transistor local wordline decoder and by reducing the number of inputs to the decoder from three to two. The reduction in inputs is made possible by the method of applying to one of the inputs, when low, a voltage signal v.sub.b which is at least one threshold lower than the voltage signal to the other input, when low. This voltage v.sub.b can be derived from the p-substrate bias voltage.
摘要翻译：公开了一种减少半导体区域的方法和电路，即存储阵列的局部字线解码器需要。通过消除三晶体管本地字线解码器的一个晶体管并且将解码器的输入数量从三个减少到两个，已经实现了面积尺寸的减小。当低时，通过施加到其中一个输入的方式，当低电平时，施加至少一个阈值的电压信号vb为低于另一输入端的电压信号的方法可以实现输入的减小。该电压vb可以从p衬底偏置电压导出。

5. 发明申请

US20120126885A1 DOUBLE GATED 4F2 DRAM CHC CELL AND METHODS OF FABRICATING THE SAME 有权
标题翻译：双环4F2 DRAM CHC电池及其制造方法
公开(公告)号：US20120126885A1
公开(公告)日：2012-05-24
申请号：US12950797
申请日：2010-11-19
申请人： Werner Juengling , Howard C. Kirsch
发明人： Werner Juengling , Howard C. Kirsch
IPC分类号： H01L29/78 , H03K17/00 , H01L21/28
CPC分类号： H01L21/823481 , H01L21/76224 , H01L21/823431 , H01L21/823437 , H01L27/0886 , H01L27/10823 , H01L27/10826 , H01L27/10876 , H01L27/10879 , H01L27/10891 , H01L29/0847 , H01L29/1037 , H01L29/4236 , H01L29/66484 , H01L29/66787 , H01L29/7855
摘要： A semiconductor device is provided that includes a fin having a first gate and a second gate formed on a first sidewall of the fin in a first trench, wherein the first gate is formed above the second gate. The device includes a third gate and a fourth gate formed on a second sidewall of the fin in a second trench, wherein the third gate is formed above the fourth gate. Methods of manufacturing and operating the device are also included. A method of operation may include biasing the first gate and the fourth gate to create a current path across the fin.
摘要翻译：提供一种半导体器件，其包括在第一沟槽中形成有鳍状物的第一侧壁上的第一栅极和第二栅极的鳍片，其中第一栅极形成在第二栅极之上。该器件包括在第二沟槽中形成在鳍片的第二侧壁上的第三栅极和第四栅极，其中第三栅极形成在第四栅极之上。还包括制造和操作设备的方法。一种操作方法可以包括偏置第一栅极和第四栅极以产生穿过散热片的电流路径。

6. 发明申请

US20090237996A1 MEMORY STRUCTURE HAVING VOLATILE AND NON-VOLATILE MEMORY PORTIONS 有权
标题翻译：具有挥发性和非易失性记忆体的记忆结构
公开(公告)号：US20090237996A1
公开(公告)日：2009-09-24
申请号：US12052300
申请日：2008-03-20
申请人： Howard C. Kirsch , Charles Ingalls , Werner Juengling
发明人： Howard C. Kirsch , Charles Ingalls , Werner Juengling
IPC分类号： G11C11/34 , H01L29/78
CPC分类号： G11C14/0018 , G11C16/0466 , H01L27/105 , H01L27/1052 , H01L27/10826 , H01L27/10876 , H01L27/10894 , H01L27/11568 , H01L29/66833 , H01L29/785 , H01L29/792
摘要： A memory array is provided that includes a transistor having two active gates sharing a source, a drain, and a channel of the transistor. One of the active gates may be coupled to a volatile memory portion of a memory cell, such as a DRAM cell, and the other active gate may be coupled to a non-volatile memory portion, for example, a charge storage node such as a SONOS cell. Methods of operating the memory array are provided that include transferring data from the volatile memory portions to the non-volatile memory portions, transferring data from the non-volatile memory portions to the volatile memory portions, and erasing the non-volatile memory portions of a row of memory cells.
摘要翻译：提供一种存储器阵列，其包括具有共享晶体管的源极，漏极和沟道的两个有源栅极的晶体管。有源栅极中的一个可以耦合到诸如DRAM单元的存储器单元的易失性存储器部分，并且另一有源栅极可以耦合到非易失性存储器部分，例如电荷存储节点，例如 SONOS细胞。提供了操作存储器阵列的方法，其包括将数据从易失性存储器部分传送到非易失性存储器部分，将数据从非易失性存储器部分传送到易失性存储器部分，以及擦除非易失性存储器部分行的存储单元。

7. 发明申请

US20090129188A1 Devices and methods for a threshold voltage difference compensated sense amplifier 有权
标题翻译：阈值电压差补偿读出放大器的器件和方法
公开(公告)号：US20090129188A1
公开(公告)日：2009-05-21
申请号：US11986333
申请日：2007-11-20
申请人： Tae Kim , Howard C. Kirsch
发明人： Tae Kim , Howard C. Kirsch
IPC分类号： G11C7/08
CPC分类号： G11C7/08 , G11C7/062
摘要： Embodiments are described for a voltage compensated sense amplifier. One such sense amplifier includes a pair of digit line nodes respectively coupled to a pair of transistors. A first pair of switches are adapted to cross-couple the gates of the transistors to the respective digit line node and a second pair of switches are adapted to couple the gates of the transistors to a voltage supply. The first and second pair of switches are coupled to respective gates of the transistors independent of the pair of transistors being respectively coupled to the digit line nodes.
摘要翻译：针对电压补偿的读出放大器描述实施例。一个这样的感测放大器包括分别耦合到一对晶体管的一对数字线节点。第一对开关适于将晶体管的栅极交叉耦合到相应的数字线节点，并且第二对开关适于将晶体管的栅极耦合到电压源。第一和第二对开关耦合到晶体管的相应栅极，独立于一对晶体管分别耦合到数字线节点。

8. 发明申请

US20080176378A1 MULTIPLE-DEPTH STI TRENCHES IN INTEGRATED CIRCUIT FABRICATION 有权
标题翻译：集成电路制造中的多层深度STI
公开(公告)号：US20080176378A1
公开(公告)日：2008-07-24
申请号：US12057643
申请日：2008-03-28
申请人： Shubneesh Batra , Howard C. Kirsch , Gurtej S. Sandhu , Xianfeng Zhou , Chih-Chen Cho
发明人： Shubneesh Batra , Howard C. Kirsch , Gurtej S. Sandhu , Xianfeng Zhou , Chih-Chen Cho
IPC分类号： H01L21/76
CPC分类号： H01L21/76229
摘要： Multiple trench depths within an integrated circuit device are formed by first forming trenches in a substrate to a first depth, but of varying widths. Formation of a dielectric layer can cause some of the trenches to fill or close off while leaving other, wider trenches open. Removal of a portion of the dielectric material can then be tailored to expose a bottom of the open trenches while leaving remaining trenches filled. Removal of exposed portions of the underlying substrate can then be used to selectively deepen the open trenches, which can subsequently be filled. Such methods can be used to form trenches of varying depths without the need for subsequent masking.
摘要翻译：集成电路器件内的多个沟槽深度通过首先将衬底中的沟槽形成第一深度但具有变化的宽度来形成。电介质层的形成可以使一些沟槽填充或封闭，同时留下其他更宽的沟槽打开。然后可以去除电介质材料的一部分以暴露开口沟槽的底部，同时留下剩余的沟槽填充。然后可以去除下面的衬底的暴露部分以选择性地加深可以随后填充的开放沟槽。这种方法可用于形成不同深度的沟槽，而不需要随后的掩蔽。

9. 发明授权

US07365384B2 Trench buried bit line memory devices and methods thereof 有权
标题翻译：沟槽掩埋位线存储器件及其方法
公开(公告)号：US07365384B2
公开(公告)日：2008-04-29
申请号：US11588748
申请日：2006-10-27
申请人： Luan C. Tran , Mark Durcan , Howard C. Kirsch
发明人： Luan C. Tran , Mark Durcan , Howard C. Kirsch
IPC分类号： H01L27/108
CPC分类号： H01L27/10885 , H01L27/10814 , H01L27/10888
摘要： A memory device includes isolation trenches that are formed generally parallel to and along associated strips of active area. A conductive bit line is recessed within each isolation trench such that the uppermost surface of the bit line is recessed below the uppermost surface of the base substrate. A bit line contact strap electrically couples the bit line to the active area both along a vertical dimension of the bit line strap and along a horizontal dimension across the uppermost surface of the base substrate.
摘要翻译：存储器件包括大致平行于并沿着有源区域的相关带形成的隔离沟槽。导电位线凹陷在每个隔离沟槽内，使得位线的最上表面凹陷在基底基板的最上表面之下。位线接触带沿着位线带的垂直尺寸并且跨越基底的最上表面的水平尺寸将位线电耦合到有源区域。

10. 发明授权

US07254074B2 Open digit line array architecture for a memory array 有权
公开(公告)号：US07254074B2
公开(公告)日：2007-08-07
申请号：US11074518
申请日：2005-03-07
申请人： Sei Seung Yoon , Charles L. Ingalls , David Pinney , Howard C. Kirsch
发明人： Sei Seung Yoon , Charles L. Ingalls , David Pinney , Howard C. Kirsch
IPC分类号： G11C7/00
CPC分类号： G11C7/18 , G11C7/04 , G11C7/065 , G11C7/12 , G11C7/14 , G11C11/4091 , G11C11/4094 , G11C11/4097
摘要： A system and method for sensing a data state stored by a memory cell that includes coupling a first digit line and a second digit line to a precharge voltage and further coupling a memory cell to the first digit line. At least one digit line other than the first and second digit lines is driven to a reference voltage level and the at least one digit line is coupled to the second digit line to establish a reference voltage in the second digit line. A voltage differential is sensed between the first digit line and the second digit line, and a data state based on the voltage differential is latched in response.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式