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1. 发明授权

US5920221A RC delay circuit for integrated circuits 失效
标题翻译： RC延迟电路用于集成电路
公开(公告)号：US5920221A
公开(公告)日：1999-07-06
申请号：US892216
申请日：1997-07-14
申请人： Chiun-Chi Shen , Yen-Tai Lin , Jiang-Hong Ho , Jack-Lian Kuo , Howard Clayton Kirsch
发明人： Chiun-Chi Shen , Yen-Tai Lin , Jiang-Hong Ho , Jack-Lian Kuo , Howard Clayton Kirsch
IPC分类号： H03K5/13
CPC分类号： H03K5/133
摘要： This invention describes a delay circuit for integrated circuits that has the capability to delay the rising and falling transitions separately and independent of each other. A signal is fed through an RC network to a Schmitt trigger and then through an inverter to the output of the delay circuit. Two MOS transistors are connected as capacitors and in parallel but in opposing directions between the delay circuit output and the input to the Schmitt trigger to form part of the RC network. The biasing of the two transistors is such that the inversion layer capacitance is active in only one transistor for each signal transition. Thus the falling and rising transition of an input signal can be delayed separately. Changing the gate and channel size in one transistor acting as a capacitor changes the delay in one signal transition. Changing the other gate and channel size changes the delay in the other transition. The output of the delay circuit is fed back through the transistor capacitors to hasten the switching of the Schmitt trigger.
摘要翻译：本发明描述了一种用于集成电路的延迟电路，其具有分别且彼此独立地延迟上升和下降转换的能力。信号通过RC网络馈送到施密特触发器，然后通过反相器馈送到延迟电路的输出。两个MOS晶体管作为电容器并联连接，但是在延迟电路输出和施密特触发器的输入之间是相反的方向，以形成RC网络的一部分。两个晶体管的偏压使得反向层电容仅在每个信号转变的一个晶体管中有效。因此，输入信号的下降和上升转换可以分开延迟。用作电容器的一个晶体管中的栅极和沟道尺寸改变了一个信号转变中的延迟。改变另一个门和通道大小会改变另一个转换的延迟。延迟电路的输出通过晶体管电容反馈，以加速施密特触发器的切换。

2. 发明授权

US5867433A Semiconductor memory with a novel column decoder for selecting a redundant array 失效
标题翻译：具有用于选择冗余阵列的新型列解码器的半导体存储器
公开(公告)号：US5867433A
公开(公告)日：1999-02-02
申请号：US893642
申请日：1997-07-11
申请人： Chiun-Chi Shen , Yen-Tai Lin , Jiang-Hong Ho , Jack-Lian Kuo , Howard Clayton Kirsch
发明人： Chiun-Chi Shen , Yen-Tai Lin , Jiang-Hong Ho , Jack-Lian Kuo , Howard Clayton Kirsch
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/785 , G11C29/832
摘要： Circuits and a method are described that integrate memory arrays, a redundant memory array, their associated decoders, sense amplifiers, and outputs into one module. This integration is achieved through the use of a column decoder with a fuse, which, when blown, permanently deselects the failing array and selects the redundant array. By OR'ing the redundant column select line of each column decoder, any column decoder can select the redundant array. Higher level array structures are produced by replication of the lower level array structure. The system output is generated by OR'ing together the respective data outputs of each array.
摘要翻译：描述了将存储器阵列，冗余存储器阵列，其相关解码器，读出放大器和输出集成到一个模块中的电路和方法。通过使用具有保险丝的列解码器来实现这种集成，当熔断器被熔断时，永久地取消选择故障阵列并选择冗余阵列。通过对每列解码器的冗余列选择行进行OR运算，任何列解码器都可以选择冗余阵列。较高级别的阵列结构是通过复制下层阵列结构产生的。系统输出是通过将每个阵列的各个数据输出进行OR组合来产生的。

3. 发明授权

US5786709A Integrated circuit output driver incorporating power distribution noise suppression circuitry 失效
标题翻译：集成电路输出驱动器，并入功率分配噪声抑制电路
公开(公告)号：US5786709A
公开(公告)日：1998-07-28
申请号：US738214
申请日：1996-10-25
申请人： Howard C. Kirsch , Yen-Tai Lin , Chiun-chi Shen , Jiang-Hong Ho , Jack-Lian Kuo
发明人： Howard C. Kirsch , Yen-Tai Lin , Chiun-chi Shen , Jiang-Hong Ho , Jack-Lian Kuo
IPC分类号： H03K17/16 , H03K19/003 , H03K19/0948
CPC分类号： H03K17/165 , H03K17/167 , H03K19/00361
摘要： A circuit for the control of a power or ground distribution transient voltage or power bounce or ground bounce is described. The circuit has a driver transistor of a first conductivity type and a driver transistor of a second conductivity type connected so as to be able to transfer a voltage to a data output terminal from a I/O voltage distribution network or a I/O ground distribution network. As the output terminal changes from a logic 1 to a logic 0 the driver transistor of the first conductivity type will conduct and a ground distribution voltage transient will begin to appear. A suppression transistor of the first conductivity type that will begin to conduct to begin cessation of conduction of the driver transistor of the first conductivity type decreasing the slew rate of the driver transistor of the first conductivity type. As the output terminal changes from a logic 0 to a logic 1 the driver transistor of the second conductivity type will conduct and a power distribution voltage transient will begin to appear. A suppression transistor of the second conductivity type that will begin to conduct to begin cessation of conduction of the driver transistor of the second conductivity type decreasing the slew rate of the driver transistor of the second conductivity type. The transistors may be PMOS, NMOS, NPN bipolar, or PNP bipolar integrated upon a silicon or compound semiconductor substrate.
摘要翻译：描述了用于控制电源或地面分配瞬态电压或电源反弹或地面反弹的电路。电路具有第一导电类型的驱动晶体管和第二导电类型的驱动晶体管，其连接成能够将电压从I / O电压分配网络或I / O地面分布传递到数据输出端子网络。当输出端从逻辑1变为逻辑0时，第一导电类型的驱动晶体管将导通，并且开始接地配电电压瞬变。第一导电类型的抑制晶体管将开始导通以开始停止第一导电类型的驱动晶体管的导通，从而降低第一导电类型的驱动晶体管的转换速率。当输出端子从逻辑0变为逻辑1时，第二导电类型的驱动晶体管将导通，并且将开始出现配电电压瞬变。第二导电类型的抑制晶体管将开始导通以开始停止第二导电类型的驱动晶体管的导通，从而降低第二导电类型的驱动晶体管的转换速率。晶体管可以是集成在硅或化合物半导体衬底上的PMOS，NMOS，NPN双极或PNP双极。

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