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1. 发明授权

US5920221A RC delay circuit for integrated circuits 失效
标题翻译： RC延迟电路用于集成电路
公开(公告)号：US5920221A
公开(公告)日：1999-07-06
申请号：US892216
申请日：1997-07-14
申请人： Chiun-Chi Shen , Yen-Tai Lin , Jiang-Hong Ho , Jack-Lian Kuo , Howard Clayton Kirsch
发明人： Chiun-Chi Shen , Yen-Tai Lin , Jiang-Hong Ho , Jack-Lian Kuo , Howard Clayton Kirsch
IPC分类号： H03K5/13
CPC分类号： H03K5/133
摘要： This invention describes a delay circuit for integrated circuits that has the capability to delay the rising and falling transitions separately and independent of each other. A signal is fed through an RC network to a Schmitt trigger and then through an inverter to the output of the delay circuit. Two MOS transistors are connected as capacitors and in parallel but in opposing directions between the delay circuit output and the input to the Schmitt trigger to form part of the RC network. The biasing of the two transistors is such that the inversion layer capacitance is active in only one transistor for each signal transition. Thus the falling and rising transition of an input signal can be delayed separately. Changing the gate and channel size in one transistor acting as a capacitor changes the delay in one signal transition. Changing the other gate and channel size changes the delay in the other transition. The output of the delay circuit is fed back through the transistor capacitors to hasten the switching of the Schmitt trigger.
摘要翻译：本发明描述了一种用于集成电路的延迟电路，其具有分别且彼此独立地延迟上升和下降转换的能力。信号通过RC网络馈送到施密特触发器，然后通过反相器馈送到延迟电路的输出。两个MOS晶体管作为电容器并联连接，但是在延迟电路输出和施密特触发器的输入之间是相反的方向，以形成RC网络的一部分。两个晶体管的偏压使得反向层电容仅在每个信号转变的一个晶体管中有效。因此，输入信号的下降和上升转换可以分开延迟。用作电容器的一个晶体管中的栅极和沟道尺寸改变了一个信号转变中的延迟。改变另一个门和通道大小会改变另一个转换的延迟。延迟电路的输出通过晶体管电容反馈，以加速施密特触发器的切换。

2. 发明授权

US5867433A Semiconductor memory with a novel column decoder for selecting a redundant array 失效
标题翻译：具有用于选择冗余阵列的新型列解码器的半导体存储器
公开(公告)号：US5867433A
公开(公告)日：1999-02-02
申请号：US893642
申请日：1997-07-11
申请人： Chiun-Chi Shen , Yen-Tai Lin , Jiang-Hong Ho , Jack-Lian Kuo , Howard Clayton Kirsch
发明人： Chiun-Chi Shen , Yen-Tai Lin , Jiang-Hong Ho , Jack-Lian Kuo , Howard Clayton Kirsch
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/785 , G11C29/832
摘要： Circuits and a method are described that integrate memory arrays, a redundant memory array, their associated decoders, sense amplifiers, and outputs into one module. This integration is achieved through the use of a column decoder with a fuse, which, when blown, permanently deselects the failing array and selects the redundant array. By OR'ing the redundant column select line of each column decoder, any column decoder can select the redundant array. Higher level array structures are produced by replication of the lower level array structure. The system output is generated by OR'ing together the respective data outputs of each array.
摘要翻译：描述了将存储器阵列，冗余存储器阵列，其相关解码器，读出放大器和输出集成到一个模块中的电路和方法。通过使用具有保险丝的列解码器来实现这种集成，当熔断器被熔断时，永久地取消选择故障阵列并选择冗余阵列。通过对每列解码器的冗余列选择行进行OR运算，任何列解码器都可以选择冗余阵列。较高级别的阵列结构是通过复制下层阵列结构产生的。系统输出是通过将每个阵列的各个数据输出进行OR组合来产生的。

3. 发明授权

US6166582A Method and apparatus of an output buffer for controlling the ground bounce of a semiconductor device 有权
标题翻译：用于控制半导体器件的接地反弹的输出缓冲器的方法和装置
公开(公告)号：US6166582A
公开(公告)日：2000-12-26
申请号：US189439
申请日：1998-11-10
申请人： Jiunn-Chin Tseng , Howard Clayton Kirsch
发明人： Jiunn-Chin Tseng , Howard Clayton Kirsch
IPC分类号： H03K19/003 , H03K5/12 , H03K17/16
CPC分类号： H03K19/00361
摘要： A method and apparatus of an output buffer for controlling the ground bounce and power supply noise during output switching is provided. A CMOS output buffer comprises a P-channel output transistor, a N-channel output transistor and a predrive circuit. During output pull-down transition, the predrive circuit generates a first gate voltage on the pull-down N-channel output transistor for a predetermined time, and further generates a second voltage value which is smaller than the first voltage value, then returns to the first voltage value after the elapse of the predetermined time. The predrive circuit makes the pull-down N-channel output transistor stay in the saturation region longer than the uncontrolled scheme, the steep rising gate voltage on the N-channel output transistor can be avoided with a very little speed degradation but instead of better ground bounce improvement. During output pull-up transition, the predrive circuit generates a first gate voltage on the pull-up P-channel output transistor for a predetermined time, and further generates a second voltage which is higher than the first voltage value, then returns back to the first voltage value after the elapse of the predetermined time.
摘要翻译：提供了一种用于在输出切换期间控制地面反弹和电源噪声的输出缓冲器的方法和装置。 CMOS输出缓冲器包括P沟道输出晶体管，N沟道输出晶体管和预驱动电路。在输出下拉转换期间，预驱动电路在下拉N沟道输出晶体管上产生预定时间的第一栅极电压，并进一步产生小于第一电压值的第二电压值，然后返回到经过预定时间后的第一电压值。预驱动电路使下拉通道N沟道输出晶体管保持在比不受控制的方案更长的饱和区域中，可以以非常小的速度降低来避免N沟道输出晶体管上的陡峭的上升栅极电压，而不是更好的接地反弹改善。在输出上拉转换期间，预驱动电路在上拉P沟道输出晶体管上产生预定时间的第一栅极电压，并进一步产生高于第一电压值的第二电压，然后返回到经过预定时间后的第一电压值。

4. 发明授权

US5792680A Method of forming a low cost DRAM cell with self aligned twin tub CMOS devices and a pillar shaped capacitor 失效
标题翻译：用自对准双槽CMOS器件和柱状电容器形成低成本DRAM单元的方法
公开(公告)号：US5792680A
公开(公告)日：1998-08-11
申请号：US756129
申请日：1996-11-25
申请人： Janmye Sung , Chih-Yuan Lu , Howard Clayton Kirsch
发明人： Janmye Sung , Chih-Yuan Lu , Howard Clayton Kirsch
IPC分类号： H01L21/8239 , H01L21/8242 , H01L27/108 , H01L21/8238
CPC分类号： H01L27/10852 , H01L27/1052 , H01L27/10817
摘要： The invention is a method of forming a reduced cost DRAM. The process has two embodiments for forming twin wells and two embodiments for forming pillar shaped capacitor electrodes. The twin well embodiments are simple low cost processes. The embodiments for forming the electrode pillars begin by forming a tungsten silicide conductive layer on a first planarization layer. For the first embodiment, the pillars are formed using a photolithography mask with a pattern of spaced transparent areas. The dimensions of the spaced transparent areas and distances between the spaced transparent areas are smaller that the resolution of the lithographic tool. Spaced oxide islands are formed with the mask and are used as an etch mask to form spaced pillars from the conductive layer. This first embodiment for fabricating the multiple pillar capacitor forms pillars of a smaller dimension than the resolution of the photolithography tool. The second embodiment for forming the pillars involves using small titanium silicide islands as an etch mask to define the pillars.
摘要翻译：本发明是一种形成降低成本的DRAM的方法。该方法具有用于形成双阱的两个实施例和用于形成柱状电容器电极的两个实施例。双阱实施例是简单的低成本处理。用于形成电极柱的实施例开始于在第一平坦化层上形成硅化钨导电层。对于第一实施例，使用具有间隔透明区域的图案的光刻掩模形成柱。间隔透明区域的尺寸和间隔开的透明区域之间的距离小于光刻工具的分辨率。用掩模形成间隔氧化物岛，并用作蚀刻掩模以与导电层形成间隔的柱。用于制造多支柱电容器的第一实施例形成比光刻工具的分辨率小的尺寸的柱。用于形成柱的第二实施例涉及使用小的硅化钛岛作为蚀刻掩模来限定柱。

5. 发明授权

US06335633B1 Adjustable, full CMOS input buffer for TTL, CMOS, or low swing input protocols 有权
标题翻译：适用于TTL，CMOS或低摆幅输入协议的可调整的全CMOS输入缓冲器
公开(公告)号：US06335633B1
公开(公告)日：2002-01-01
申请号：US09498982
申请日：2000-02-07
申请人： Howard Clayton Kirsch
发明人： Howard Clayton Kirsch
IPC分类号： H03K19003
CPC分类号： H03K19/00384 , H03K19/018585
摘要： An input buffer within an integrated circuit capable of receiving an input signal that complies with the electrical characteristic voltage levels of TTL, LVTTL, SSTL, or GTL, buffering the input signal, and converting the input signal to an output signal having voltage levels acceptable to internal circuitry of the integrated circuits is described. The input buffer will have an adjustable threshold trip point at which the input signal will cause the output signal to change between a first logic state and a second logic state. The adjustable threshold trip point will be determined by an adjustment voltage circuit that is immune to variation in semiconductor processing parameters, power supply voltage and operating temperature.
摘要翻译：集成电路内的输入缓冲器，能够接收符合TTL，LVTTL，SSTL或GTL的电特性电压电平的输入信号，缓冲输入信号，并将输入信号转换成具有可接受电压电平的输出信号描述集成电路的内部电路。输入缓冲器将具有可调节的阈值跳变点，输入信号将使输入信号在第一逻辑状态和第二逻辑状态之间变化。可调节的阈值跳变点将由不受半导体加工参数，电源电压和工作温度变化影响的调节电压电路决定。

6. 发明授权

US6023174A Adjustable, full CMOS input buffer for TTL, CMOS, or low swing input protocols 失效
公开(公告)号：US6023174A
公开(公告)日：2000-02-08
申请号：US891973
申请日：1997-07-11
申请人： Howard Clayton Kirsch
发明人： Howard Clayton Kirsch
IPC分类号： H03K19/003 , H03K19/0185
CPC分类号： H03K19/00384 , H03K19/018585
摘要： An input buffer within an integrated circuit capable of receiving an input signal that complies with the electrical characteristic voltage levels of TTL, LVTTL, SSTL, or GTL, buffering the input signal, and converting the input signal to an output signal having voltage levels acceptable to internal circuitry of the integrated circuits is described. The input buffer will have an adjustable threshold trip point at which the input signal will cause the output signal to change between a first logic state and a second logic state. The adjustable threshold trip point will be determined by an adjustment voltage circuit that is immune to variation in semiconductor processing parameters, power supply voltage and operating temperature.

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