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1. 发明授权

US5786709A Integrated circuit output driver incorporating power distribution noise suppression circuitry 失效
标题翻译：集成电路输出驱动器，并入功率分配噪声抑制电路
公开(公告)号：US5786709A
公开(公告)日：1998-07-28
申请号：US738214
申请日：1996-10-25
申请人： Howard C. Kirsch , Yen-Tai Lin , Chiun-chi Shen , Jiang-Hong Ho , Jack-Lian Kuo
发明人： Howard C. Kirsch , Yen-Tai Lin , Chiun-chi Shen , Jiang-Hong Ho , Jack-Lian Kuo
IPC分类号： H03K17/16 , H03K19/003 , H03K19/0948
CPC分类号： H03K17/165 , H03K17/167 , H03K19/00361
摘要： A circuit for the control of a power or ground distribution transient voltage or power bounce or ground bounce is described. The circuit has a driver transistor of a first conductivity type and a driver transistor of a second conductivity type connected so as to be able to transfer a voltage to a data output terminal from a I/O voltage distribution network or a I/O ground distribution network. As the output terminal changes from a logic 1 to a logic 0 the driver transistor of the first conductivity type will conduct and a ground distribution voltage transient will begin to appear. A suppression transistor of the first conductivity type that will begin to conduct to begin cessation of conduction of the driver transistor of the first conductivity type decreasing the slew rate of the driver transistor of the first conductivity type. As the output terminal changes from a logic 0 to a logic 1 the driver transistor of the second conductivity type will conduct and a power distribution voltage transient will begin to appear. A suppression transistor of the second conductivity type that will begin to conduct to begin cessation of conduction of the driver transistor of the second conductivity type decreasing the slew rate of the driver transistor of the second conductivity type. The transistors may be PMOS, NMOS, NPN bipolar, or PNP bipolar integrated upon a silicon or compound semiconductor substrate.
摘要翻译：描述了用于控制电源或地面分配瞬态电压或电源反弹或地面反弹的电路。电路具有第一导电类型的驱动晶体管和第二导电类型的驱动晶体管，其连接成能够将电压从I / O电压分配网络或I / O地面分布传递到数据输出端子网络。当输出端从逻辑1变为逻辑0时，第一导电类型的驱动晶体管将导通，并且开始接地配电电压瞬变。第一导电类型的抑制晶体管将开始导通以开始停止第一导电类型的驱动晶体管的导通，从而降低第一导电类型的驱动晶体管的转换速率。当输出端子从逻辑0变为逻辑1时，第二导电类型的驱动晶体管将导通，并且将开始出现配电电压瞬变。第二导电类型的抑制晶体管将开始导通以开始停止第二导电类型的驱动晶体管的导通，从而降低第二导电类型的驱动晶体管的转换速率。晶体管可以是集成在硅或化合物半导体衬底上的PMOS，NMOS，NPN双极或PNP双极。

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