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    • 2. 发明授权
    • Power converter module
    • 电源转换模块
    • US08687393B2
    • 2014-04-01
    • US13421851
    • 2012-03-15
    • Shu-Chia LinWen-Yueh HsiehChing-Yuan Lin
    • Shu-Chia LinWen-Yueh HsiehChing-Yuan Lin
    • H02M3/24
    • H02M7/53871H02M2001/0022
    • A power converter module is disclosed, which is an all-digital module. The power converter module includes a reference voltage generation unit, a voltage loop control unit, a current loop control unit, an input voltage compensation unit, and a pulse width modulation generation unit, to transfer input power to stable output power for providing power to an external loading device through driving bridge switch unit with external driver. The voltage loop control unit and the current loop control unit contain a proportion-integral-differentiation controller for receiving signal related to voltage and current of loading device to form voltage control loop and current control loop. The pulse width modulation generation unit contains function of deciding necessary stop time to improve quality of output power and decrease the effect of input power and loading variation, and to provide stable sine-waveform output power to the external loading device.
    • 公开了一种功率转换器模块,其是全数字模块。 功率转换器模块包括参考电压产生单元,电压环路控制单元,电流环路控制单元,输入电压补偿单元和脉冲宽度调制生成单元,用于将输入功率传送到稳定的输出功率,以向 外部负载装置通过驱动桥式开关单元与外部驱动器。 电压环控制单元和电流环控制单元包含一个比例积分微分控制器,用于接收与负载装置的电压和电流相关的信号,形成电压控制回路和电流控制回路。 脉冲宽度调制生成单元包含决定必要的停止时间以提高输出功率的质量并降低输入功率和负载变化的影响的功能,并向外部负载装置提供稳定的正弦波输出功率。
    • 3. 发明授权
    • Digital power factor correction device
    • 数字功率因数校正装置
    • US08664928B2
    • 2014-03-04
    • US13421847
    • 2012-03-15
    • Shu-Chia LinWen-Yueh HsiehChing-Yuan Lin
    • Shu-Chia LinWen-Yueh HsiehChing-Yuan Lin
    • G05F1/00
    • H02M3/158H02M1/4208H02M2001/009Y02B70/126Y10T307/258
    • A digital power factor correction device is provided, which is an all-digital control module. The digital power factor correction device includes a voltage loop control unit, an input power control unit, a current loop control unit, and a pulse width modulation generation unit, to perform power factor correction for minimizing the phase difference between input current and input voltage through adjusting input current with an external driver and a switch unit. The voltage loop control unit and the current loop control unit contain a proportion-integral-differentiation controller to form a voltage control loop and a current control loop, respectively. The input power control unit adjusts current waveform according to the input power, while the pulse width modulation generation unit determines the stop time of pulse width modulation to produce a pulse width modulation signal, to control the external driver and the switch unit for eliminating loading effect.
    • 提供了一种数字功率因数校正装置,它是全数字控制模块。 数字功率因数校正装置包括电压环路控制单元,输入功率控制单元,电流环路控制单元和脉冲宽度调制生成单元,以执行功率因数校正,以使输入电流和输入电压之间的相位差最小化 用外部驱动器和开关单元调节输入电流。 电压回路控制单元和电流回路控制单元分别包含比例积分微分控制器,分别形成电压控制回路和电流控制回路。 输入功率控制单元根据输入功率调整电流波形,而脉宽调制生成单元确定脉冲宽度调制的停止时间以产生脉宽调制信号,控制外部驱动器和开关单元以消除负载效应 。
    • 4. 发明申请
    • DIGITAL POWER FACTOR CORRECTION DEVICE
    • 数字功率因数校正装置
    • US20120286745A1
    • 2012-11-15
    • US13421847
    • 2012-03-15
    • SHU-CHIA LINWen-Yueh HsiehChing-Yuan Lin
    • SHU-CHIA LINWen-Yueh HsiehChing-Yuan Lin
    • G05F1/70
    • H02M3/158H02M1/4208H02M2001/009Y02B70/126Y10T307/258
    • A digital power factor correction device is provided, which is an all-digital control module. The digital power factor correction device includes a voltage loop control unit, an input power control unit, a current loop control unit, and a pulse width modulation generation unit, to perform power factor correction for minimizing the phase difference between input current and input voltage through adjusting input current with an external driver and a switch unit. The voltage loop control unit and the current loop control unit contain proportion-integral-differentiation controller to form voltage control loop and current control loop, respectively. The input power control unit adjusts current waveform according to the input power, while the pulse width modulation generation unit decides stop time of pulse width modulation to produce a pulse width modulation signal, to control the external driver and the switch unit for eliminating loading effect.
    • 提供了一种数字功率因数校正装置,它是全数字控制模块。 数字功率因数校正装置包括电压环路控制单元,输入功率控制单元,电流环路控制单元和脉冲宽度调制生成单元,以执行功率因数校正,以使输入电流和输入电压之间的相位差最小化 用外部驱动器和开关单元调节输入电流。 电压环控制单元和电流环控制单元分别包含比例积分微分控制器,以形成电压控制回路和电流控制回路。 输入功率控制单元根据输入功率调整电流波形,而脉宽调制生成单元决定脉宽调制的停止时间,生成脉宽调制信号,控制外部驱动器和开关单元,消除负载效应。
    • 5. 发明申请
    • ROTARY SPINDLE HEAD FOR MACHINE TOOL
    • 机床用旋转主轴
    • US20120020754A1
    • 2012-01-26
    • US12945592
    • 2010-11-12
    • Feng-Ming OuYu-Hsi HsingHsi-Hung HsiaoChing-Yuan Lin
    • Feng-Ming OuYu-Hsi HsingHsi-Hung HsiaoChing-Yuan Lin
    • B23C1/12
    • B23Q1/5406B23Q5/12B23Q2210/004B23Q2220/006Y10T409/307672
    • A rotary spindle head for a machine tool, comprises a rotary spindle unit, a fork-shaped spindle base, and a driving unit, wherein the fork-shaped spindle base is disposed to the machine tool and is rotatably connecting to the rotary spindle unit, while the driving unit, having a torque motor and a planetary-gear speed reducer coaxially coupled to the torque motor, is coupled to the fork-shaped spindle base. The planetary-gear speed reducer is coupled to the rotary spindle unit for driving the rotary spindle unit to rotate within the fork-shaped spindle base. Since the planetary-gear speed reducer has lower speed reduction ratio and has a speed reducing design with the coaxial arrangement of the input/output shafts, it is capable of magnifying the torque of the torque motor for retaining a higher rotation speed so that the rotary spindle head can be utilized for high-speed light-machining and high-torque heavy-machining.
    • 一种用于机床的旋转主轴头,包括旋转主轴单元,叉形主轴基座和驱动单元,其中叉状心轴基座设置在机床上并且可旋转地连接到旋转主轴单元, 而具有扭矩电动机和同轴联接到扭矩电动机的行星齿轮减速器的驱动单元联接到叉状心轴基座。 行星齿轮减速器联接到旋转主轴单元,用于驱动旋转主轴单元在叉状心轴基座内旋转。 由于行星齿轮减速器具有较低的减速比,并且具有与输入/输出轴的同轴布置的减速设计,因此能够放大转矩电动机的扭矩以保持更高的转速,使得旋转 主轴头可用于高速光加工和高扭矩重型加工。
    • 7. 发明授权
    • Non-volatile memory and operating method thereof
    • 非易失性存储器及其操作方法
    • US07450418B2
    • 2008-11-11
    • US11403437
    • 2006-04-12
    • Hong-Yi LiaoWu-Chang ChangChing-Yuan Lin
    • Hong-Yi LiaoWu-Chang ChangChing-Yuan Lin
    • G11C11/34
    • G11C16/0416G11C16/0433H01L27/115H01L27/11568
    • An operating method of a non-volatile memory is provided. The non-volatile memory includes plural memory cells. Each memory cell includes a charge storage structure, a gate, and a source and a drain disposed in the well on the both sides of the gate. During an erasing operation, a first voltage is applied to the source of the selected memory cell, a second voltage is applied to the gate of each selected memory cell, and a third voltage is applied to the well; and the drain of the selected memory cell is floated, so that the selected memory cell is erased. In the meantime, the fourth voltage is applied to the drain of each unselected memory cell, the fifth voltage is applied to the gate of the unselected memory cell, and the source of the unselected memory cell is floated to prevent the unselected memory cell from being erased.
    • 提供了一种非易失性存储器的操作方法。 非易失性存储器包括多个存储单元。 每个存储单元包括电荷存储结构,栅极以及设置在栅极两侧的阱中的源极和漏极。 在擦除操作期间,将第一电压施加到所选择的存储单元的源极,将第二电压施加到每个选择的存储单元的栅极,并将第三电压施加到阱; 并且所选择的存储单元的漏极浮动,使得所选存储单元被擦除。 同时,将第四电压施加到每个未选择的存储单元的漏极,第五电压被施加到未选择的存储单元的栅极,并且未选择的存储单元的源被浮置以防止未选择的存储单元 擦除
    • 10. 发明授权
    • Nonvolatile memory device having self reprogramming function
    • 具有自重新编程功能的非易失性存储器件
    • US07385855B2
    • 2008-06-10
    • US11306370
    • 2005-12-26
    • Ching-Yuan LinChien-Liang Kuo
    • Ching-Yuan LinChien-Liang Kuo
    • G11C16/06
    • G11C29/52G11C16/04G11C16/10G11C16/3431G11C29/12G11C29/1201G11C2029/1204
    • A nonvolatile memory device having a self reprogramming function is provided. The nonvolatile memory device includes a memory cell, a first transistor, a second transistor, and a latch circuit. The memory cell is for data storage. The first transistor receives a reading control signal at a gate. And a first source/drain is electrically coupled to the memory cell. The second transistor receives a reset control signal at a gate. A source/drain is electrically coupled to a second source/drain of the first transistor, and a second source/drain of the second transistor is grounded. In addition, the electrical characteristics of the second transistor are opposite to that of the first transistor. The latch circuit includes a latch input terminal and a latch output terminal. In which, the latch input terminal is electrically coupled to the second source/drain of the first transistor and the first source/drain of the second transistor.
    • 提供了具有自重新编程功能的非易失性存储装置。 非易失性存储器件包括存储单元,第一晶体管,第二晶体管和锁存电路。 存储单元用于数据存储。 第一晶体管在门处接收读取控制信号。 并且第一源极/漏极电耦合到存储器单元。 第二晶体管在门处接收复位控制信号。 源极/漏极电耦合到第一晶体管的第二源极/漏极,并且第二晶体管的第二源极/漏极接地。 此外,第二晶体管的电特性与第一晶体管的电特性相反。 锁存电路包括锁存输入端和锁存输出端。 其中,锁存器输入端子电耦合到第一晶体管的第二源极/漏极和第二晶体管的第一源极/漏极。