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21. 发明申请

US20070057300A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20070057300A1
公开(公告)日：2007-03-15
申请号：US11466796
申请日：2006-08-24
申请人： Shinichi Fukada
发明人： Shinichi Fukada
IPC分类号： H01L29/94
CPC分类号： H01L27/11502 , H01L29/40111
摘要： A semiconductor device includes a substrate, a first electrode provided above the substrate, a ferroelectric layer provided above the first electrode, a second electrode provided above the ferroelectric layer, and a dielectric side spacer that is provided above the first electrode and on a side surface of at least the ferroelectric layer.
摘要翻译：半导体器件包括衬底，设置在衬底上的第一电极，设置在第一电极上方的铁电层，设置在铁电层上方的第二电极和设置在第一电极上方和侧表面上的电介质侧衬垫至少是铁电层。

22. 发明授权

US07074665B2 Method of fabricating semiconductor device 失效
公开(公告)号：US07074665B2
公开(公告)日：2006-07-11
申请号：US10701423
申请日：2003-11-06
申请人： Shinichi Fukada , Naotaka Hashimoto , Masanori Kojima , Hiroshi Momiji , Hiromi Abe , Masayuki Suzuki
发明人： Shinichi Fukada , Naotaka Hashimoto , Masanori Kojima , Hiroshi Momiji , Hiromi Abe , Masayuki Suzuki
IPC分类号： H01L21/8238
CPC分类号： H01L29/6659 , H01L21/2652 , H01L21/28518 , H01L21/823814 , H01L21/823835 , H01L21/823842 , H01L29/665 , H01L29/66545 , H01L29/7833
摘要： An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

23. 发明授权

US06700152B2 Dynamic random access memory including a logic circuit and an improved storage capacitor arrangement 失效
标题翻译：包括逻辑电路和改进的存储电容器布置的动态随机存取存储器
公开(公告)号：US06700152B2
公开(公告)日：2004-03-02
申请号：US10231053
申请日：2002-08-30
申请人： Takuya Fukuda , Nobuyoshi Kobayashi , Yoshitaka Nakamura , Masayoshi Saito , Shinichi Fukada , Yoshifumi Kawamoto
发明人： Takuya Fukuda , Nobuyoshi Kobayashi , Yoshitaka Nakamura , Masayoshi Saito , Shinichi Fukada , Yoshifumi Kawamoto
IPC分类号： H01L27108
CPC分类号： H01L27/10808 , H01L27/108
摘要： The new structure of a memory cell which enables avoiding the problem of a step without increasing the number of processes, the structure of a semiconductor integrated circuit in which a common part of the same substrate in a manufacturing process is increased and the structure of the semiconductor integrated circuit which allows measures for environment obstacles without increasing the number of processes are disclosed. Memory cell structure in which a capacitor is formed in the uppermost layer of plural metal wiring layers by connecting the storage node of the capacitor to a diffusion layer via plugs and pads is adopted. It is desirable that a dielectric film formed in a metal wiring layer under the uppermost layer and a supplementary capacitor composed of a storage node and a plate electrode are connected to the capacitor. It is also desirable that the plate electrode of the capacitor covers the chip.
摘要翻译：存储单元的新结构能够在不增加处理次数的情况下避免步骤的问题，制造过程中同一基板的公共部分增加的半导体集成电路的结构和半导体的结构公开了不增加处理次数的环境障碍措施的集成电路。采用通过将电容器的存储节点经由插头和焊盘连接到扩散层，在多个金属布线层的最上层形成电容器的存储单元结构。最好将形成在最上层的金属布线层中的电介质膜和由存储节点和平板电极构成的辅助电容器连接到电容器。还希望电容器的平板电极覆盖芯片。

24. 发明授权

US06291847B1 Semiconductor integrated circuit device and process for manufacturing the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US06291847B1
公开(公告)日：2001-09-18
申请号：US09159754
申请日：1998-09-24
申请人： Kiyonori Ohyu , Makoto Ohkura , Aritoshi Sugimoto , Yoshitaka Tadaki , Makoto Ogasawara , Masashi Horiguchi , Norio Hasegawa , Shinichi Fukada
发明人： Kiyonori Ohyu , Makoto Ohkura , Aritoshi Sugimoto , Yoshitaka Tadaki , Makoto Ogasawara , Masashi Horiguchi , Norio Hasegawa , Shinichi Fukada
IPC分类号： H01L27108
CPC分类号： H01L27/10897 , H01L27/10814 , H01L27/10894
摘要： A field oxide film 3 in a region where relief cells are formed is made wider than the field oxide film 3 in a region where normal memory cells are formed thereby to make a field relaxation layer 8r of the relief cells deeper than the field relaxation layer 8 of the normal cells, and the depletion layer of the sources and drains (n-type semiconductor regions) of the relief cells is widened to weaken the junction field.
摘要翻译：在形成正常存储单元的区域中，形成有浮雕单元的区域中的场氧化膜3比场氧化膜3宽，使得浮雕单元的场弛豫层8r比场弛豫层8更深的正电池，并且补充电池的源极和漏极（n型半导体区域）的耗尽层变宽以削弱结场。

25. 发明申请

US20110149318A1 APPARATUS, METHOD AND PROGRAM FOR PROCESSING AN IMAGE 失效
标题翻译：用于处理图像的装置，方法和程序
公开(公告)号：US20110149318A1
公开(公告)日：2011-06-23
申请号：US13037203
申请日：2011-02-28
申请人： Shinichi Fukada , Akio Suzuki
发明人： Shinichi Fukada , Akio Suzuki
IPC分类号： H04N1/60 , G06K9/00
CPC分类号： H04N1/46
摘要： An image processing apparatus includes a comparison unit, a change unit, and a printing unit to perform variable printing in a form of a composite of a master page and a variable page. The comparison unit compares a color of the master page and a color of the variable page near a boundary line between the master page and the boundary page. In a case where the master page and the variable page are similar in color near the boundary line, the change unit changes the master page to another master page with a color that is not similar to the color of the variable page. The printing unit prints the another master page and the variable page in a composite form.
摘要翻译：图像处理装置包括比较单元，改变单元和打印单元，以主页和可变页的复合形式执行可变打印。比较单元将母版页的颜色与母版页和边界页之间的边界线附近的可变页的颜色进行比较。在主页和可变页在边界线附近的颜色相似的情况下，更改单元将主页更改为具有与可变页的颜色不相似的颜色的另一母版页。打印单元以复合形式打印另一母版页和变量页。

26. 发明申请

US20100264476A1 FERROELECTRIC MEMORY AND ITS MANUFACTURING METHOD 有权
标题翻译：电磁记忆及其制造方法
公开(公告)号：US20100264476A1
公开(公告)日：2010-10-21
申请号：US12829924
申请日：2010-07-02
申请人： Shinichi Fukada
发明人： Shinichi Fukada
IPC分类号： H01L27/108
CPC分类号： H01L27/11502 , H01L27/11507
摘要： To securely prevent hydrogen from entering a ferroelectric layer of a ferroelectric memory. A first hydrogen barrier layer 5 is formed on the lower side of ferroelectric capacitors 7. Upper surfaces and side surfaces of the ferroelectric capacitors 7 are covered by a second hydrogen barrier layer. All upper electrodes 7c of the plural ferroelectric capacitors 7 to be connected to a common plate line P are connected to one another by an upper wiring layer 91. The upper wiring layer 91 is connected to the plate line P through a lower wiring 32 provided below the ferroelectric capacitors 7. A third hydrogen barrier layer 92 is formed on the upper wiring layer 91 such that all edge sections 92a of the third hydrogen barrier layer 92 come in contact with the first hydrogen barrier layer 5.
摘要翻译：可靠地防止氢气进入铁电存储器的铁电层。第一氢阻挡层5形成在铁电电容器7的下侧。铁电电容器7的上表面和侧表面被第二氢阻挡层覆盖。要连接到公共板线P的多个铁电电容器7的所有上电极7c通过上布线层91彼此连接。上布线层91通过下面布置的下布线32连接到板线P 铁电电容器7.第三氢阻挡层92形成在上布线层91上，使得第三氢阻挡层92的所有边缘部分92a与第一氢阻挡层5接触。

27. 发明申请

US20090263943A1 METHOD OF FABRICATING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 有权
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：US20090263943A1
公开(公告)日：2009-10-22
申请号：US12492276
申请日：2009-06-26
申请人： Shinji Nishihara , Shuji Ikeda , Naotaka Hashimoto , Hiroshi Momiji , Hiromi Abe , Shinichi Fukada , Masayuki Suzuki
发明人： Shinji Nishihara , Shuji Ikeda , Naotaka Hashimoto , Hiroshi Momiji , Hiromi Abe , Shinichi Fukada , Masayuki Suzuki
IPC分类号： H01L21/336 , H01L21/28 , H01L21/44
CPC分类号： H01L21/823814 , C23C14/16 , C23C14/3414 , H01L21/28518 , H01L21/2855 , H01L21/31608 , H01L21/76229 , H01L21/76828 , H01L21/823835 , H01L21/823842 , H01L21/823871 , H01L23/53223 , H01L29/456 , H01L29/4933 , H01L29/665 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETS by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.
摘要翻译：在MOSFET的栅电极，源极和漏极的表面上形成具有低电阻和小的漏电流的Co硅化物层，通过使用高纯度Co靶溅射沉积在晶片的主平面上的Co膜， Co纯度至少为99.99％，Fe和Ni含量不大于10ppm，Co的纯度优选为99.999％。

28. 发明授权

US07514272B2 Method of manufacturing ferroelectric memory device 有权
标题翻译：铁电存储器件的制造方法
公开(公告)号：US07514272B2
公开(公告)日：2009-04-07
申请号：US11717791
申请日：2007-03-13
申请人： Shinichi Fukada , Hiroyuki Mitsui
发明人： Shinichi Fukada , Hiroyuki Mitsui
IPC分类号： H01L21/00
CPC分类号： H01L27/11507 , H01L21/7687 , H01L27/11502 , H01L28/55 , H01L28/65
摘要： A method of manufacturing a ferroelectric memory device includes: forming an active element on a substrate; forming an interlayer insulating layer on the substrate; forming an opening on the interlayer insulating layer and forming a contact plug inside the opening; forming a foundation layer above the substrate; and laminating, on the foundation layer, a first electrode, a ferroelectric layer, and a second electrode. In this method, the forming of the foundation layer includes: forming a first titanium layer having a thickness less than a depth of a recess; nitriding the first titanium layer into a first titanium nitride layer; forming a second titanium layer on the first titanium nitride layer so as to at least partially fill the recess remaining on the contact plug; nitriding the second titanium layer into a second titanium nitride layer, and polishing a surface of the second titanium nitride layer.
摘要翻译：制造铁电存储器件的方法包括：在衬底上形成有源元件; 在所述基板上形成层间绝缘层; 在所述层间绝缘层上形成开口，并在所述开口内形成接触插塞; 在基底上形成基础层; 并且在所述基础层上层叠第一电极，铁电体层和第二电极。在该方法中，基底层的形成包括：形成厚度小于凹部的深度的第一钛层; 将第一钛层氮化为第一氮化钛层; 在所述第一氮化钛层上形成第二钛层，以至少部分地填充残留在所述接触插塞上的凹部; 将第二钛层氮化成第二氮化钛层，并且研磨第二氮化钛层的表面。

29. 发明授权

US07279342B2 Ferroelectric memory 有权
标题翻译：铁电存储器
公开(公告)号：US07279342B2
公开(公告)日：2007-10-09
申请号：US11210010
申请日：2005-08-23
申请人： Mamoru Ueda , Kazuhiro Masuda , Shinichi Fukada
发明人： Mamoru Ueda , Kazuhiro Masuda , Shinichi Fukada
IPC分类号： H01L21/00
CPC分类号： H01L27/11502 , H01L27/11507
摘要： A ferroelectric memory includes a base member, a first dielectric layer formed above the base member, a second dielectric layer formed above the first dielectric layer, a contact hole that penetrates the first and second dielectric layers, a plug formed in the contact hole, and a barrier layer formed above the plug, and a ferroelectric capacitor formed from a lower electrode, a ferroelectric layer and an upper electrode successively laminated in a region including above the plug. The second dielectric layer has a property that is more difficult to be polished than the plug and the first dielectric layer.
摘要翻译：铁电存储器包括基底构件，形成在基底构件上的第一电介质层，形成在第一电介质层上方的第二电介质层，穿透第一和第二电介质层的接触孔，形成在接触孔中的插塞，以及形成在插塞上方的阻挡层，以及由下电极，强电介质层和上电极形成的强电介质电容器，其连续地层压在包括在插塞上方的区域中。第二电介质层具有比插塞和第一电介质层更难以抛光的性质。

30. 发明授权

US07262065B2 Ferroelectric memory and its manufacturing method 有权
标题翻译：铁电记忆及其制造方法
公开(公告)号：US07262065B2
公开(公告)日：2007-08-28
申请号：US11226728
申请日：2005-09-14
申请人： Hiroyuki Mitsui , Katsuo Takano , Shinichi Fukada , Hiroshi Matsuki
发明人： Hiroyuki Mitsui , Katsuo Takano , Shinichi Fukada , Hiroshi Matsuki
IPC分类号： H01L21/00 , H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L28/57 , H01L27/11507 , H01L28/65
摘要： A method for manufacturing a ferroelectric memory includes: (a) forming first and second contact sections on a first dielectric layer formed above a base substrate; (b) forming a laminated body having a lower electrode, a ferroelectric layer and an upper electrode successively laminated; (c) forming a conductive hard mask above the laminated body and etching an area of the laminated body exposed through the hard mask, to thereby form a ferroelectric capacitor above the first contact section; (d) forming above the first dielectric layer a second dielectric layer that covers the hard mask, the ferroelectric capacitor and the second contact section; (e) forming a contact hole in the second dielectric layer which exposes the second contact section; (f) providing a conductive layer in an area including the contact hole for forming a third contact section; and (g) polishing the conductive layer and the second dielectric layer until the hard mask above the ferroelectric capacitor is exposed.
摘要翻译：制造铁电存储器的方法包括：（a）在形成在基底基板上的第一电介质层上形成第一和第二接触部分; （b）依次层叠具有下电极，铁电层和上电极的叠层体; （c）在层叠体上形成导电硬掩模，并蚀刻通过硬掩模暴露的层叠体的区域，从而在第一接触部分上形成铁电电容器; （d）在所述第一电介质层的上方形成覆盖所述硬掩模，所述强电介质电容器和所述第二接触部的第二电介质层; （e）在所述第二电介质层中形成暴露所述第二接触部分的接触孔; （f）在包括用于形成第三接触部分的接触孔的区域中提供导电层; 和（g）研磨导电层和第二介电层，直到暴露铁电电容器上方的硬掩模。

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