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1. 发明授权

US06479899B1 Semiconductor integrated circuit device and process for manufacturing the same 失效
公开(公告)号：US06479899B1
公开(公告)日：2002-11-12
申请号：US09051978
申请日：1998-04-24
申请人： Takuya Fukuda , Nobuyoshi Kobayashi , Yoshitaka Nakamura , Masayoshi Saito , Shinichi Fukada , Yoshifumi Kawamoto
发明人： Takuya Fukuda , Nobuyoshi Kobayashi , Yoshitaka Nakamura , Masayoshi Saito , Shinichi Fukada , Yoshifumi Kawamoto
IPC分类号： H01L2348
CPC分类号： H01L27/10808 , H01L27/108
摘要： The new structure of a memory cell which enables avoiding the problem of a step without increasing the number of processes, the structure of a semiconductor integrated circuit in which a common part of the same substrate in a manufacturing process is increased and the structure of the semiconductor integrated circuit which allows measures for environment obstacles without increasing the number of processes are disclosed. Memory cell structure in which a capacitor is formed in the uppermost layer of plural metal wiring layers by connecting the storage node of the capacitor to a diffusion layer via plugs and pads is adopted. It is desirable that a dielectric film formed in a metal wiring layer under the uppermost layer and a supplementary capacitor composed of a storage node and a plate electrode are connected to the capacitor. It is also desirable that the plate electrode of the capacitor covers the chip.

2. 发明授权

US06432769B1 Semiconductor integrated circuit device and process for manufacture the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US06432769B1
公开(公告)日：2002-08-13
申请号：US09642582
申请日：2000-08-22
申请人： Takuya Fukuda , Nobuyoshi Kobayashi , Yoshitaka Nakamura , Masayoshi Saito , Shinichi Fukada , Yoshifumi Kawamoto
发明人： Takuya Fukuda , Nobuyoshi Kobayashi , Yoshitaka Nakamura , Masayoshi Saito , Shinichi Fukada , Yoshifumi Kawamoto
IPC分类号： H01L2972
CPC分类号： H01L27/10808 , H01L27/108
摘要： The new structure of a memory cell which enables avoiding the problem of a step without increasing the number of processes, the structure of a semiconductor integrated circuit in which a common part of the same substrate in a manufacturing process is increased and the structure of the semiconductor integrated circuit which allows measures for environment obstacles without increasing the number of processes are disclosed. Memory cell structure in which a capacitor is formed in the uppermost layer of plural metal wiring layers by connecting the storage node of the capacitor to a diffusion layer via plugs and pads is adopted. It is desirable that a dielectric film formed in a metal wiring layer under the uppermost layer and a supplementary capacitor composed of a storage node and a plate electrode are connected to the capacitor. It is also desirable that the plate electrode of the capacitor covers the chip.
摘要翻译：存储单元的新结构能够在不增加处理次数的情况下避免步骤的问题，制造过程中同一基板的公共部分增加的半导体集成电路的结构和半导体的结构公开了不增加处理次数的环境障碍措施的集成电路。采用通过将电容器的存储节点经由插头和焊盘连接到扩散层，在多个金属布线层的最上层形成电容器的存储单元结构。最好将形成在最上层的金属布线层中的电介质膜和由存储节点和平板电极构成的辅助电容器连接到电容器。还希望电容器的平板电极覆盖芯片。

3. 发明授权

US06700152B2 Dynamic random access memory including a logic circuit and an improved storage capacitor arrangement 失效
标题翻译：包括逻辑电路和改进的存储电容器布置的动态随机存取存储器
公开(公告)号：US06700152B2
公开(公告)日：2004-03-02
申请号：US10231053
申请日：2002-08-30
申请人： Takuya Fukuda , Nobuyoshi Kobayashi , Yoshitaka Nakamura , Masayoshi Saito , Shinichi Fukada , Yoshifumi Kawamoto
发明人： Takuya Fukuda , Nobuyoshi Kobayashi , Yoshitaka Nakamura , Masayoshi Saito , Shinichi Fukada , Yoshifumi Kawamoto
IPC分类号： H01L27108
CPC分类号： H01L27/10808 , H01L27/108
摘要： The new structure of a memory cell which enables avoiding the problem of a step without increasing the number of processes, the structure of a semiconductor integrated circuit in which a common part of the same substrate in a manufacturing process is increased and the structure of the semiconductor integrated circuit which allows measures for environment obstacles without increasing the number of processes are disclosed. Memory cell structure in which a capacitor is formed in the uppermost layer of plural metal wiring layers by connecting the storage node of the capacitor to a diffusion layer via plugs and pads is adopted. It is desirable that a dielectric film formed in a metal wiring layer under the uppermost layer and a supplementary capacitor composed of a storage node and a plate electrode are connected to the capacitor. It is also desirable that the plate electrode of the capacitor covers the chip.
摘要翻译：存储单元的新结构能够在不增加处理次数的情况下避免步骤的问题，制造过程中同一基板的公共部分增加的半导体集成电路的结构和半导体的结构公开了不增加处理次数的环境障碍措施的集成电路。采用通过将电容器的存储节点经由插头和焊盘连接到扩散层，在多个金属布线层的最上层形成电容器的存储单元结构。最好将形成在最上层的金属布线层中的电介质膜和由存储节点和平板电极构成的辅助电容器连接到电容器。还希望电容器的平板电极覆盖芯片。

4. 发明授权

US5986299A Semiconductor integrated circuit device having multi-level wiring capacitor structures 失效
标题翻译：具有多电平布线电容器结构的半导体集成电路器件
公开(公告)号：US5986299A
公开(公告)日：1999-11-16
申请号：US962730
申请日：1997-11-03
申请人： Yoshitaka Nakamura , Nobuyoshi Kobayashi , Takuya Fukuda , Masayoshi Saito
发明人： Yoshitaka Nakamura , Nobuyoshi Kobayashi , Takuya Fukuda , Masayoshi Saito
IPC分类号： H01L23/522 , H01L21/768 , H01L21/822 , H01L21/8242 , H01L21/8246 , H01L27/04 , H01L27/105 , H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L27/10844 , H01L21/768 , H01L27/105 , H01L27/10808 , H01L27/10852
摘要： A semiconductor integrated circuit device of the invention is provided with a memory cell array portion and a peripheral circuit portions. In the memory cell array portion, a plurality of plugs which penetrate each of a plurality of interlayer insulating films and the sides of which are almost vertical are directly connected in sequence. In the peripheral circuit portion, a plurality of plugs are mutually connected through contact pads for wiring.
摘要翻译：本发明的半导体集成电路器件具有存储单元阵列部分和外围电路部分。在存储单元阵列部分中，贯穿多个层间绝缘膜中的每一个并且其侧面几乎垂直的多个插头依次直接连接。在外围电路部分中，多个插头通过用于布线的接触垫相互连接。

5. 发明授权

US06303478B1 Semiconductor integrated circuit device and method for fabricating the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US06303478B1
公开(公告)日：2001-10-16
申请号：US09421125
申请日：1999-10-19
申请人： Yoshitaka Nakamura , Nobuyoshi Kobayashi , Takuya Fukuda , Masayoshi Saito
发明人： Yoshitaka Nakamura , Nobuyoshi Kobayashi , Takuya Fukuda , Masayoshi Saito
IPC分类号： H01L218242
CPC分类号： H01L27/10844 , H01L21/768 , H01L27/105 , H01L27/10808 , H01L27/10852
摘要： A method of fabricating a semiconductor device having, for example, a memory cell array portion and a peripheral circuit portion is disclosed. By such a method, a first interlayer insulating film is formed on a semiconductor substrate, a first connection hole is formed by selectively removing a predetermined portion of the first interlayer insulating film, the sides of the first hole being substantially vertical to the bottom thereof, a first plug is formed by padding the first hole with a metallic film and, subsequently, a second interlayer insulating film is formed on the first insulating film, a second hole is formed by selectively removing a predetermined portion of the second interlayer insulating film, the sides of the second hole being substantially vertical to the bottom thereof, and a second plug aligned to be in direct connection with the first plug is formed by padding the second hole with the metallic film. A MOS transistor is formed on the semiconductor substrate before the first interlayer insulating film is formed and the first hole formed is extended to expose the diffused layer of the MOS transistor. The surfaces of both the first and second interlayer insulating films are smoothed by a chemical mechanical polishing (CMP) method. The process of padding the connection holes with the metallic film is effected through a CVD or selective CVD method.
摘要翻译：公开了一种制造具有例如存储单元阵列部分和外围电路部分的半导体器件的方法。通过这样的方法，在半导体衬底上形成第一层间绝缘膜，通过选择性地去除第一层间绝缘膜的预定部分，第一孔的侧面基本垂直于其底部而形成第一连接孔，通过用金属膜填充第一孔而形成第一插塞，随后在第一绝缘膜上形成第二层间绝缘膜，通过选择性地去除第二层间绝缘膜的预定部分形成第二孔，第二孔的侧面基本上垂直于其底部，并且通过用金属膜填充第二孔而形成与第一塞直接连接的第二塞子。在形成第一层间绝缘膜之前，在半导体衬底上形成MOS晶体管，并且形成的第一孔延伸以露出MOS晶体管的扩散层。通过化学机械抛光（CMP）方法使第一和第二层间绝缘膜的表面平滑。用金属膜填充连接孔的过程通过CVD或选择性CVD方法进行。

6. 发明授权

US06215144B1 Semiconductor integrated circuit device, and method of manufacturing the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US06215144B1
公开(公告)日：2001-04-10
申请号：US09236223
申请日：1999-01-25
申请人： Masayoshi Saito , Yoshitaka Nakamura , Hidekazu Goto , Keizo Kawakita , Satoru Yamada , Toshihiro Sekiguchi , Isamu Asano , Yoshitaka Tadaki , Takuya Fukuda , Masayuki Suzuki , Tsuyoshi Tamaru , Naoki Fukuda , Hideo Aoki , Masayoshi Hirasawa
发明人： Masayoshi Saito , Yoshitaka Nakamura , Hidekazu Goto , Keizo Kawakita , Satoru Yamada , Toshihiro Sekiguchi , Isamu Asano , Yoshitaka Tadaki , Takuya Fukuda , Masayuki Suzuki , Tsuyoshi Tamaru , Naoki Fukuda , Hideo Aoki , Masayoshi Hirasawa
IPC分类号： H01L2972
CPC分类号： H01L21/76855 , H01L21/28518 , H01L21/31604 , H01L21/76801 , H01L21/76828 , H01L21/76837 , H01L21/76843 , H01L21/76856 , H01L21/7687 , H01L27/10814 , H01L27/10885 , H01L27/10894 , H01L28/40
摘要： In a DRAM having a capacitor-over-bitline structure in which the capacitive insulating film of an information storing capacitive element C is formed of a high dielectric material such as Ta2O5 (tantalum oxide) film 46, the portions of bit lines BL and first-layer interconnect lines 23 to 26 of a peripheral circuit which are in contact with at least an underlying silicon oxide film 28 are formed of a W film, the bit lines BL and the interconnect lines 23 to 26 being arranged below the information storing capacitive element C, whereby the adhesion at the interface between the bit lines BL and the interconnect lines 23 to 26 and the silicon oxide film is improved in terms of high-temperature heat treatment to be performed when the capacitive insulating film is being formed.
摘要翻译：在具有电容器的位线结构的DRAM中，信息存储电容元件C的电容绝缘膜由诸如Ta 2 O 5（氧化钽）膜46的高电介质材料形成，位线BL和第一 - 与W膜形成的与外部电路至少底层的氧化硅膜28接触的层间布线23〜26，位线BL和布线23〜26配置在信息存储电容元件C的下方从而在形成电容绝缘膜时进行的高温热处理方面提高了位线BL与布线23〜26之间界面处的粘附性和氧化硅膜。

7. 发明授权

US06638811B2 Method of manufacturing a semiconductor integrated circuit device having a capacitor 有权
标题翻译：具有电容器的半导体集成电路器件的制造方法
公开(公告)号：US06638811B2
公开(公告)日：2003-10-28
申请号：US10157977
申请日：2002-05-31
申请人： Masayoshi Saito , Yoshitaka Nakamura , Hidekazu Goto , Keizo Kawakita , Satoru Yamada , Toshihiro Sekiguchi , Isamu Asano , Yoshitaka Tadaki , Takuya Fukuda , Masayuki Suzuki , Tsuyoshi Tamaru , Naoki Fukuda , Hideo Aoki , Masayoshi Hirasawa
发明人： Masayoshi Saito , Yoshitaka Nakamura , Hidekazu Goto , Keizo Kawakita , Satoru Yamada , Toshihiro Sekiguchi , Isamu Asano , Yoshitaka Tadaki , Takuya Fukuda , Masayuki Suzuki , Tsuyoshi Tamaru , Naoki Fukuda , Hideo Aoki , Masayoshi Hirasawa
IPC分类号： H01L218242
CPC分类号： H01L21/76855 , H01L21/28518 , H01L21/31604 , H01L21/76801 , H01L21/76828 , H01L21/76837 , H01L21/76843 , H01L21/76856 , H01L21/7687 , H01L27/10814 , H01L27/10885 , H01L27/10894 , H01L28/40
摘要： In a DRAM having a capacitor-over-bitline structure in which the capacitive insulating film of an information storing capacitive element C is formed of a high dielectric material such as Ta2O5 (tantalum oxide) film 46, the portions of bit lines BL and first-layer interconnect lines 23 to 26 of a peripheral circuit which are in contact with at least an underlying silicon oxide film 28 are formed of a W film, the bit lines BL and the interconnect lines 23 to 26 being arranged below the information storing capacitive element C, whereby the adhesion at the interface between the bit lines BL and the interconnect lines 23 to 26 and the silicon oxide film is improved in terms of high-temperature heat treatment to be performed when the capacitive insulating film is being formed.
摘要翻译：在具有电容器的位线结构的DRAM中，信息存储电容元件C的电容绝缘膜由诸如Ta 2 O 5（氧化钽）膜46的高电介质材料形成，位线BL和第一 - 与W膜形成的与外部电路至少底层的氧化硅膜28接触的层间布线23〜26，位线BL和布线23〜26配置在信息存储电容元件C的下方从而在形成电容绝缘膜时进行的高温热处理方面提高了位线BL与布线23〜26之间界面处的粘附性和氧化硅膜。

8. 发明授权

US06399438B2 Method of manufacturing semiconductor integrated circuit device having a capacitor 有权
标题翻译：具有电容器的半导体集成电路器件的制造方法
公开(公告)号：US06399438B2
公开(公告)日：2002-06-04
申请号：US09828201
申请日：2001-04-09
申请人： Masayoshi Saito , Yoshitaka Nakamura , Hidekazu Goto , Keizo Kawakita , Satoru Yamada , Toshihiro Sekiguchi , Isamu Asano , Yoshitaka Tadaki , Takuya Fukuda , Masayuki Suzuki , Tsuyoshi Tamaru , Naoki Fukuda , Hideo Aoki , Masayoshi Hirasawa
发明人： Masayoshi Saito , Yoshitaka Nakamura , Hidekazu Goto , Keizo Kawakita , Satoru Yamada , Toshihiro Sekiguchi , Isamu Asano , Yoshitaka Tadaki , Takuya Fukuda , Masayuki Suzuki , Tsuyoshi Tamaru , Naoki Fukuda , Hideo Aoki , Masayoshi Hirasawa
IPC分类号： H01L218242
CPC分类号： H01L21/76855 , H01L21/28518 , H01L21/31604 , H01L21/76801 , H01L21/76828 , H01L21/76837 , H01L21/76843 , H01L21/76856 , H01L21/7687 , H01L27/10814 , H01L27/10885 , H01L27/10894 , H01L28/40
摘要： In a DRAM having a capacitor-over-bitline structure in which the capacitive insulating film of an information storing capacitive element C is formed of a high dielectric material such as Ta2O5 (tantalum oxide) film 46, the portions of bit lines BL and first-layer interconnect lines 23 to 26 of a peripheral circuit which are in contact with at least an underlying silicon oxide film 28 are formed of a W film, the bit lines BL and the interconnect lines 23 to 26 being arranged below the information storing capacitive element C, whereby the adhesion at the interface between the bit lines BL and the interconnect lines 23 to 26 and the silicon oxide film is improved in terms of high-temperature heat treatment to be performed when the capacitive insulating film is being formed.
摘要翻译：在具有电容器的位线结构的DRAM中，信息存储电容元件C的电容绝缘膜由诸如Ta 2 O 5（氧化钽）膜46的高电介质材料形成，位线BL和第一 - 与W膜形成的与外部电路至少底层的氧化硅膜28接触的层间布线23〜26，位线BL和布线23〜26配置在信息存储电容元件C的下方从而在形成电容绝缘膜时进行的高温热处理方面提高了位线BL与布线23〜26之间界面处的粘附性和氧化硅膜。

9. 发明授权

US06255151B1 Semiconductor integrated circuit device and method of manufacturing same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US06255151B1
公开(公告)日：2001-07-03
申请号：US09209013
申请日：1998-12-11
申请人： Takuya Fukuda , Yuzuru Ohji , Nobuyoshi Kobayashi
发明人： Takuya Fukuda , Yuzuru Ohji , Nobuyoshi Kobayashi
IPC分类号： H01L21336
CPC分类号： H01L27/10894 , H01L21/31053 , H01L23/53228 , H01L27/10814 , H01L27/10882 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： A steplike offset between a memory cell array region and a peripheral circuit region, which is caused by a capacitor C, is reduced by an insulating film having a thickness substantially equal to the height of the capacitor C. Wiring or interconnection grooves are defined in the neighborhood of the surface of an insulating film whose surface is flattened by a CMP method. Further, connecting holes are defined in lower portions of the bottom faces of the interconnection grooves respectively. Second layer interconnections containing copper are formed within the interconnection grooves, and connecting portions containing copper are formed within the connecting holes. The second layer interconnections and first layer interconnections are connected to each other by the connecting portions whose lengths are shortened. The second layer interconnections and the connecting portions are integrally formed by a damascene method using the CMP method.
摘要翻译：由电容器C引起的存储单元阵列区域和外围电路区域之间的阶梯状偏移通过具有基本上等于电容器C的高度的厚度的绝缘膜而减小。布线或互连槽限定在通过CMP方法将表面平坦化的绝缘膜的表面附近。此外，连接孔分别限定在互连槽的底面的下部。包含铜的第二层互连形成在互连槽内，并且在连接孔内形成包含铜的连接部分。第二层互连和第一层互连通过缩短长度的连接部彼此连接。第二层互连和连接部分通过使用CMP方法的镶嵌方法一体地形成。

10. 发明授权

US06833331B2 Method of manufacturing semiconductor integrated circuit device having insulating film formed from liquid substance containing polymer of silicon, oxygen, and hydrogen 失效
标题翻译：具有由含有硅，氧和氢的聚合物的液体物质形成的绝缘膜的半导体集成电路器件的制造方法
公开(公告)号：US06833331B2
公开(公告)日：2004-12-21
申请号：US10303935
申请日：2002-11-26
申请人： Masayoshi Saito , Katsuhiko Hotta , Masayoshi Hirasawa , Masayuki Kojima , Hiroyuki Uchiyama , Hiroyuki Maruyama , Takuya Fukuda
发明人： Masayoshi Saito , Katsuhiko Hotta , Masayoshi Hirasawa , Masayuki Kojima , Hiroyuki Uchiyama , Hiroyuki Maruyama , Takuya Fukuda
IPC分类号： H01L2131
CPC分类号： H01L21/3124 , H01L21/02164 , H01L21/02216 , H01L21/02282 , H01L21/02337 , H01L21/3125 , H01L21/76802 , H01L21/76814 , H01L21/76816 , H01L21/76825 , H01L21/76826 , H01L21/76828 , H01L21/76831 , H01L27/10814 , H01L27/10894
摘要： An SOG film 16 obtained by heat-treating a polysilazan type SOG film at high temperature of about 800° C. is used as a planarized insulating film to be formed on the gate electrode (9; see FIGS. 31 and 32) of a MISFET (Qs, Qn, Qp) A polysilazan SOG film (57) not subjected to such a heat treatment is used as interlayer insulating film arranged among upper wiring layers (54, 55, 56, 62, 63).
摘要翻译：使用通过在约800℃的高温下热处理聚硅氮烷型SOG膜获得的SOG膜16作为形成在MISFET的栅极（9;参见图31和32）上的平坦化绝缘膜）（Qs，Qn，Qp）将不进行这种热处理的聚硅氮烷SOG膜（57）用作布置在上布线层（54,55,56,62,63）中的层间绝缘膜。

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