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1. 发明申请

US20160225615A1 PRECURSORS FOR SILICON DIOXIDE GAP FILL 审中-公开
标题翻译：硅二氧化硅填料的前身
公开(公告)号：US20160225615A1
公开(公告)日：2016-08-04
申请号：US15093865
申请日：2016-04-08
申请人： Entegris, Inc.
发明人： William Hunks , Chongying Xu , Bryan C. Hendrix , Jeffrey F. Roeder , Steven M. Bilodeau , Weimin Li
IPC分类号： H01L21/02 , H01L29/06
CPC分类号： H01L21/02211 , H01L21/02123 , H01L21/02164 , H01L21/02216 , H01L21/02222 , H01L21/02263 , H01L21/31604 , H01L21/31608 , H01L29/0649
摘要： A full fill trench structure is described, including a microelectronic device substrate having a high aspect ratio trench therein and filled with silicon dioxide of a substantially void-free character and substantially uniform density throughout its bulk mass. A method of manufacturing a semiconductor product also is described, involving use of specific silicon precursor compositions for forming substantially void-free and substantially uniform density silicon dioxide material in the trench. The precursor fill composition may include silicon and germanium, to produce a microelectronic device structure including a GeO2/SiO2 trench fill material. A suppressor component may be employed in the precursor fill composition, to eliminate or minimize seam formation in the cured trench fill material.
摘要翻译：描述了一种全填充沟槽结构，其包括其中具有高纵横比沟槽的微电子器件衬底，并填充了其整个整体质量基本上无空隙特征和基本均匀密度的二氧化硅。还描述了制造半导体产品的方法，其涉及使用特定的硅前体组合物，用于在沟槽中形成基本上无空隙且基本均匀的密度二氧化硅材料。前体填充组合物可以包括硅和锗，以产生包括GeO 2 / SiO 2沟槽填充材料的微电子器件结构。可以在前体填充组合物中使用抑制剂组分，以消除或最小化固化沟槽填充材料中的接缝形成。

2. 发明授权

US09337054B2 Precursors for silicon dioxide gap fill 有权
标题翻译：二氧化硅填充前体
公开(公告)号：US09337054B2
公开(公告)日：2016-05-10
申请号：US12665929
申请日：2008-06-27
申请人： William Hunks , Chongying Xu , Bryan C. Hendrix , Jeffrey F. Roeder , Steven M. Bilodeau , Weimin Li
发明人： William Hunks , Chongying Xu , Bryan C. Hendrix , Jeffrey F. Roeder , Steven M. Bilodeau , Weimin Li
IPC分类号： H01L21/316 , H01L21/02
CPC分类号： H01L21/02211 , H01L21/02123 , H01L21/02164 , H01L21/02216 , H01L21/02222 , H01L21/02263 , H01L21/31604 , H01L21/31608 , H01L29/0649
摘要： A full fill trench structure is described, including a microelectronic device substrate having a high aspect ratio trench therein and filled with silicon dioxide of a substantially void-free character and substantially uniform density throughout its bulk mass. A method of manufacturing a semiconductor product also is described, involving use of specific silicon precursor compositions for forming substantially void-free and substantially uniform density silicon dioxide material in the trench. The precursor fill composition may include silicon and germanium, to produce a microelectronic device structure including a GeO2/SiO2 trench fill material. A suppressor component may be employed in the precursor fill composition, to eliminate or minimize seam formation in the cured trench fill material.
摘要翻译：描述了一种全填充沟槽结构，其包括其中具有高纵横比沟槽的微电子器件衬底，并填充了其整个整体质量基本上无空隙特征和基本均匀密度的二氧化硅。还描述了制造半导体产品的方法，其涉及使用特定的硅前体组合物，用于在沟槽中形成基本上无空隙且基本均匀的密度二氧化硅材料。前体填充组合物可以包括硅和锗，以产生包括GeO 2 / SiO 2沟槽填充材料的微电子器件结构。可以在前体填充组合物中使用抑制剂组分，以消除或最小化固化沟槽填充材料中的接缝形成。

3. 发明申请

US20150214042A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SUBSTRATE PROCESSING APPARATUS 有权
标题翻译：制造半导体器件和衬底加工设备的方法
公开(公告)号：US20150214042A1
公开(公告)日：2015-07-30
申请号：US14681065
申请日：2015-04-07
申请人： Hitachi Kokusai Electric Inc.
发明人： Ryota SASAJIMA , Yoshiro HIROSE , Yosuke OTA , Naonori AKAE , Kojiro YOKOZAWA
IPC分类号： H01L21/02 , H01L21/321
CPC分类号： H01L21/0223 , C23C16/402 , C23C16/45546 , C23C16/54 , C23C16/56 , H01L21/02164 , H01L21/02178 , H01L21/02181 , H01L21/02186 , H01L21/02189 , H01L21/02238 , H01L21/02244 , H01L21/0228 , H01L21/02337 , H01L21/3141 , H01L21/31608 , H01L21/31645 , H01L21/32051 , H01L21/321
摘要： Provided is a method of manufacturing a semiconductor device. The method includes: (a) forming an oxide film having a predetermined thickness on a substrate by alternately repeating: (a-1) forming a layer containing a predetermined element on the substrate by supplying a source gas containing the predetermined element into a process vessel accommodating the substrate and exhausting the source gas from the process vessel; and (a-2) changing the layer containing the predetermined element into an oxide layer by supplying an oxygen-containing gas and an hydrogen-containing gas into the process vessel, wherein inside of the process vessel is under a heated atmosphere having a pressure lower than an atmospheric pressure; and exhausting the oxygen-containing gas and the hydrogen-containing gas from the process vessel; and (b) modifying the oxide film formed on the substrate by supplying the oxygen-containing gas and the hydrogen-containing gas into the process vessel, wherein the inside of the process vessel is under the heated atmosphere having the pressure lower than the atmospheric pressure, and exhausting the oxygen-containing gas and the hydrogen-containing gas from the process vessel.
摘要翻译：提供一种制造半导体器件的方法。该方法包括：（a）通过交替地重复以下步骤：（a-1）在基板上形成具有预定厚度的氧化膜，该方法包括：（a-1）在基板上形成含有预定元素的层，容纳衬底并从处理容器排出源气体; 和（a-2）通过向处理容器供给含氧气体和含氢气体将含有预定元素的层改变为氧化物层，其中处理容器内部处于低压下的加热气氛比大气压; 并从处理容器排出含氧气体和含氢气体; 和（b）通过向处理容器供给含氧气体和含氢气体来改性在基板上形成的氧化膜，其中处理容器的内部处于压力低于大气压的加热气氛下并从处理容器排出含氧气体和含氢气体。

4. 发明授权

US08994189B2 Semiconductor structures including tight pitch contacts 有权
标题翻译：包括紧密节距触点的半导体结构
公开(公告)号：US08994189B2
公开(公告)日：2015-03-31
申请号：US14275414
申请日：2014-05-12
申请人： Micron Technology, Inc.
发明人： Luan C. Tran
IPC分类号： H01L23/48 , H01L21/02 , H01L21/033 , H01L21/311 , H01L21/314 , H01L21/316 , H01L21/768
CPC分类号： H01L21/76802 , H01L21/02164 , H01L21/0228 , H01L21/0337 , H01L21/0338 , H01L21/3086 , H01L21/3088 , H01L21/31144 , H01L21/3141 , H01L21/31608 , H01L21/7681 , H01L21/76816 , H01L21/76877 , H01L23/481 , H01L27/108 , H01L2924/0002 , H01L2924/00
摘要： Methods of fabricating semiconductor structures incorporating tight pitch contacts aligned with active area features and of simultaneously fabricating self-aligned tight pitch contacts and conductive lines using various techniques for defining patterns having sublithographic dimensions. Semiconductor structures having tight pitch contacts aligned with active area features and, optionally, aligned conductive lines are also disclosed, as are semiconductor structures with tight pitch contact holes and aligned trenches for conductive lines.
摘要翻译：制造具有与有源区域特征对准的紧密节距触点的半导体结构的方法，并且使用用于限定具有亚光刻尺寸的图案的各种技术同时制造自对准的紧密节距触点和导线。还公开了具有与有源区域特征对准的紧密节距触点的半导体结构以及可选地对齐的导线，半导体结构具有紧密的节距接触孔和用于导线的对准的沟槽。

5. 发明授权

US08667928B2 Semiconductor processing 有权
标题翻译：半导体处理
公开(公告)号：US08667928B2
公开(公告)日：2014-03-11
申请号：US13086133
申请日：2011-04-13
申请人： Shyam Surthi
发明人： Shyam Surthi
IPC分类号： H01L21/00
CPC分类号： C23C16/45546 , C23C16/45578 , C23C16/46 , H01L21/02164 , H01L21/02211 , H01L21/0228 , H01L21/3141 , H01L21/31608
摘要： Embodiments of the present disclosure include semiconductor processing methods and systems. One method includes forming a material layer on a semiconductor substrate by exposing a deposition surface of the substrate to at least a first and a second reactant sequentially introduced into a reaction chamber having an associated process temperature. The method includes removing residual first reactant from the chamber after introduction of the first reactant, removing residual second reactant from the chamber after introduction of the second reactant, and establishing a temperature differential substantially between an edge of the substrate and a center of the substrate via a purge process.
摘要翻译：本公开的实施例包括半导体处理方法和系统。一种方法包括在半导体衬底上形成材料层，方法是将衬底的沉积表面暴露于至少第一和第二反应物，该第一和第二反应物依次导入具有相关工艺温度的反应室中。该方法包括在引入第一反应物之后从室中除去残留的第一反应物，在引入第二反应物之后从室中除去残留的第二反应物，并且基本上在衬底的边缘和衬底的中心之间建立温差清洗过程。

6. 发明申请

US20140017904A1 FLOWABLE FILM DIELECTRIC GAP FILL PROCESS 有权
标题翻译：流动膜电介质膜填充工艺
公开(公告)号：US20140017904A1
公开(公告)日：2014-01-16
申请号：US13935398
申请日：2013-07-03
申请人： Novellus Systems, Inc.
发明人： Vishal GAURI , Raashina HUMAYUN , Chi-I LANG , Judy H. HUANG , Michael BARNES , Sunil SHANKER
IPC分类号： H01L21/31
CPC分类号： H01L21/31 , C23C16/045 , C23C16/401 , C23C16/56 , H01L21/02164 , H01L21/02271 , H01L21/0234 , H01L21/3121 , H01L21/3122 , H01L21/31608 , H01L21/76224
摘要： Methods of this invention relate to filling gaps on substrates with a solid dielectric material by forming a flowable film in the gap. The flowable film provides consistent, void-free gap fill. The film is then converted to a solid dielectric material. In this manner gaps on the substrate are filled with a solid dielectric material. According to various embodiments, the methods involve reacting a dielectric precursor with an oxidant to form the dielectric material. In certain embodiments, the dielectric precursor condenses and subsequently reacts with the oxidant to form dielectric material. In certain embodiments, vapor phase reactants react to form a condensed flowable film.
摘要翻译：本发明的方法涉及通过在间隙中形成可流动的膜来填充具有固体电介质材料的衬底上的间隙。可流动膜提供一致的，无空隙的间隙填充。然后将膜转化成固体电介质材料。以这种方式，用固体电介质材料填充衬底上的间隙。根据各种实施方案，所述方法包括使电介质前体与氧化剂反应以形成电介质材料。在某些实施方案中，电介质前体冷凝并随后与氧化剂反应以形成电介质材料。在某些实施方案中，气相反应物反应形成冷凝的可流动的膜。

7. 发明申请

US20140015011A1 Novel Fabrication Technique for High Frequency, High Power Group III Nitride Electronic Devices 审中-公开
标题翻译：高频，大功率III组氮化物电子器件的新型制作技术
公开(公告)号：US20140015011A1
公开(公告)日：2014-01-16
申请号：US13933668
申请日：2013-07-02
申请人： M. Asif Khan , Vinod Adivarahan
发明人： M. Asif Khan , Vinod Adivarahan
IPC分类号： H01L29/778
CPC分类号： H01L29/7783 , H01L21/02057 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/02211 , H01L21/02274 , H01L21/0228 , H01L21/30621 , H01L21/3141 , H01L21/31608 , H01L21/3185 , H01L29/2003 , H01L29/66462
摘要： Fabrication methods of a high frequency (sub-micron gate length) operation of AlInGaN/InGaN/GaN MOS-DHFET, and the HFET device resulting from the fabrication methods, are generally disclosed. The method of forming the HFET device generally includes a novel double-recess etching and a pulsed deposition of an ultra-thin, high-quality silicon dioxide layer as the active gate-insulator. The methods of the present invention can be utilized to form any suitable field effect transistor (FET), and are particular suited for forming high electron mobility transistors (HEMT).
摘要翻译：通常公开了AlInGaN / InGaN / GaN MOS-DHFET的高频（亚微米栅极长度）操作和由制造方法产生的HFET器件的制造方法。形成HFET器件的方法通常包括新颖的双凹槽蚀刻和作为有源栅绝缘体的超薄，高质量二氧化硅层的脉冲沉积。本发明的方法可用于形成任何合适的场效应晶体管（FET），并且特别适于形成高电子迁移率晶体管（HEMT）。

8. 发明授权

US08557716B2 Semiconductor device manufacturing method and substrate processing apparatus 有权
标题翻译：半导体装置的制造方法和基板处理装置
公开(公告)号：US08557716B2
公开(公告)日：2013-10-15
申请号：US12707008
申请日：2010-02-17
申请人： Norikazu Mizuno
发明人： Norikazu Mizuno
IPC分类号： H01L21/31
CPC分类号： H01L21/02164 , H01L21/02211 , H01L21/0228 , H01L21/3141 , H01L21/31608 , H01L21/67109
摘要： A thin film can be formed on a substrate at a low temperature with a practicable film-forming rate. There is provided a semiconductor device manufacturing method for forming an oxide or nitride film on a substrate. The method comprises: exposing the substrate to a source gas; exposing the substrate to a modification gas comprising an oxidizing gas or a nitriding gas, wherein an atom has electronegativity different from that of another atom in molecules of the oxidizing gas or the nitriding gas; and exposing the substrate to a catalyst. The catalyst has acid dissociation constant pKa in a range from 5 to 7, but a pyridine is not used as the catalyst.
摘要翻译：可以在低温下以可行的成膜速度在基板上形成薄膜。提供了一种用于在基板上形成氧化物或氮化物膜的半导体器件制造方法。该方法包括：将衬底暴露于源气体; 将衬底暴露于包含氧化气体或氮化气体的改性气体中，其中原子在氧化气体或氮化气体的分子中具有与另一原子的电负性不同的电负性; 并将基底暴露于催化剂。催化剂的酸解离常数pKa在5〜7的范围内，但吡啶不用作催化剂。

9. 发明授权

US08481422B2 Prevention and reduction of solvent and solution penetration into porous dielectrics using a thin barrier layer 失效
标题翻译：使用薄的阻挡层防止和减少溶剂和溶液渗透到多孔电介质中
公开(公告)号：US08481422B2
公开(公告)日：2013-07-09
申请号：US13455299
申请日：2012-04-25
申请人： Kelvin Chan , Khaled A. Elsheref , Alexandros T. Demos , Mei-Yee Shek , Lipan Li , Li-Qun Xia , Kang Sub Yim
发明人： Kelvin Chan , Khaled A. Elsheref , Alexandros T. Demos , Mei-Yee Shek , Lipan Li , Li-Qun Xia , Kang Sub Yim
IPC分类号： H01L21/4763
CPC分类号： H01L21/3141 , H01L21/02164 , H01L21/02216 , H01L21/02274 , H01L21/0228 , H01L21/31105 , H01L21/31116 , H01L21/31608 , H01L21/76814 , H01L21/76831
摘要： A method and apparatus for treating a substrate is provided. A porous dielectric layer is formed on the substrate. In some embodiments, the dielectric may be capped by a dense dielectric layer. The dielectric layers are patterned, and a dense dielectric layer deposited conformally over the substrate. The dense conformal dielectric layer seals the pores of the porous dielectric layer against contact with species that may infiltrate the pores. The portion of the dense conformal pore-sealing dielectric layer covering the field region and bottom portions of the pattern openings is removed by directional selective etch.
摘要翻译：提供了一种处理基板的方法和装置。在基板上形成多孔介电层。在一些实施例中，电介质可以由致密的电介质层封盖。对电介质层进行图案化，并且将致密的电介质层保形地沉积在衬底上。密实的保形介电层密封多孔介电层的孔隙，防止与可能渗入孔隙的物质接触。通过方向选择性蚀刻去除覆盖图案开口的场区域和底部的稠密共形孔隙电介质层的部分。

10. 发明授权

US08415258B2 Method of manufacturing semiconductor device, method of processing substrate and substrate processing apparatus 有权
标题翻译：半导体装置的制造方法，基板的处理方法及基板处理装置
公开(公告)号：US08415258B2
公开(公告)日：2013-04-09
申请号：US13286314
申请日：2011-11-01
申请人： Naonori Akae , Yoshiro Hirose , Yushin Takasawa , Yosuke Ota , Ryota Sasajima
发明人： Naonori Akae , Yoshiro Hirose , Yushin Takasawa , Yosuke Ota , Ryota Sasajima
IPC分类号： H01L21/31
CPC分类号： H01L21/31608 , C23C16/32 , C23C16/34 , C23C16/401 , C23C16/45527 , C23C16/45546 , C23C16/45578 , H01L21/0214 , H01L21/02164 , H01L21/0217 , H01L21/02178 , H01L21/02181 , H01L21/02189 , H01L21/0228 , H01L21/3141 , H01L21/3145 , H01L21/3185
摘要： Provided is a method of manufacturing a semiconductor device. The method includes: loading a substrate into a process vessel; performing a process to form an film on the substrate by alternately repeating: (a) forming a layer containing an element on the substrate by supplying at least two types of source gases into the process vessel, each of the at least two types of source gases containing the element, and (b) changing the layer containing the element by supplying reaction gas into the process vessel, the reaction gas being different from the at least two types of source gases; and unloading the processed substrate from the process vessel.
摘要翻译：提供一种制造半导体器件的方法。该方法包括：将基底装载到处理容器中; 通过交替地重复以下步骤来执行在衬底上形成膜的工艺：（a）通过将至少两种类型的源气体供应到处理容器中，在衬底上形成含有元素的层，所述至少两种类型的源气体（b）通过将反应气体供应到处理容器中来改变含有元素的层，所述反应气体与所述至少两种源气体不同; 并从处理容器卸载经处理的基材。

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