专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

11. 发明授权

US06442068B1 Non-volatile memory with functional capability of burst mode read and page mode read during suspension of an operation of electrical alteration 有权
标题翻译：在电气变更操作暂停期间读取突发模式读取和页面模式的功能性能的非易失性存储器
公开(公告)号：US06442068B1
公开(公告)日：2002-08-27
申请号：US09619589
申请日：2000-07-19
申请人： Simone Bartoli , Lorenzo Bedarida , Mauro Sali , Antonio Russo
发明人： Simone Bartoli , Lorenzo Bedarida , Mauro Sali , Antonio Russo
IPC分类号： G11C1134
CPC分类号： G11C16/26 , G11C16/10 , G11C2216/20
摘要： An electrically alterable semiconductor memory includes at least two memory sectors the content of which is individually alterable, and a control circuit for controlling operations of electrical alteration of the content of the memory, permitting the selective execution of an operation of electrical alteration of the content of one of the memory sectors with the possibility of suspending the execution to permit read access to the other of the memory sectors. The control circuit is also capable of permitting, during the suspension, an operation of burst mode or page mode reading of the content of the other memory sector.
摘要翻译：电可改变的半导体存储器包括至少两个存储器扇区，其内容是可单独改变的;以及控制电路，用于控制存储器内容的电气改变的操作，允许选择性地执行对内容的电气改变的操作其中一个存储器扇区具有暂停执行以允许对另一个存储器扇区的读取访问的可能性。控制电路还能够在暂停期间允许对其他存储器扇区的内容的突发模式或页面模式读取的操作。

12. 发明授权

US06353350B1 Pulse generator independent of supply voltage 有权
标题翻译：脉冲发生器独立于电源电压
公开(公告)号：US06353350B1
公开(公告)日：2002-03-05
申请号：US09721502
申请日：2000-11-22
申请人： Lorenzo Bedarida , Simone Bartoli , Luigi Bettini
发明人： Lorenzo Bedarida , Simone Bartoli , Luigi Bettini
IPC分类号： H03K300
CPC分类号： G11C7/04 , G11C7/06 , G11C7/22 , G11C2207/065 , H03K3/011 , H03K3/355 , H03K5/04
摘要： A pulse generator of a type that includes at least one current mirror connected between first and second voltage references and to at least one initiation terminal receiving a pulsive-type initiating signal, connected to a load terminal receiving a load signal, and connected to an output terminal providing an output signal. The pulse generator further includes at least one logic gate having one input terminal connected to an internal control circuit node of the current mirror, having another input terminal connected to receive the initiating signal, and having an output terminal connected to the output terminal of the pulse generator; at least one regulator circuit connected between the current mirror and the second voltage reference and feedback connected to the output terminal; and at least one conductive-type transistor connected between the current mirror and the regulator circuit; the output terminal of the pulse generator delivering a retarded pulsive-type output signal that is independent of the supply voltage and exhibits the same dependency on temperature as the regulator circuit.
摘要翻译：一种类型的脉冲发生器，包括连接在第一和第二电压基准之间的至少一个电流镜和连接到接收负载信号的负载终端并连接到输出的至少一个起始终端的起始终端终端提供输出信号。脉冲发生器还包括至少一个逻辑门，其中一个输入端连接到电流镜的内部控制电路节点，其另一输入端连接以接收起始信号，并且具有连接到脉冲的输出端的输出端发电机; 连接在电流镜与第二电压基准之间的至少一个调节器电路和连接到输出端的反馈; 以及连接在电流镜和调节器电路之间的至少一个导电型晶体管; 脉冲发生器的输出端子输出与电源电压无关的延迟脉动型输出信号，并且对温度表现出与调节器电路相同的依赖性。

13. 发明授权

US06349059B1 Method for reading data from a non-volatile memory device with autodetect burst mode reading and corresponding reading circuit 失效
标题翻译：从具有自动检测突发模式读取的非易失性存储器件读取数据的方法和相应的读取电路
公开(公告)号：US06349059B1
公开(公告)日：2002-02-19
申请号：US09716746
申请日：2000-11-20
申请人： Simone Bartoli , Antonio Geraci , Mauro Sali , Lorenzo Bedarida
发明人： Simone Bartoli , Antonio Geraci , Mauro Sali , Lorenzo Bedarida
IPC分类号： G11C1604
CPC分类号： G11C7/1033 , G11C7/1045 , G11C7/1072
摘要： A method for reading data from an integrated electronic memory device including a non-volatile memory matrix includes supplying the memory with an address of a memory location where a reading is to be effected, accessing the memory matrix in a random read mode, supplying the memory with a clock signal and an address acknowledge signal (LAN), detecting a request for burst read mode access, and starting the burst reading as the clock signal shows a rising edge. A related circuit is also provided.
摘要翻译：一种用于从包括非易失性存储器矩阵的集成电子存储器件读取数据的方法包括向存储器提供要进行读取的存储器位置的地址，以随机读取模式访问存储器矩阵，提供存储器具有时钟信号和地址确认信号（LAN），检测对突发读取模式存取的请求，以及当时钟信号显示上升沿时启动突发读取。还提供了相关的电路。

14. 发明授权

US06320361B2 Buffer device with dual supply voltage for low supply voltage applications 失效
标题翻译：用于低电源电压应用的双电源电压缓冲器件
公开(公告)号：US06320361B2
公开(公告)日：2001-11-20
申请号：US09736984
申请日：2000-12-13
申请人： Vincenzo Dima , Lorenzo Bedarida , Antonino Geraci , Simone Bartoli
发明人： Vincenzo Dima , Lorenzo Bedarida , Antonino Geraci , Simone Bartoli
IPC分类号： G05F140
CPC分类号： G05F3/242
摘要： An output buffer device having first and second supply voltage references, the first voltage reference being lower in value than the second voltage reference. The output buffer device includes first and second complementary MOS transistors, which transistors are connected in series together between one of the supply voltage references and a further voltage reference, have gate terminals connected together and to an input terminal of this buffer device, and have drain terminals connected together and to an output terminal of the buffer device. Advantageously, the first transistor is connected to the first supply voltage reference. Furthermore, the output buffer device comprises at least one additional drive MOS transistor of the same type as the first MOS transistor and placed between the second supply voltage reference and the output terminal of the buffer device.
摘要翻译：一种具有第一和第二电源电压基准的输出缓冲器装置，该第一参考电压值低于第二电压基准。输出缓冲器件包括第一和第二互补MOS晶体管，这些晶体管串联连接在一个电源电压基准和另一个电压基准之间，栅极端子连接在一起并连接到该缓冲器件的输入端，并且具有漏极连接在一起的端子和缓冲器的输出端子。有利地，第一晶体管连接到第一电源电压基准。此外，输出缓冲器件包括与第一MOS晶体管相同类型的至少一个额外的驱动MOS晶体管，并且放置在第二电源电压基准和缓冲器件的输出端之间。

15. 发明授权

US5994948A CMOS twin-tub negative voltage switching architecture 失效
标题翻译： CMOS双槽负压开关架构
公开(公告)号：US5994948A
公开(公告)日：1999-11-30
申请号：US921930
申请日：1997-08-27
申请人： Simone Bartoli , Antonio Russo , Mauro Luigi Sali
发明人： Simone Bartoli , Antonio Russo , Mauro Luigi Sali
IPC分类号： G11C16/30 , G05F1/10
CPC分类号： G11C16/30
摘要： A CMOS twin-tub negative voltage switching architecture is for a non-volatile memory device and includes a negative voltage multiplier for generating a increased voltage value starting from a single main power supply. A voltage regulator feedback is connected to the voltage multiplier for regulating the generated negative voltage value; and a plurality of independent switch circuits each one receiving as an input the negative voltage value and producing as an output a predetermined local negative voltage.
摘要翻译： CMOS双槽负电压开关结构用于非易失性存储器件，并且包括用于从单个主电源开始产生增加的电压值的负电压倍增器。电压调节器反馈连接到电压倍增器，用于调节产生的负电压值; 以及多个独立的开关电路，每个独立的开关电路每个接收负电压值作为输入，并产生预定的局部负电压作为输出。

16. 发明申请

US20140293707A1 Erase Techniques and Circuits Therefor for Non-Volatile Memory Devices 有权
标题翻译：用于非易失性存储器件的擦除技术及其电路
公开(公告)号：US20140293707A1
公开(公告)日：2014-10-02
申请号：US14227676
申请日：2014-03-27
申请人： Vincenzo Ferragina , Stefano Surico , Giuseppe Moioli , Simone Bartoli
发明人： Vincenzo Ferragina , Stefano Surico , Giuseppe Moioli , Simone Bartoli
IPC分类号： G11C16/34
CPC分类号： G11C16/3445 , G11C16/0483 , G11C16/16 , G11C16/3418
摘要： Disclosed herein is a method that comprises applying a first voltage to a memory cell, applying again the first voltage to the memory cell when the memory cell have not been shifted to an erased condition, and applying a second voltage to the memory cell when the memory cell have not still been shifted to an erased condition, the second voltage being higher than the first voltage.
摘要翻译：本文公开了一种方法，其包括向存储器单元施加第一电压，当存储器单元未被移位到擦除状态时再次将第一电压施加到存储器单元，以及当存储器向存储器单元施加第二电压时，单元还没有被移动到擦除状态，第二电压高于第一电压。

17. 发明申请

US20080170455A1 Compensated current offset in a sensing circuit 有权
标题翻译：感测电路中的补偿电流偏移
公开(公告)号：US20080170455A1
公开(公告)日：2008-07-17
申请号：US11652742
申请日：2007-01-12
申请人： Lorenzo Bedarida , Gabriele Pelli , Simone Bartoli , Mauro Chinosi
发明人： Lorenzo Bedarida , Gabriele Pelli , Simone Bartoli , Mauro Chinosi
IPC分类号： G11C7/08
CPC分类号： G11C7/062 , G11C7/02 , G11C7/067 , G11C16/26 , G11C2207/063
摘要： A sensing circuit with current offset functionality. In one embodiment, the sensing circuit includes a memory circuit having a first offset circuit operative to offset a first current. The sensing circuit also includes a reference circuit coupled to the memory circuit, where the reference circuit includes a second offset circuit operative to offset a second current. The sensing circuit also includes a compare circuit coupled to the memory circuit and the reference circuit, where the compare circuit determines the state of a memory cell based on first current and the second current. According to the system disclosed herein, the first and second offset circuits optimize the performance of the sensing circuit and prevent errors when determining the state of the memory cell.
摘要翻译：具有电流偏移功能的感测电路。在一个实施例中，感测电路包括存储器电路，该存储器电路具有可操作以偏移第一电流的第一偏移电路。感测电路还包括耦合到存储器电路的参考电路，其中参考电路包括可操作以偏移第二电流的第二偏移电路。感测电路还包括耦合到存储器电路和参考电路的比较电路，其中比较电路基于第一电流和第二电流确定存储器单元的状态。根据本文公开的系统，第一和第二偏移电路优化感测电路的性能并且在确定存储器单元的状态时防止错误。

18. 发明申请

US20080144379A1 IMPLEMENTATION OF COLUMN REDUNDANCY FOR A FLASH MEMORY WITH A HIGH WRITE PARALLELISM 有权
标题翻译：实现具有高写并发性的闪存存储器的冗余冗余
公开(公告)号：US20080144379A1
公开(公告)日：2008-06-19
申请号：US11611452
申请日：2006-12-15
申请人： Simone Bartoli , Stefano Surico , Andrea Sacco , Maria Mostola
发明人： Simone Bartoli , Stefano Surico , Andrea Sacco , Maria Mostola
IPC分类号： G11C16/06
CPC分类号： G11C29/82 , G11C29/806 , G11C29/846
摘要： A redundant memory array has r columns of redundant memory cells, r redundant senses, and a redundant column decoder. Redundant address registers store addresses of defective regular memory cells. Redundant latches are provided in n groups of r latches. Redundancy comparison logic compares addresses of defective regular memory cells with an external input address. If the comparison is true, what is provided is: a DISABLE_LOAD signal to disable the regular senses for one of the n groups of m columns, an ENABLE_LATCH signal to one of the n groups of m columns to disables corresponding regular senses, and one or r REDO signals to a respective one of the r redundant latches in one of the n groups that is disabled. The selected one of the redundant latches activates one of the r redundant senses to access a redundant column.
摘要翻译：冗余存储器阵列具有r列的冗余存储器单元，r冗余感测器和冗余列解码器。冗余地址寄存器存储有缺陷的常规存储单元的地址。在n组r个锁存器中提供冗余锁存器。冗余比较逻辑将缺陷常规存储单元的地址与外部输入地址进行比较。如果比较是真的，提供的是：DISABLE_LOAD信号，用于禁用n列m列中的一个的常规感测，将一个ENABLE_LATCH信号分配给m列的n组中的一组，以禁用相应的常规感官，以及其中之一 r REDO信号到禁用的n个组之一的r个冗余锁存器中的相应一个。所选的一个冗余锁存器激活r个冗余感测之一以访问冗余列。

19. 发明授权

US07283396B2 System and method for matching resistance in a non-volatile memory 有权
标题翻译：用于在非易失性存储器中匹配电阻的系统和方法
公开(公告)号：US07283396B2
公开(公告)日：2007-10-16
申请号：US11193924
申请日：2005-07-28
申请人： Lorenzo Bedarida , Andrea Sacco , Giorgio Oddone , Simone Bartoli
发明人： Lorenzo Bedarida , Andrea Sacco , Giorgio Oddone , Simone Bartoli
IPC分类号： G11C16/06
CPC分类号： G11C16/26
摘要： A method and system for approximating resistance in a non-volatile memory has a memory matrix. The memory matrix has a plurality of memory cells and a plurality of memory source lines that are coupled to the plurality of memory cells. A reference matrix is coupled to the memory matrix and has a reference cell. A logic generator is coupled to the reference matrix and is configured to generate an approximation, at the reference cell, of a resistance between a selected one of the plurality of memory cells and at least one of the plurality of memory source lines.
摘要翻译：用于近似非易失性存储器中的电阻的方法和系统具有存储器矩阵。存储矩阵具有耦合到多个存储单元的多个存储器单元和多个存储器源极线。参考矩阵耦合到存储器矩阵并具有参考单元。逻辑发生器耦合到参考矩阵，并被配置为在参考单元处产生多个存储器单元中的所选择的一个与多个存储器源极线中的至少一个之间的电阻的近似。

20. 发明申请

US20070076476A1 Method and system for regulating a program voltage value during multilevel memory device programming 有权
标题翻译：用于在多级存储器件编程期间调节编程电压值的方法和系统
公开(公告)号：US20070076476A1
公开(公告)日：2007-04-05
申请号：US11635160
申请日：2006-12-07
申请人： Massimiliano Frulio , Simone Bartoli , Davide Manfre' , Andrea Sacco
发明人： Massimiliano Frulio , Simone Bartoli , Davide Manfre' , Andrea Sacco
IPC分类号： G11C16/04
CPC分类号： G11C16/12 , G11C5/145 , G11C11/5628 , G11C16/04 , G11C16/30 , G11C16/3459 , G11C29/02 , G11C29/021 , G11C29/028
摘要： Regulating a program voltage value during multilevel memory device programming includes utilizing a program path duplicate in an output pump regulator circuit. Further, the output pump regulator circuit is utilized to provide a regulated program voltage for memory cell programming, the regulated program voltage correcting for a program path voltage drop.
摘要翻译：在多级存储器件编程期间调节编程电压值包括在输出泵调节器电路中使用程序路径副本。此外，输出泵调节器电路用于为存储器单元编程提供调节的编程电压，用于编程路径电压降的调节的编程电压。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式