专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20060279988A1 System and method for matching resistance in a non-volatile memory 有权
标题翻译：用于在非易失性存储器中匹配电阻的系统和方法
公开(公告)号：US20060279988A1
公开(公告)日：2006-12-14
申请号：US11193924
申请日：2005-07-28
申请人： Lorenzo Bedarida , Andrea Sacco , Giorgio Oddone , Simone Bartoli
发明人： Lorenzo Bedarida , Andrea Sacco , Giorgio Oddone , Simone Bartoli
IPC分类号： G11C16/04
CPC分类号： G11C16/26
摘要： A method and system for approximating resistance in a non-volatile memory has a memory matrix. The memory matrix has a plurality of memory cells and a plurality of memory source lines that are coupled to the plurality of memory cells. A reference matrix is coupled to the memory matrix and has a reference cell. A logic generator is coupled to the reference matrix and is configured to generate an approximation, at the reference cell, of a resistance between a selected one of the plurality of memory cells and at least one of the plurality of memory source lines.
摘要翻译：用于近似非易失性存储器中的电阻的方法和系统具有存储器矩阵。存储矩阵具有耦合到多个存储单元的多个存储器单元和多个存储器源极线。参考矩阵耦合到存储器矩阵并具有参考单元。逻辑发生器耦合到参考矩阵，并被配置为在参考单元处产生多个存储器单元中的所选择的一个与多个存储器源极线中的至少一个之间的电阻的近似。

2. 发明授权

US07283396B2 System and method for matching resistance in a non-volatile memory 有权
标题翻译：用于在非易失性存储器中匹配电阻的系统和方法
公开(公告)号：US07283396B2
公开(公告)日：2007-10-16
申请号：US11193924
申请日：2005-07-28
申请人： Lorenzo Bedarida , Andrea Sacco , Giorgio Oddone , Simone Bartoli
发明人： Lorenzo Bedarida , Andrea Sacco , Giorgio Oddone , Simone Bartoli
IPC分类号： G11C16/06
CPC分类号： G11C16/26
摘要： A method and system for approximating resistance in a non-volatile memory has a memory matrix. The memory matrix has a plurality of memory cells and a plurality of memory source lines that are coupled to the plurality of memory cells. A reference matrix is coupled to the memory matrix and has a reference cell. A logic generator is coupled to the reference matrix and is configured to generate an approximation, at the reference cell, of a resistance between a selected one of the plurality of memory cells and at least one of the plurality of memory source lines.
摘要翻译：用于近似非易失性存储器中的电阻的方法和系统具有存储器矩阵。存储矩阵具有耦合到多个存储单元的多个存储器单元和多个存储器源极线。参考矩阵耦合到存储器矩阵并具有参考单元。逻辑发生器耦合到参考矩阵，并被配置为在参考单元处产生多个存储器单元中的所选择的一个与多个存储器源极线中的至少一个之间的电阻的近似。

3. 发明授权

US06873551B2 Apparatus and method for a configurable mirror fast sense amplifier 有权
标题翻译：一种可配置镜像快速读出放大器的装置和方法
公开(公告)号：US06873551B2
公开(公告)日：2005-03-29
申请号：US10622804
申请日：2003-07-18
申请人： Lorenzo Bedarida , Andrea Sacco , Monica Marziani
发明人： Lorenzo Bedarida , Andrea Sacco , Monica Marziani
IPC分类号： G11C7/06 , G11C7/14 , G11C16/06
CPC分类号： G11C7/14 , G11C7/062 , G11C2207/063
摘要： A configurable mirror sense amplifier system for flash memory having the following features. A power source generates a reference voltage. A plurality of transistors is biased at the reference voltage. The plurality of transistors is each coupled to a second transistor. Each of the plurality of transistors is also configured to provide a current for comparison with the flash memory. The reference voltage is internal, stable and independent from variations of a power supply or temperature. The plurality of transistors is in parallel with one another. A mirror transistor is coupled to the plurality of transistors. The plurality of transistors is configured so that at least one of at least one transistor is activated with a signal in order to provide the current for comparison to the flash memory. Also, the reference voltage may be modified in order to modify the current for comparison to the flash memory.
摘要翻译：一种用于闪存的可配置的镜像放大器系统，具有以下特征。电源产生参考电压。多个晶体管被偏置在参考电压。多个晶体管各自耦合到第二晶体管。多个晶体管中的每一个也被配置为提供用于与闪速存储器进行比较的电流。参考电压是内部的，稳定的，独立于电源或温度的变化。多个晶体管彼此并联。反射镜晶体管耦合到多个晶体管。多个晶体管被配置为使得至少一个晶体管中的至少一个被激活，以便提供用于与闪存相比较的电流。此外，可以修改参考电压以便修改用于与闪存存储器进行比较的电流。

4. 发明申请

US20060170490A1 Fast dynamic low-voltage current mirror with compensated error 有权
标题翻译：具有补偿误差的快速动态低压电流镜
公开(公告)号：US20060170490A1
公开(公告)日：2006-08-03
申请号：US11393153
申请日：2006-03-29
申请人： Lorenzo Bedarida , Danut Manea , Mirella Marsella , Andrea Sacco
发明人： Lorenzo Bedarida , Danut Manea , Mirella Marsella , Andrea Sacco
IPC分类号： G05F1/10
CPC分类号： G05F3/262
摘要： A current mirror comprising: current source; a first p-channel transistor having a source coupled to operating potential, and a gate and drain coupled to current source; a second p-channel transistor having a source coupled to operating potential, a gate coupled to gate of first p-channel transistor, and a drain; a zero-threshold p-channel transistor having a source coupled to drain of second p-channel transistor, a gate coupled to gate of first p-channel transistor, and a drain; a first n-channel transistor having a source coupled to ground, and a gate and drain coupled to drain of zero-threshold p-channel transistor; a second n-channel transistor having a source coupled to ground, a gate coupled to gate of first n-channel transistor, and a drain; and a zero-threshold n-channel transistor having a source coupled to drain of second n-channel transistor, a gate coupled to gate of first n-channel transistor, and a drain coupled to current-output node.
摘要翻译：电流镜，包括：电流源; 具有耦合到工作电位的源极的第一p沟道晶体管和耦合到电流源的栅极和漏极; 具有耦合到工作电位的源极的第二p沟道晶体管，耦合到第一p沟道晶体管的栅极的栅极和漏极; 零阈值p沟道晶体管，其具有耦合到第二p沟道晶体管的漏极的源极，耦合到第一p沟道晶体管的栅极的栅极和漏极; 第一n沟道晶体管，其具有耦合到地的源极，以及耦合到零阈值p沟道晶体管的漏极的栅极和漏极; 具有耦合到地的源极的第二n沟道晶体管，耦合到第一n沟道晶体管的栅极的栅极和漏极; 以及零阈值n沟道晶体管，其具有耦合到第二n沟道晶体管的漏极的源极，耦合到第一n沟道晶体管的栅极的栅极和耦合到电流输出节点的漏极。

5. 发明申请

US20050226051A1 Fast dynamic low-voltage current mirror with compensated error 有权
标题翻译：具有补偿误差的快速动态低压电流镜
公开(公告)号：US20050226051A1
公开(公告)日：2005-10-13
申请号：US11102031
申请日：2005-04-07
申请人： Lorenzo Bedarida , Danut Manea , Mirella Marsella , Andrea Sacco
发明人： Lorenzo Bedarida , Danut Manea , Mirella Marsella , Andrea Sacco
IPC分类号： G05F3/26 , G11C16/04
CPC分类号： G05F3/262
摘要： A current mirror comprising: a first current source; a first n-channel MOS transistor having a drain and a gate coupled to said current source and a source coupled to ground; a second n-channel MOS transistor having a drain, a gate coupled to said drain and said gate of said first n-channel MOS transistor, and a source coupled to ground; a third n-channel MOS transistor having a source coupled to said drain of said second n-channel MOS transistor, a gate, and a drain comprising an output-current node; a second current source; a p-channel MOS transistor having a drain coupled to ground, a source coupled to said second current source and said gate of said third n-channel MOS transistor, and a gate coupled to said drain and said gate of said first n-channel MOS transistor.
摘要翻译：一种电流镜，包括：第一电流源; 第一n沟道MOS晶体管，其具有耦合到所述电流源的漏极和栅极以及耦合到地的源极; 具有漏极的第二n沟道MOS晶体管，耦合到所述漏极的栅极和所述第一n沟道MOS晶体管的所述栅极以及耦合到地的源极; 第三n沟道MOS晶体管，具有耦合到所述第二n沟道MOS晶体管的所述漏极的源极，栅极和包括输出电流节点的漏极; 第二个电流源; 具有耦合到地的漏极的p沟道MOS晶体管，耦合到所述第二电流源和所述第三n沟道MOS晶体管的所述栅极的源极，以及耦合到所述第一n沟道MOS晶体管的所述漏极和所述栅极的栅极晶体管。

6. 发明授权

US06954102B2 Fast dynamic mirror sense amplifier with separate comparison equalization and evaluation paths 有权
标题翻译：快速动态镜像放大器，具有独立的比较均衡和评估路径
公开(公告)号：US06954102B2
公开(公告)日：2005-10-11
申请号：US10407640
申请日：2003-04-03
申请人： Lorenzo Bedarida , Andrea Sacco , Mirella Marsella , Massimiliano Frulio
发明人： Lorenzo Bedarida , Andrea Sacco , Mirella Marsella , Massimiliano Frulio
IPC分类号： G11C7/06 , G11C7/14 , G11C16/28 , G03F1/10
CPC分类号： G11C7/14 , G11C7/062 , G11C7/067 , G11C16/28 , G11C2207/063
摘要： A memory cell sensing circuit to sense data from a memory cell includes a reference memory cell coupled to pass a reference current. A sense amplifier has a first input and a second input coupled to a bias circuit of the data memory cell. A first mirror mirrors the reference current to a voltage coupled to the first input of the sense amplifier. A second mirror mirrors the reference current to a voltage coupled to the bias circuit of the data memory cell. A third mirror mirrors the reference current to a voltage coupled to the second input of the sense amplifier through a pass gate.
摘要翻译：用于感测来自存储器单元的数据的存储单元感测电路包括耦合以传递参考电流的参考存储单元。读出放大器具有耦合到数据存储单元的偏置电路的第一输入和第二输入。第一镜将参考电流反射到耦合到读出放大器的第一输入端的电压。第二镜将参考电流反射到耦合到数据存储单元的偏置电路的电压。第三反射镜将参考电流反射到通过传输门耦合到读出放大器的第二输入的电压。

7. 发明申请

US20080144379A1 IMPLEMENTATION OF COLUMN REDUNDANCY FOR A FLASH MEMORY WITH A HIGH WRITE PARALLELISM 有权
标题翻译：实现具有高写并发性的闪存存储器的冗余冗余
公开(公告)号：US20080144379A1
公开(公告)日：2008-06-19
申请号：US11611452
申请日：2006-12-15
申请人： Simone Bartoli , Stefano Surico , Andrea Sacco , Maria Mostola
发明人： Simone Bartoli , Stefano Surico , Andrea Sacco , Maria Mostola
IPC分类号： G11C16/06
CPC分类号： G11C29/82 , G11C29/806 , G11C29/846
摘要： A redundant memory array has r columns of redundant memory cells, r redundant senses, and a redundant column decoder. Redundant address registers store addresses of defective regular memory cells. Redundant latches are provided in n groups of r latches. Redundancy comparison logic compares addresses of defective regular memory cells with an external input address. If the comparison is true, what is provided is: a DISABLE_LOAD signal to disable the regular senses for one of the n groups of m columns, an ENABLE_LATCH signal to one of the n groups of m columns to disables corresponding regular senses, and one or r REDO signals to a respective one of the r redundant latches in one of the n groups that is disabled. The selected one of the redundant latches activates one of the r redundant senses to access a redundant column.
摘要翻译：冗余存储器阵列具有r列的冗余存储器单元，r冗余感测器和冗余列解码器。冗余地址寄存器存储有缺陷的常规存储单元的地址。在n组r个锁存器中提供冗余锁存器。冗余比较逻辑将缺陷常规存储单元的地址与外部输入地址进行比较。如果比较是真的，提供的是：DISABLE_LOAD信号，用于禁用n列m列中的一个的常规感测，将一个ENABLE_LATCH信号分配给m列的n组中的一组，以禁用相应的常规感官，以及其中之一 r REDO信号到禁用的n个组之一的r个冗余锁存器中的相应一个。所选的一个冗余锁存器激活r个冗余感测之一以访问冗余列。

8. 发明申请

US20070076476A1 Method and system for regulating a program voltage value during multilevel memory device programming 有权
标题翻译：用于在多级存储器件编程期间调节编程电压值的方法和系统
公开(公告)号：US20070076476A1
公开(公告)日：2007-04-05
申请号：US11635160
申请日：2006-12-07
申请人： Massimiliano Frulio , Simone Bartoli , Davide Manfre' , Andrea Sacco
发明人： Massimiliano Frulio , Simone Bartoli , Davide Manfre' , Andrea Sacco
IPC分类号： G11C16/04
CPC分类号： G11C16/12 , G11C5/145 , G11C11/5628 , G11C16/04 , G11C16/30 , G11C16/3459 , G11C29/02 , G11C29/021 , G11C29/028
摘要： Regulating a program voltage value during multilevel memory device programming includes utilizing a program path duplicate in an output pump regulator circuit. Further, the output pump regulator circuit is utilized to provide a regulated program voltage for memory cell programming, the regulated program voltage correcting for a program path voltage drop.
摘要翻译：在多级存储器件编程期间调节编程电压值包括在输出泵调节器电路中使用程序路径副本。此外，输出泵调节器电路用于为存储器单元编程提供调节的编程电压，用于编程路径电压降的调节的编程电压。

9. 发明授权

US07184311B2 Method and system for regulating a program voltage value during multilevel memory device programming 有权
标题翻译：用于在多级存储器件编程期间调节编程电压值的方法和系统
公开(公告)号：US07184311B2
公开(公告)日：2007-02-27
申请号：US11123754
申请日：2005-05-05
申请人： Massimiliano Frulio , Simone Bartoli , Davide Manfre′ , Andrea Sacco
发明人： Massimiliano Frulio , Simone Bartoli , Davide Manfre′ , Andrea Sacco
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C11/5628 , G11C7/04 , G11C16/04 , G11C16/12 , G11C16/30 , G11C29/021 , G11C29/028
摘要： Regulating a program voltage value during multilevel memory device programming includes utilizing a program path duplicate in an output pump regulator circuit. Further, the output pump regulator circuit is utilized to provide a regulated program voltage for memory cell programming, the regulated program voltage correcting for a program path voltage drop and compensating for temperature variation.
摘要翻译：在多级存储器件编程期间调节编程电压值包括在输出泵调节器电路中使用程序路径副本。此外，输出泵调节器电路用于提供用于存储器单元编程的调节编程电压，用于编程路径电压降的校准编程电压并补偿温度变化。

10. 发明授权

US07379338B2 Method and system for regulating a program voltage value during multilevel memory device programming 有权
标题翻译：用于在多级存储器件编程期间调节编程电压值的方法和系统
公开(公告)号：US07379338B2
公开(公告)日：2008-05-27
申请号：US11635160
申请日：2006-12-07
申请人： Massimiliano Frulio , Simone Bartoli , Davide Manfre′ , Andrea Sacco
发明人： Massimiliano Frulio , Simone Bartoli , Davide Manfre′ , Andrea Sacco
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/12 , G11C5/145 , G11C11/5628 , G11C16/04 , G11C16/30 , G11C16/3459 , G11C29/02 , G11C29/021 , G11C29/028
摘要： Regulating a program voltage value during multilevel memory device programming includes utilizing a program path duplicate in an output pump regulator circuit. Further, the output pump regulator circuit is utilized to provide a regulated program voltage for memory cell programming, the regulated program voltage correcting for a program path voltage drop.
摘要翻译：在多级存储器件编程期间调节编程电压值包括在输出泵调节器电路中使用程序路径副本。此外，输出泵调节器电路用于为存储器单元编程提供调节的编程电压，用于编程路径电压降的调节的编程电压。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式