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1. 发明授权

US07864557B2 Flexible OTP sector protection architecture for flash memories 有权
标题翻译：灵活的OTP扇区保护架构，用于闪存
公开(公告)号：US07864557B2
公开(公告)日：2011-01-04
申请号：US11529158
申请日：2006-09-28
申请人： Riccardo Riva Reggiori , Lorenzo Bedarida , Giorgio Oddone , Fabio Tassan Caser
发明人： Riccardo Riva Reggiori , Lorenzo Bedarida , Giorgio Oddone , Fabio Tassan Caser
IPC分类号： G11C17/00
CPC分类号： G11C16/22 , G11C2216/26
摘要： A method and system for protecting a memory having a plurality of blocks from modification is disclosed. The method and system include providing a plurality of one time programmable (OTP) cells and OTP cell logic coupled with the OTP cells. An OTP cell of the plurality of OTP cells corresponds to a portion of a block of the plurality of blocks. The OTP cell allows modification of the portion of the block when the OTP cell is in a first state and permanently prevents modification of the portion of the block when the OTP cell is in a second state. The OTP cell logic uses the plurality of OTP cells to select the portion of the block as corresponding to the OTP cell. This portion of the block is write protected when the OTP cell is placed in the second state.
摘要翻译：公开了一种用于保护具有多个块的存储器不被修改的方法和系统。该方法和系统包括提供与OTP单元耦合的多个一次可编程（OTP）单元和OTP单元逻辑。多个OTP单元的OTP单元对应于多个块的块的一部分。当OTP小区处于第一状态时，OTP小区允许修改块的部分，并且当OTP小区处于第二状态时永久地防止块的该部分的修改。 OTP单元逻辑使用多个OTP单元来选择与OTP单元相对应的块的该部分。当OTP单元处于第二状态时，块的这一部分是写保护的。

2. 发明申请

US20060279988A1 System and method for matching resistance in a non-volatile memory 有权
标题翻译：用于在非易失性存储器中匹配电阻的系统和方法
公开(公告)号：US20060279988A1
公开(公告)日：2006-12-14
申请号：US11193924
申请日：2005-07-28
申请人： Lorenzo Bedarida , Andrea Sacco , Giorgio Oddone , Simone Bartoli
发明人： Lorenzo Bedarida , Andrea Sacco , Giorgio Oddone , Simone Bartoli
IPC分类号： G11C16/04
CPC分类号： G11C16/26
摘要： A method and system for approximating resistance in a non-volatile memory has a memory matrix. The memory matrix has a plurality of memory cells and a plurality of memory source lines that are coupled to the plurality of memory cells. A reference matrix is coupled to the memory matrix and has a reference cell. A logic generator is coupled to the reference matrix and is configured to generate an approximation, at the reference cell, of a resistance between a selected one of the plurality of memory cells and at least one of the plurality of memory source lines.
摘要翻译：用于近似非易失性存储器中的电阻的方法和系统具有存储器矩阵。存储矩阵具有耦合到多个存储单元的多个存储器单元和多个存储器源极线。参考矩阵耦合到存储器矩阵并具有参考单元。逻辑发生器耦合到参考矩阵，并被配置为在参考单元处产生多个存储器单元中的所选择的一个与多个存储器源极线中的至少一个之间的电阻的近似。

3. 发明授权

US07499334B2 Method and apparatus for discharging a memory cell in a memory device after an erase operation 有权
标题翻译：在擦除操作之后，用于在存储器件中放电存储单元的方法和装置
公开(公告)号：US07499334B2
公开(公告)日：2009-03-03
申请号：US11583625
申请日：2006-10-18
申请人： Lorenzo Bedarida , Simone Bartoli , Giorgio Oddone , Davide Manfre′
发明人： Lorenzo Bedarida , Simone Bartoli , Giorgio Oddone , Davide Manfre′
IPC分类号： G11C11/34
CPC分类号： G11C16/12 , G11C16/10 , G11C16/22
摘要： A method and apparatus for discharging a memory cell in a memory device. In one implementation, the memory cell includes a capacitor having a first plate and a second plate, and the method includes initially discharging the first plate of the capacitor through a first discharge circuit and discharging the second plate of the capacitor through a second discharge circuit. After the initial discharge, the method further includes completely discharging the first plate of the capacitor and the second plate of the capacitor by coupling both the first plate of the capacitor and the second plate of the capacitor to ground.
摘要翻译：一种用于对存储器件中的存储单元进行放电的方法和装置。在一个实施方式中，存储单元包括具有第一板和第二板的电容器，并且该方法包括首先通过第一放电电路对电容器的第一板进行放电，并通过第二放电电路对电容器的第二板进行放电。在初始放电之后，该方法还包括通过将电容器的第一板和电容器的第二板耦合到地将电容器的第一板和电容器的第二板完全放电。

4. 发明申请

US20070253255A1 Memory device, method for sensing a current output from a selected memory cell and sensing circuit 审中-公开
标题翻译：存储器件，用于感测来自所选存储器单元和感测电路的电流输出的方法
公开(公告)号：US20070253255A1
公开(公告)日：2007-11-01
申请号：US11414622
申请日：2006-04-28
申请人： Girolamo Gallo , Giorgio Oddone , Alberto Taddeo , Carmelo Giunta , Marco Carminati
发明人： Girolamo Gallo , Giorgio Oddone , Alberto Taddeo , Carmelo Giunta , Marco Carminati
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： G11C7/062 , G11C7/02 , G11C7/04 , G11C7/067 , G11C16/26 , G11C16/3418 , G11C16/3427 , G11C2207/063
摘要： A memory device, a method for sensing a current output and a sensing circuit are disclosed. In one embodiment, a first voltage is supplied at least to a drain and a source terminal of a neighboring memory cell before sensing, and the first voltage is applied to a source terminal of a selected memory cell, while sensing the current though the selected memory cell.
摘要翻译：公开了一种存储器件，用于感测电流输出的方法和感测电路。在一个实施例中，在感测之前至少将相邻存储单元的漏极和源极端子提供第一电压，并且将第一电压施加到所选择的存储器单元的源极端口，同时通过选择的存储器感测电流细胞。

5. 发明授权

US07176750B2 Method and apparatus for fast power-on of the band-gap reference 有权
标题翻译：带隙基准快速上电的方法和装置
公开(公告)号：US07176750B2
公开(公告)日：2007-02-13
申请号：US11124871
申请日：2005-05-09
申请人： Giorgio Oddone , Stefano Sivero , Giorgio Bosisio , Andrea Bettini
发明人： Giorgio Oddone , Stefano Sivero , Giorgio Bosisio , Andrea Bettini
IPC分类号： G05F1/10
CPC分类号： G05F3/30
摘要： A fast power-on band-gap reference circuit includes a buffer, a first band-gap logic, and a second high drive band-gap logic. During power-on of the band-gap reference circuit, both the first band-gap logic and the second high drive band-gap logic are activated, in which the first band-gap logic charges an output of the first band-gap logic and the second high drive band-gap logic charges a capacitance associated with an output of the band-gap reference circuit. When the output of the first band-gap logic reaches a predetermined value, the second high drive band-gap logic is deactivated and the output of the first band-gap logic is couple to the output of the band-gap reference circuit through the buffer.
摘要翻译：快速上电带隙参考电路包括缓冲器，第一带隙逻辑和第二高驱动带隙逻辑。在带隙参考电路的上电期间，第一带隙逻辑和第二高驱动带隙逻辑都被激活，其中第一带隙逻辑对第一带隙逻辑的输出进行充电，第二高驱动带隙逻辑对与带隙基准电路的输出相关联的电容进行充电。当第一带隙逻辑的输出达到预定值时，第二高驱动带隙逻辑被去激活，并且第一带隙逻辑的输出通过缓冲器耦合到带隙参考电路的输出。

6. 发明申请

US20060140010A1 Method and system for reducing soft-writing in a multi-level flash memory 失效
公开(公告)号：US20060140010A1
公开(公告)日：2006-06-29
申请号：US11144174
申请日：2005-06-02
申请人： Lorenzo Bedarida , Fabio Caser , Simone Bartoli , Giorgio Oddone
发明人： Lorenzo Bedarida , Fabio Caser , Simone Bartoli , Giorgio Oddone
IPC分类号： G11C16/04
CPC分类号： G11C16/3454
摘要： A system and method for reducing soft-writing in a multilevel flash memory during read or verify includes a memory cell. A first and second reference cells are coupled to the memory cell and are configured to receive a first and a second voltage. A current comparison circuit is coupled to the first and second reference cells and to the memory cell and is configured to compare current flow through the memory cell with current flow through the first and second reference cells, and to determine whether the memory cell holds a first range of values while the first reference cell receives the first voltage, and if the memory cell does not hold the first range of values, to determine whether the memory cell holds a second range of values while the second reference cell receives the second voltage, thereby reducing soft-writing during the read operation.

7. 发明申请

US20060038609A1 Method and apparatus for fast power-on of the band-gap reference 有权
标题翻译：带隙基准快速上电的方法和装置
公开(公告)号：US20060038609A1
公开(公告)日：2006-02-23
申请号：US11124871
申请日：2005-05-09
申请人： Giorgio Oddone , Stefano Sivero , Giorgio Bosisio , Andrea Bettini
发明人： Giorgio Oddone , Stefano Sivero , Giorgio Bosisio , Andrea Bettini
IPC分类号： G05F1/10
CPC分类号： G05F3/30
摘要： A fast power-on band-gap reference circuit includes a band-gap logic and a band-gap dummy logic. During power-on, both the band-gap logic and the band-gap dummy logic are activated and charges the capacitance of a band-gap line. When an output of the band-gap logic reaches a predetermined value, the band-gap dummy logic is deactivated. Thus, the band-gap dummy logic, with a high drive capability, charges the band-gap capacitance at the same time the band-gap logic starts to generate the compensate temperature voltage. In this manner, the band-gap reference circuit reaches its stable, functional state faster than conventional circuits, in the range of a few microseconds.
摘要翻译：快速上电带隙参考电路包括带隙逻辑和带隙虚拟逻辑。在上电期间，带隙逻辑和带隙虚拟逻辑都被激活并对带隙线的电容进行充电。当带隙逻辑的输出达到预定值时，带隙虚拟逻辑被去激活。因此，具有高驱动能力的带隙虚拟逻辑在带隙逻辑开始产生补偿温度电压的同时对带隙电容进行充电。以这种方式，带隙参考电路在几微秒的范围内达到其比常规电路更稳定的功能状态。

8. 发明申请

US20120212259A1 COMPARATOR OF A DIFFERENCE OF INPUT VOLTAGES WITH AT LEAST A THRESHOLD 审中-公开
标题翻译：输入电压差异至少达到阈值的比较器
公开(公告)号：US20120212259A1
公开(公告)日：2012-08-23
申请号：US13398694
申请日：2012-02-16
申请人： Alberto Riva , Giorgio Oddone , Domenico Attianese
发明人： Alberto Riva , Giorgio Oddone , Domenico Attianese
IPC分类号： H03K5/22
CPC分类号： H03K5/082 , G01R19/10 , G01R19/1659 , H03F3/45179 , H03F3/45183 , H03F2203/45394 , H03F2203/45498 , H03F2203/45646 , H03F2203/45702 , H03K5/2481
摘要： A comparator is configured to generate an output voltage representing the comparison between the absolute value of the difference between two input voltages with an adjustable reference voltage. The comparator includes an input differential amplifier, receiving the two input voltages and connected to an active load network controlled by a control voltage, a control circuit that generates the control voltage representing the adjustable reference voltage, and an output stage having a logic circuit configured to produce the output voltage of the comparator as a logic combination of the output voltages of the differential amplifier.
摘要翻译：比较器被配置为产生表示两个输入电压之间的差的绝对值与可调参考电压之间的比较的输出电压。比较器包括输入差分放大器，接收两个输入电压并连接到由控制电压控制的有源负载网络，产生表示可调参考电压的控制电压的控制电路，以及具有逻辑电路的输出级，该逻辑电路被配置为产生比较器的输出电压作为差分放大器的输出电压的逻辑组合。

9. 发明授权

US07522455B2 Method and system for reducing soft-writing in a multi-level flash memory 失效
标题翻译：减少多级闪存中软写入的方法和系统
公开(公告)号：US07522455B2
公开(公告)日：2009-04-21
申请号：US11144174
申请日：2005-06-02
申请人： Lorenzo Bedarida , Fabio Tassan Caser , Simone Bartoli , Giorgio Oddone
发明人： Lorenzo Bedarida , Fabio Tassan Caser , Simone Bartoli , Giorgio Oddone
IPC分类号： G11C11/34
CPC分类号： G11C16/3454
摘要： A system and method for reducing soft-writing in a multilevel flash memory during read or verify includes a memory cell. A first and second reference cells are coupled to the memory cell and are configured to receive a first and a second voltage. A current comparison circuit is coupled to the first and second reference cells and to the memory cell and is configured to compare current flow through the memory cell with current flow through the first and second reference cells, and to determine whether the memory cell holds a first range of values while the first reference cell receives the first voltage, and if the memory cell does not hold the first range of values, to determine whether the memory cell holds a second range of values while the second reference cell receives the second voltage, thereby reducing soft-writing during the read operation.
摘要翻译：在读取或验证期间减少多级闪存中的软写入的系统和方法包括存储单元。第一和第二参考单元耦合到存储单元，并被配置为接收第一和第二电压。电流比较电路耦合到第一和第二参考单元和存储单元，并且被配置为将通过存储器单元的电流与通过第一和第二参考单元的电流进行比较，并且确定存储器单元是否保持第一在第一参考单元接收到第一电压的同时，如果存储单元不保持第一范围的值，则确定存储单元是否在第二参考单元接收到第二电压时保持第二范围的值，从而在读取操作期间减少软写入。

10. 发明申请

US20070025134A1 Flexible OTP sector protection architecture for flash memories 有权
标题翻译：灵活的OTP扇区保护架构，用于闪存
公开(公告)号：US20070025134A1
公开(公告)日：2007-02-01
申请号：US11529158
申请日：2006-09-28
申请人： Riccardo Riva Reggiori , Lorenzo Bedarida , Giorgio Oddone , Fabio Tassan Caser
发明人： Riccardo Riva Reggiori , Lorenzo Bedarida , Giorgio Oddone , Fabio Tassan Caser
IPC分类号： G11C17/00
CPC分类号： G11C16/22 , G11C2216/26
摘要： A method and system for protecting a memory having a plurality of blocks from modification is disclosed. The method and system include providing a plurality of one time programmable (OTP) cells and OTP cell logic coupled with the OTP cells. An OTP cell of the plurality of OTP cells corresponds to a portion of a block of the plurality of blocks. The OTP cell allows modification of the portion of the block when the OTP cell is in a first state and permanently prevents modification of the portion of the block when the OTP cell is in a second state. The OTP cell logic uses the plurality of OTP cells to select the portion of the block as corresponding to the OTP cell. This portion of the block is write protected when the OTP cell is placed in the second state.
摘要翻译：公开了一种用于保护具有多个块的存储器不被修改的方法和系统。该方法和系统包括提供与OTP单元耦合的多个一次可编程（OTP）单元和OTP单元逻辑。多个OTP单元的OTP单元对应于多个块的块的一部分。当OTP小区处于第一状态时，OTP小区允许修改块的部分，并且当OTP小区处于第二状态时永久地防止块的该部分的修改。 OTP单元逻辑使用多个OTP单元来选择与OTP单元相对应的块的该部分。当OTP单元处于第二状态时，块的这一部分是写保护的。

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