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1. 发明授权

US07782695B2 Compensated current offset in a sensing circuit 有权
标题翻译：感测电路中的补偿电流偏移
公开(公告)号：US07782695B2
公开(公告)日：2010-08-24
申请号：US11652742
申请日：2007-01-12
申请人： Lorenzo Bedarida , Gabriele Pelli , Simone Bartoli , Mauro Chinosi
发明人： Lorenzo Bedarida , Gabriele Pelli , Simone Bartoli , Mauro Chinosi
IPC分类号： G11C7/00
CPC分类号： G11C7/062 , G11C7/02 , G11C7/067 , G11C16/26 , G11C2207/063
摘要： A sensing circuit with current offset functionality. In one embodiment, the sensing circuit includes a memory circuit having a first offset circuit operative to offset a first current. The sensing circuit also includes a reference circuit coupled to the memory circuit, where the reference circuit includes a second offset circuit operative to offset a second current. The sensing circuit also includes a compare circuit coupled to the memory circuit and the reference circuit, where the compare circuit determines the state of a memory cell based on first current and the second current. According to the system disclosed herein, the first and second offset circuits optimize the performance of the sensing circuit and prevent errors when determining the state of the memory cell.
摘要翻译：具有电流偏移功能的感测电路。在一个实施例中，感测电路包括存储器电路，该存储器电路具有可操作以偏移第一电流的第一偏移电路。感测电路还包括耦合到存储器电路的参考电路，其中参考电路包括可操作以偏移第二电流的第二偏移电路。感测电路还包括耦合到存储器电路和参考电路的比较电路，其中比较电路基于第一电流和第二电流确定存储器单元的状态。根据本文公开的系统，第一和第二偏移电路优化感测电路的性能并且在确定存储器单元的状态时防止错误。

2. 发明申请

US20080170455A1 Compensated current offset in a sensing circuit 有权
标题翻译：感测电路中的补偿电流偏移
公开(公告)号：US20080170455A1
公开(公告)日：2008-07-17
申请号：US11652742
申请日：2007-01-12
申请人： Lorenzo Bedarida , Gabriele Pelli , Simone Bartoli , Mauro Chinosi
发明人： Lorenzo Bedarida , Gabriele Pelli , Simone Bartoli , Mauro Chinosi
IPC分类号： G11C7/08
CPC分类号： G11C7/062 , G11C7/02 , G11C7/067 , G11C16/26 , G11C2207/063
摘要： A sensing circuit with current offset functionality. In one embodiment, the sensing circuit includes a memory circuit having a first offset circuit operative to offset a first current. The sensing circuit also includes a reference circuit coupled to the memory circuit, where the reference circuit includes a second offset circuit operative to offset a second current. The sensing circuit also includes a compare circuit coupled to the memory circuit and the reference circuit, where the compare circuit determines the state of a memory cell based on first current and the second current. According to the system disclosed herein, the first and second offset circuits optimize the performance of the sensing circuit and prevent errors when determining the state of the memory cell.
摘要翻译：具有电流偏移功能的感测电路。在一个实施例中，感测电路包括存储器电路，该存储器电路具有可操作以偏移第一电流的第一偏移电路。感测电路还包括耦合到存储器电路的参考电路，其中参考电路包括可操作以偏移第二电流的第二偏移电路。感测电路还包括耦合到存储器电路和参考电路的比较电路，其中比较电路基于第一电流和第二电流确定存储器单元的状态。根据本文公开的系统，第一和第二偏移电路优化感测电路的性能并且在确定存储器单元的状态时防止错误。

3. 发明授权

US07561485B2 Sense architecture 有权
标题翻译：感觉架构
公开(公告)号：US07561485B2
公开(公告)日：2009-07-14
申请号：US11652771
申请日：2007-01-12
申请人： Gabriele Pelli , Lorenzo Bedarida , Simone Bartoli , Giorgio Bosisio
发明人： Gabriele Pelli , Lorenzo Bedarida , Simone Bartoli , Giorgio Bosisio
IPC分类号： G11C7/02
CPC分类号： G11C16/28
摘要： A memory system is disclosed. In one embodiment, the memory system includes a first bitline, where the first bitline produces a first transient current. The memory system also includes a sense amplifier coupled to the first bitline. The memory system also includes a second bitline coupled to the sense amplifier, where the second bitline produces a second transient current that is equal to the first transient current. The sense amplifier enables the first and second transient currents to be canceled. According to the system disclosed herein, the state of a memory cell may be determined without being adversely affected by transient currents.
摘要翻译：公开了一种存储系统。在一个实施例中，存储器系统包括第一位线，其中第一位线产生第一瞬态电流。存储器系统还包括耦合到第一位线的读出放大器。存储器系统还包括耦合到读出放大器的第二位线，其中第二位线产生等于第一瞬态电流的第二瞬态电流。读出放大器能够消除第一和第二瞬态电流。根据本文公开的系统，可以确定存储器单元的状态而不受瞬态电流的不利影响。

4. 发明申请

US20080170441A1 Sense architecture 有权
标题翻译：感觉架构
公开(公告)号：US20080170441A1
公开(公告)日：2008-07-17
申请号：US11652771
申请日：2007-01-12
申请人： Gabriele Pelli , Lorenzo Bedarida , Simone Bartoli , Giorgio Bosisio
发明人： Gabriele Pelli , Lorenzo Bedarida , Simone Bartoli , Giorgio Bosisio
IPC分类号： G11C16/28
CPC分类号： G11C16/28
摘要： A memory system is disclosed. In one embodiment, the memory system includes a first bitline, where the first bitline produces a first transient current. The memory system also includes a sense amplifier coupled to the first bitline. The memory system also includes a second bitline coupled to the sense amplifier, where the second bitline produces a second transient current that is equal to the first transient current. The sense amplifier enables the first and second transient currents to be canceled. According to the system disclosed herein, the state of a memory cell may be determined without being adversely affected by transient currents.
摘要翻译：公开了一种存储系统。在一个实施例中，存储器系统包括第一位线，其中第一位线产生第一瞬态电流。存储器系统还包括耦合到第一位线的读出放大器。存储器系统还包括耦合到读出放大器的第二位线，其中第二位线产生等于第一瞬态电流的第二瞬态电流。读出放大器能够消除第一和第二瞬态电流。根据本文公开的系统，可以确定存储器单元的状态而不受瞬态电流的不利影响。

5. 发明申请

US20080170454A1 Sense amplifier with stages to reduce capacitance mismatch in current mirror load 有权
标题翻译：具有阶段的感应放大器，以减少电流镜像负载中的电容失配
公开(公告)号：US20080170454A1
公开(公告)日：2008-07-17
申请号：US11652770
申请日：2007-01-12
申请人： Gabriele Pelli , Lorenzo Bedarida , Massimiliano Frulio , Davide Manfre
发明人： Gabriele Pelli , Lorenzo Bedarida , Massimiliano Frulio , Davide Manfre
IPC分类号： G11C7/06
CPC分类号： G11C7/062 , G11C7/067 , G11C16/28 , G11C2207/063
摘要： A sense amplifier circuit for reading the state of memory cells. In one aspect of the invention, the sense amplifier circuit includes a first stage receiving a cell current derived from the memory cell and a reference current derived from a reference cell, and a second stage receiving the cell current and the reference current. A comparator, coupled to the first stage and the second stage, provides an output indicative of the state of the memory cell based on a difference of the voltages provided by the first stage and the second stage, where the state indicated by the comparator is substantially unaffected by capacitive current components provided by transient behavior of the first and second stages.
摘要翻译：一种用于读取存储器单元状态的读出放大器电路。在本发明的一个方面，读出放大器电路包括接收从存储单元导出的单元电流的第一级和从参考单元导出的参考电流，以及接收单元电流和参考电流的第二级。耦合到第一级和第二级的比较器基于由第一级和第二级提供的电压的差提供指示存储器单元的状态的输出，其中由比较器指示的状态基本上不受由第一和第二级的瞬态特性提供的电容电流分量的影响。

6. 发明申请

US20080164948A1 BIASING CURRENT TO SPEED UP CURRENT MIRROR SETTLING TIME 有权
标题翻译：偏移电流以加快电流反射时间
公开(公告)号：US20080164948A1
公开(公告)日：2008-07-10
申请号：US11619729
申请日：2007-01-04
申请人： Gabriele Pelli , Lorenzo Bedarida , Massimiliano Frulio , Andrea Bettini
发明人： Gabriele Pelli , Lorenzo Bedarida , Massimiliano Frulio , Andrea Bettini
IPC分类号： H03F3/04
CPC分类号： H03F3/343 , G09G3/20 , G09G3/3216 , G09G3/3225
摘要： A current mirror circuit includes a first current-mirror transistor coupled to a second current-mirror transistor. A load is coupled to the second current-mirror transistor. A first current source is coupled to the first current-mirror transistor to cause a bias current to flow through the first current-mirror transistor and a second current source is coupled to the second current-mirror transistor and in parallel with the load to shunt the bias current away from the load.
摘要翻译：电流镜电路包括耦合到第二电流镜晶体管的第一电流镜晶体管。负载耦合到第二电流镜晶体管。第一电流源耦合到第一电流镜晶体管以引起偏置电流流过第一电流镜晶体管，并且第二电流源耦合到第二电流镜晶体管并且与负载并联以分流偏置电流远离负载。

7. 发明授权

US06809575B2 Temperature-compensated current reference circuit 有权
标题翻译：温度补偿电流参考电路
公开(公告)号：US06809575B2
公开(公告)日：2004-10-26
申请号：US10407622
申请日：2003-04-03
申请人： Giorgio Oddone , Lorenzo Bedarida , Mauro Chinosi
发明人： Giorgio Oddone , Lorenzo Bedarida , Mauro Chinosi
IPC分类号： G05F110
CPC分类号： G05F3/245
摘要： A circuit comprises an amplifier having first output node comprising a first n-channel MOS transistor and a second output node comprising a second n-channel MOS transistor. A first p-channel MOS transistor is coupled to a supply potential, and the second output node. A first PNP bipolar transistor is coupled to the first p-channel MOS transistor through a first resistor and to the second n-channel MOS transistor and to ground. A second PNP bipolar transistor is coupled to the first p-channel MOS transistor through a second resistor in series with a third resistor and to ground. The first n-channel MOS transistor is coupled to a common node between the second and third resistors. A third n-channel MOS transistor is coupled to the first p-channel MOS transistor, to ground through a fourth resistor, and to either a reference potential or to the common node between the second and third resistors.
摘要翻译：一种电路包括具有包括第一n沟道MOS晶体管的第一输出节点和包括第二n沟道MOS晶体管的第二输出节点的放大器。第一p沟道MOS晶体管耦合到电源电位和第二输出节点。第一PNP双极晶体管通过第一电阻器和第二n沟道MOS晶体管耦合到第一p沟道MOS晶体管并接地。第二PNP双极晶体管通过与第三电阻器串联的第二电阻器并接地耦合到第一p沟道MOS晶体管。第一n沟道MOS晶体管耦合到第二和第三电阻之间的公共节点。第三n沟道MOS晶体管被耦合到第一p沟道MOS晶体管，通过第四电阻器接地，并且连接到参考电位或第二和第三电阻器之间的公共节点。

8. 发明授权

US07522002B2 Biasing current to speed up current mirror settling time 有权
标题翻译：偏置电流以加快电流反射镜稳定时间
公开(公告)号：US07522002B2
公开(公告)日：2009-04-21
申请号：US11619729
申请日：2007-01-04
申请人： Gabriele Pelli , Lorenzo Bedarida , Massimiliano Frulio , Andrea Bettini
发明人： Gabriele Pelli , Lorenzo Bedarida , Massimiliano Frulio , Andrea Bettini
IPC分类号： H03F3/04
CPC分类号： H03F3/343 , G09G3/20 , G09G3/3216 , G09G3/3225
摘要： A current mirror circuit includes a first current-mirror transistor coupled to a second current-mirror transistor. A load is coupled to the second current-mirror transistor. A first current source is coupled to the first current-mirror transistor to cause a bias current to flow through the first current-mirror transistor and a second current source is coupled to the second current-mirror transistor and in parallel with the load to shunt the bias current away from the load.
摘要翻译：电流镜电路包括耦合到第二电流镜晶体管的第一电流镜晶体管。负载耦合到第二电流镜晶体管。第一电流源耦合到第一电流镜晶体管以引起偏置电流流过第一电流镜晶体管，并且第二电流源耦合到第二电流镜晶体管并且与负载并联以分流偏置电流远离负载。

9. 发明授权

US07522463B2 Sense amplifier with stages to reduce capacitance mismatch in current mirror load 有权
标题翻译：具有阶段的感应放大器，以减少电流镜像负载中的电容失配
公开(公告)号：US07522463B2
公开(公告)日：2009-04-21
申请号：US11652770
申请日：2007-01-12
申请人： Gabriele Pelli , Lorenzo Bedarida , Massimiliano Frulio , Davide Manfre′
发明人： Gabriele Pelli , Lorenzo Bedarida , Massimiliano Frulio , Davide Manfre′
IPC分类号： G11C7/00
CPC分类号： G11C7/062 , G11C7/067 , G11C16/28 , G11C2207/063
摘要： A sense amplifier circuit for reading the state of memory cells. In one aspect of the invention, the sense amplifier circuit includes a first stage receiving a cell current derived from the memory cell and a reference current derived from a reference cell, and a second stage receiving the cell current and the reference current. A comparator, coupled to the first stage and the second stage, provides an output indicative of the state of the memory cell based on a difference of the voltages provided by the first stage and the second stage, where the state indicated by the comparator is substantially unaffected by capacitive current components provided by transient behavior of the first and second stages.
摘要翻译：一种用于读取存储器单元状态的读出放大器电路。在本发明的一个方面，读出放大器电路包括接收从存储单元导出的单元电流的第一级和从参考单元导出的参考电流，以及接收单元电流和参考电流的第二级。耦合到第一级和第二级的比较器基于由第一级和第二级提供的电压的差提供指示存储器单元的状态的输出，其中由比较器指示的状态基本上不受由第一和第二级的瞬态特性提供的电容电流分量的影响。

10. 发明授权

US07158415B2 System for performing fast testing during flash reference cell setting 有权
标题翻译：在闪存参考单元设置期间执行快速测试的系统
公开(公告)号：US07158415B2
公开(公告)日：2007-01-02
申请号：US11089268
申请日：2005-03-24
申请人： Lorenzo Bedarida , Simone Bartoli , Stefano Surico , Massimiliano Frulio
发明人： Lorenzo Bedarida , Simone Bartoli , Stefano Surico , Massimiliano Frulio
IPC分类号： G11C16/10
CPC分类号： G11C29/028 , G11C16/04 , G11C29/24 , G11C29/50 , G11C29/50004 , G11C2029/5004
摘要： An embedded circuit in a memory device is used in place of an external test device to perform time-consuming tasks such as voltage verification during the setting of reference cells. An external test device programs at least one reference cell to a predetermined value. The embedded circuit uses the cell programmed by the external device as a comparative reference to program additional reference cells.
摘要翻译：使用存储器件中的嵌入式电路来代替外部测试装置来执行耗费时间的任务，例如参考单元设置期间的电压验证。外部测试装置将至少一个参考单元编程为预定值。嵌入式电路使用由外部设备编程的单元作为比较参考来编程附加参考单元。

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