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1. 发明申请

US20130193590A1 SEMICONDUCTOR DEVICE INCLUDING VOLTAGE CONVERTER CIRCUIT, AND METHOD OF MAKING THE SEMICONDUCTOR DEVICE 审中-公开
标题翻译：包括电压转换器电路的半导体器件及制造半导体器件的方法
公开(公告)号：US20130193590A1
公开(公告)日：2013-08-01
申请号：US13363242
申请日：2012-01-31
申请人： Simone Bartoli , Antonino Geraci , Stefano Sivero , Marco Passerini
发明人： Simone Bartoli , Antonino Geraci , Stefano Sivero , Marco Passerini
IPC分类号： H01L23/49 , H01L21/50
CPC分类号： H01L23/50 , G11C5/147 , H01L24/05 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/05553 , H01L2224/05554 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2224/05669 , H01L2224/32225 , H01L2224/45015 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48599 , H01L2224/48624 , H01L2224/48644 , H01L2224/48647 , H01L2224/48669 , H01L2224/49113 , H01L2224/73265 , H01L2224/85205 , H03K17/223 , H03K19/0013 , H01L2924/00014 , H01L2924/20752 , H01L2924/00012 , H01L2924/00
摘要： A semiconductor device includes a first bonding pad, a second bonding pad, a wire bonded to a selected one of the first and second bonding pads, a power supply line electrically connected to the first bonding pad, and a voltage converter circuit coupled to the second bonding pad, the voltage converter circuit being activated when the wire is bonded to the second pad to produce an internal power voltage, which is different from a voltage received by the voltage converter circuit through the wire and the second bonding pad, and supply the internal power voltage to the power supply line, and the voltage converter circuit being deactivated when the wire is connected to the first bonding pad to allow the power supply line to receive a power voltage through the wire and the first bonding pad.
摘要翻译：半导体器件包括第一接合焊盘，第二接合焊盘，接合到第一和第二接合焊盘中的所选择的接合焊盘的引线，电连接到第一接合焊盘的电源线，以及耦合到第二接合焊盘的电压转换器电路当焊丝接合到第二焊盘上时，电压转换器电路被激活以产生与电压转换器电路通过电线和第二接合焊盘接收的电压不同的内部电源电压，并且提供内部当电线连接到第一接合焊盘以允许电源线通过电线和第一接合焊盘接收电力电压时，电压转换器电路被去激活。

2. 发明授权

US07684245B2 Non-volatile memory array architecture with joined word lines 有权
标题翻译：具有连接字线的非易失性存储器阵列架构
公开(公告)号：US07684245B2
公开(公告)日：2010-03-23
申请号：US11928086
申请日：2007-10-30
申请人： Steve Schumann , Massimiliano Frulio , Simone Bartoli , Lorenzo Bedarida , Edward Shue-Ching Hui
发明人： Steve Schumann , Massimiliano Frulio , Simone Bartoli , Lorenzo Bedarida , Edward Shue-Ching Hui
IPC分类号： G11C11/34 , G11C16/04 , G11C5/06
CPC分类号： G11C16/3418 , Y10T29/49002
摘要： In an embodiment, a non-volatile memory array wherein narrow word lines, as small as the minimum feature size width F, in separate strings, are extended outwardly from a non-volatile memory array and joined by wider connector segments. The joined word lines provide new opportunities. First, metal straps that can be formed to overlie the word lines can be joined by metal connector segments to the word lines. The connector segments can serve as an interface between the polysilicon word lines and the metal straps. Two adjacent word lines in the same string share a single metal strap using these segments thereby reducing the overall number of segments and contacts in the array. Increased width of the polysilicon joinder segments joining word lines in different strings, provides the opportunity for widening the connection beyond the minimum feature size so that contact may be readily made between the metal straps and the polysilicon word lines. Second, the joined word lines require fewer row decoder circuits. One row decoder is provided for each joined set of word lines.
摘要翻译：在一个实施例中，非易失性存储器阵列，其中与分离的串中的最小特征尺寸宽度F一样小的窄字线从非易失性存储器阵列向外延伸并由更宽的连接器段连接。加入的词语提供了新的机会。首先，可以形成为覆盖字线的金属带可以通过金属连接器部分连接到字线。连接器部分可以用作多晶硅字线和金属带之间的接口。相同字符串中的两个相邻字线使用这些段共享单个金属带，从而减少阵列中的段和触点的总数。在不同的串中连接字线的多晶硅接合段的增加的宽度提供了将连接扩大超出最小特征尺寸的机会，使得可以容易地在金属带和多晶硅字线之间进行接触。第二，连接的字线需要更少的行解码器电路。为每个连接的字线组提供一行解码器。

3. 发明授权

US07551498B2 Implementation of column redundancy for a flash memory with a high write parallelism 有权
标题翻译：实现具有高写入并行性的闪存的列冗余
公开(公告)号：US07551498B2
公开(公告)日：2009-06-23
申请号：US11611452
申请日：2006-12-15
申请人： Simone Bartoli , Stefano Surico , Andrea Sacco , Maria Mostola
发明人： Simone Bartoli , Stefano Surico , Andrea Sacco , Maria Mostola
IPC分类号： G11C7/00
CPC分类号： G11C29/82 , G11C29/806 , G11C29/846
摘要： A redundant memory array has r columns of redundant memory cells, r redundant senses, and a redundant column decoder. Redundant address registers store addresses of defective regular memory cells. Redundant latches are provided in n groups of r latches. Redundancy comparison logic compares addresses of defective regular memory cells with an external input address. If the comparison is true, what is provided is: a DISABLE_LOAD signal to disable the regular senses for one of the n groups of m columns, an ENABLE_LATCH signal to one of the n groups of m columns to disables corresponding regular senses, and one or r REDO signals to a respective one of the r redundant latches in one of the n groups that is disabled. The selected one of the redundant latches activates one of the r redundant senses to access a redundant column.
摘要翻译：冗余存储器阵列具有r列的冗余存储器单元，r冗余感测器和冗余列解码器。冗余地址寄存器存储有缺陷的常规存储单元的地址。在n组r个锁存器中提供冗余锁存器。冗余比较逻辑将缺陷常规存储单元的地址与外部输入地址进行比较。如果比较是真的，提供的是：DISABLE_LOAD信号，用于禁用n列m列中的一个的常规感测，将一个ENABLE_LATCH信号分配给m列的n组中的一组，以禁用相应的常规感官，以及其中之一 r REDO信号到禁用的n个组之一的r个冗余锁存器中的相应一个。所选的一个冗余锁存器激活r个冗余感测之一以访问冗余列。

4. 发明授权

US07177198B2 Compensated method to implement a high voltage discharge phase after erase pulse in a flash memory device 有权
标题翻译：补偿方法在闪存器件中擦除脉冲后实现高电压放电相位
公开(公告)号：US07177198B2
公开(公告)日：2007-02-13
申请号：US11123979
申请日：2005-05-06
申请人： Lorenzo Bedarida , Simone Bartoli , Giorgio Oddone , Davide Manfre′
发明人： Lorenzo Bedarida , Simone Bartoli , Giorgio Oddone , Davide Manfre′
IPC分类号： G11C11/34
CPC分类号： G11C16/14
摘要： A method for discharge in a flash memory device includes: initiating a discharge of a memory cell after an erase operation; coupling a first discharge circuit to a first plate of a gate-bulk capacitor, and a second discharge circuit to a second plate of the gate-bulk capacitor, where the first plate represents the common gate node of the memory cell and the second plate represents the bulk-source node of the memory cell; and coupling the common gate node and the bulk-source node to ground to provide for a complete discharge. The current injected into the first plate approximately equals the current extracted from the second plate. In this manner, dangerous oscillations of the gate and bulk-source voltages as they go to ground are eliminated without complicated designs or voltage limitators, and without sacrificing the fast discharge after the erase operation. The reliability of the discharge operation is thus significantly improved.
摘要翻译：一种闪速存储装置中的放电方法包括：在擦除操作之后启动存储单元的放电; 将第一放电电路耦合到栅极 - 体积电容器的第一板，以及将第二放电电路耦合到栅极 - 体积电容器的第二板，其中第一板表示存储单元的公共栅极节点，第二板表示存储器单元的批量源节点; 并将公共栅极节点和体源节点耦合到地，以提供完全放电。注入第一板的电流大约等于从第二板提取的电流。以这种方式，在没有复杂设计或限压器的情况下，栅极和体源电压的危险振荡消除，而不会在擦除操作之后不牺牲快速放电。因此，放电操作的可靠性显着提高。

5. 发明申请

US20060114721A1 Method and system for regulating a program voltage value during multilevel memory device programming 有权
标题翻译：用于在多级存储器件编程期间调节编程电压值的方法和系统
公开(公告)号：US20060114721A1
公开(公告)日：2006-06-01
申请号：US11123754
申请日：2005-05-05
申请人： Massimiliano Frulio , Simone Bartoli , Davide Manfre , Andrea Sacco
发明人： Massimiliano Frulio , Simone Bartoli , Davide Manfre , Andrea Sacco
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C7/04 , G11C16/04 , G11C16/12 , G11C16/30 , G11C29/021 , G11C29/028
摘要： Regulating a program voltage value during multilevel memory device programming includes utilizing a program path duplicate in an output pump regulator circuit. Further, the output pump regulator circuit is utilized to provide a regulated program voltage for memory cell programming, the regulated program voltage correcting for a program path voltage drop and compensating for temperature variation.
摘要翻译：在多级存储器件编程期间调节编程电压值包括在输出泵调节器电路中使用程序路径副本。此外，输出泵调节器电路用于提供用于存储器单元编程的调节编程电压，用于编程路径电压降的校准编程电压并补偿温度变化。

6. 发明申请

US20060062063A1 Compensated method to implement a high voltage discharge phase after erase pulse in a flash memory device 有权
标题翻译：补偿方法在闪存器件中擦除脉冲后实现高电压放电相位
公开(公告)号：US20060062063A1
公开(公告)日：2006-03-23
申请号：US11123979
申请日：2005-05-06
申请人： Lorenzo Bedarida , Simone Bartoli , Giorgio Oddone , Davide Manfre'
发明人： Lorenzo Bedarida , Simone Bartoli , Giorgio Oddone , Davide Manfre'
IPC分类号： G11C16/04 , G11C7/00
CPC分类号： G11C16/14
摘要： A method for discharge in a flash memory device includes: initiating a discharge of a memory cell after an erase operation; coupling a first discharge circuit to a first plate of a gate-bulk capacitor, and a second discharge circuit to a second plate of the gate-bulk capacitor, where the first plate represents the common gate node of the memory cell and the second plate represents the bulk-source node of the memory cell; and coupling the common gate node and the bulk-source node to ground to provide for a complete discharge. The current injected into the first plate approximately equals the current extracted from the second plate. In this manner, dangerous oscillations of the gate and bulk-source voltages as they go to ground are eliminated without complicated designs or voltage limitators, and without sacrificing the fast discharge after the erase operation. The reliability of the discharge operation is thus significantly improved.
摘要翻译：一种闪速存储装置中的放电方法包括：在擦除操作之后启动存储单元的放电; 将第一放电电路耦合到栅极 - 体积电容器的第一板，以及将第二放电电路耦合到栅极 - 体积电容器的第二板，其中第一板表示存储单元的公共栅极节点，第二板表示存储器单元的批量源节点; 并将公共栅极节点和体源节点耦合到地，以提供完全放电。注入第一板的电流大约等于从第二板提取的电流。以这种方式，在没有复杂设计或限压器的情况下，栅极和体源电压的危险振荡消除，而不会在擦除操作之后不牺牲快速放电。因此，放电操作的可靠性显着提高。

7. 发明授权

US06912598B1 Non-volatile memory with functional capability of simultaneous modification of the content and burst mode read or page mode read 有权
标题翻译：具有同时修改内容和突发模式读取或页面模式读取功能的非易失性存储器
公开(公告)号：US06912598B1
公开(公告)日：2005-06-28
申请号：US09627703
申请日：2000-07-28
申请人： Lorenzo Bedarida , Antonino Geraci , Mauro Sali , Simone Bartoli
发明人： Lorenzo Bedarida , Antonino Geraci , Mauro Sali , Simone Bartoli
IPC分类号： G11C16/10 , G11C16/26 , G06F9/28 , G06F13/16
CPC分类号： G11C16/10 , G11C16/26
摘要： An electrically alterable semiconductor memory comprises at least two substantially independent memory banks, and a first control circuit for controlling operations of electrical alteration of the content of the memory. The first control circuit permits the selective execution of an operation of electrical alteration of the content of one of the at least two memory banks. The memory also comprises second control circuit that permits, simultaneously with said operation of electrical alteration of the content of one of the at least two memory banks, a burst mode, page mode, or standard read operation for reading the content of the other memory bank.
摘要翻译：一种电可更改的半导体存储器包括至少两个基本上独立的存储体，以及第一控制电路，用于控制存储器内容的电气改变的操作。第一控制电路允许选择性地执行对至少两个存储体之一的内容的电气改变的操作。存储器还包括第二控制电路，其允许同时对所述至少两个存储器组之一的内容进行电气改变的所述操作，用于读取另一个存储体的内容的突发模式，寻呼模式或标准读取操作。

8. 发明授权

US06724241B1 Variable charge pump circuit with dynamic load 有权
标题翻译：具有动态负载的可变电荷泵电路
公开(公告)号：US06724241B1
公开(公告)日：2004-04-20
申请号：US10352733
申请日：2003-01-27
申请人： Lorenzo Bedarida , Simone Bartoli , Stefano Sivero
发明人： Lorenzo Bedarida , Simone Bartoli , Stefano Sivero
IPC分类号： G05F110
CPC分类号： H02M3/07
摘要： A variable charge pump circuit uses a plurality of selectable loads to minimize the voltage ripples of the pumped output by selecting the appropriate load for a preselected pump voltage. The charge pump circuit also compares the pump voltage to a reference voltage to shut down the variable charge pump circuit if the pump voltage is larger than the reference voltage. The charge pump circuit also compares the maximum voltage output to the reference voltage to monitor whether the maximum ripple on voltage output is larger than the reference voltage. The charge pump circuit comprises one or more stages operable to receive a supply voltage and generate one or more pump voltages, a plurality of loads each associated with a specific pump voltage, and a load selector means coupled to the output pump and the plurality of loads for selecting a load associated with a specific pump voltage.
摘要翻译：可变电荷泵电路使用多个可选择的负载来通过为预选的泵电压选择合适的负载来最小化泵浦输出的电压波动。如果泵浦电压大于参考电压，则电荷泵电路还将泵浦电压与参考电压进行比较以关闭可变电荷泵电路。电荷泵电路还将最大电压输出与参考电压进行比较，以监测电压输出上的最大纹波是否大于参考电压。电荷泵电路包括一个或多个级，可操作以接收电源电压并产生一个或多个泵电压，每个与特定泵电压相关联的多个负载，以及耦合到输出泵和多个负载的负载选择器装置用于选择与特定泵电压相关联的负载。

9. 发明授权

US06442068B1 Non-volatile memory with functional capability of burst mode read and page mode read during suspension of an operation of electrical alteration 有权
标题翻译：在电气变更操作暂停期间读取突发模式读取和页面模式的功能性能的非易失性存储器
公开(公告)号：US06442068B1
公开(公告)日：2002-08-27
申请号：US09619589
申请日：2000-07-19
申请人： Simone Bartoli , Lorenzo Bedarida , Mauro Sali , Antonio Russo
发明人： Simone Bartoli , Lorenzo Bedarida , Mauro Sali , Antonio Russo
IPC分类号： G11C1134
CPC分类号： G11C16/26 , G11C16/10 , G11C2216/20
摘要： An electrically alterable semiconductor memory includes at least two memory sectors the content of which is individually alterable, and a control circuit for controlling operations of electrical alteration of the content of the memory, permitting the selective execution of an operation of electrical alteration of the content of one of the memory sectors with the possibility of suspending the execution to permit read access to the other of the memory sectors. The control circuit is also capable of permitting, during the suspension, an operation of burst mode or page mode reading of the content of the other memory sector.
摘要翻译：电可改变的半导体存储器包括至少两个存储器扇区，其内容是可单独改变的;以及控制电路，用于控制存储器内容的电气改变的操作，允许选择性地执行对内容的电气改变的操作其中一个存储器扇区具有暂停执行以允许对另一个存储器扇区的读取访问的可能性。控制电路还能够在暂停期间允许对其他存储器扇区的内容的突发模式或页面模式读取的操作。

10. 发明授权

US06353350B1 Pulse generator independent of supply voltage 有权
标题翻译：脉冲发生器独立于电源电压
公开(公告)号：US06353350B1
公开(公告)日：2002-03-05
申请号：US09721502
申请日：2000-11-22
申请人： Lorenzo Bedarida , Simone Bartoli , Luigi Bettini
发明人： Lorenzo Bedarida , Simone Bartoli , Luigi Bettini
IPC分类号： H03K300
CPC分类号： G11C7/04 , G11C7/06 , G11C7/22 , G11C2207/065 , H03K3/011 , H03K3/355 , H03K5/04
摘要： A pulse generator of a type that includes at least one current mirror connected between first and second voltage references and to at least one initiation terminal receiving a pulsive-type initiating signal, connected to a load terminal receiving a load signal, and connected to an output terminal providing an output signal. The pulse generator further includes at least one logic gate having one input terminal connected to an internal control circuit node of the current mirror, having another input terminal connected to receive the initiating signal, and having an output terminal connected to the output terminal of the pulse generator; at least one regulator circuit connected between the current mirror and the second voltage reference and feedback connected to the output terminal; and at least one conductive-type transistor connected between the current mirror and the regulator circuit; the output terminal of the pulse generator delivering a retarded pulsive-type output signal that is independent of the supply voltage and exhibits the same dependency on temperature as the regulator circuit.
摘要翻译：一种类型的脉冲发生器，包括连接在第一和第二电压基准之间的至少一个电流镜和连接到接收负载信号的负载终端并连接到输出的至少一个起始终端的起始终端终端提供输出信号。脉冲发生器还包括至少一个逻辑门，其中一个输入端连接到电流镜的内部控制电路节点，其另一输入端连接以接收起始信号，并且具有连接到脉冲的输出端的输出端发电机; 连接在电流镜与第二电压基准之间的至少一个调节器电路和连接到输出端的反馈; 以及连接在电流镜和调节器电路之间的至少一个导电型晶体管; 脉冲发生器的输出端子输出与电源电压无关的延迟脉动型输出信号，并且对温度表现出与调节器电路相同的依赖性。

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