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1. 发明申请

US20140293707A1 Erase Techniques and Circuits Therefor for Non-Volatile Memory Devices 有权
标题翻译：用于非易失性存储器件的擦除技术及其电路
公开(公告)号：US20140293707A1
公开(公告)日：2014-10-02
申请号：US14227676
申请日：2014-03-27
申请人： Vincenzo Ferragina , Stefano Surico , Giuseppe Moioli , Simone Bartoli
发明人： Vincenzo Ferragina , Stefano Surico , Giuseppe Moioli , Simone Bartoli
IPC分类号： G11C16/34
CPC分类号： G11C16/3445 , G11C16/0483 , G11C16/16 , G11C16/3418
摘要： Disclosed herein is a method that comprises applying a first voltage to a memory cell, applying again the first voltage to the memory cell when the memory cell have not been shifted to an erased condition, and applying a second voltage to the memory cell when the memory cell have not still been shifted to an erased condition, the second voltage being higher than the first voltage.
摘要翻译：本文公开了一种方法，其包括向存储器单元施加第一电压，当存储器单元未被移位到擦除状态时再次将第一电压施加到存储器单元，以及当存储器向存储器单元施加第二电压时，单元还没有被移动到擦除状态，第二电压高于第一电压。

2. 发明申请

US20130016564A1 ERASE TECHNIQUES AND CIRCUITS THEREFOR FOR NON-VOLATILE MEMORY DEVICES 失效
标题翻译：用于非易失性存储器件的擦除技术和电路
公开(公告)号：US20130016564A1
公开(公告)日：2013-01-17
申请号：US13181988
申请日：2011-07-13
申请人： Vincenzo Ferragina , Stefano Surico , Giuseppe Moioli , Simone Bartoli
发明人： Vincenzo Ferragina , Stefano Surico , Giuseppe Moioli , Simone Bartoli
IPC分类号： G11C16/14 , G11C16/16
CPC分类号： G11C16/3445 , G11C16/0483 , G11C16/16 , G11C16/3418
摘要： Disclosed herein is a method that comprises applying a first voltage to a memory cell, applying again the first voltage to the memory cell when the memory cell have not been shifted to an erased condition, and applying a second voltage to the memory cell when the memory cell have not still been shifted to an erased condition, the second voltage being higher than the first voltage.
摘要翻译：本文公开了一种方法，其包括向存储器单元施加第一电压，当存储器单元未被移位到擦除状态时再次将第一电压施加到存储器单元，以及当存储器向存储器单元施加第二电压时，单元还没有被移动到擦除状态，第二电压高于第一电压。

3. 发明授权

US08705283B2 Erase techniques and circuits therefor for non-volatile memory devices 失效
标题翻译：擦除非易失性存储器件的技术和电路
公开(公告)号：US08705283B2
公开(公告)日：2014-04-22
申请号：US13181988
申请日：2011-07-13
申请人： Vincenzo Ferragina , Stefano Surico , Giuseppe Moioli , Simone Bartoli
发明人： Vincenzo Ferragina , Stefano Surico , Giuseppe Moioli , Simone Bartoli
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/3445 , G11C16/0483 , G11C16/16 , G11C16/3418
摘要： Disclosed herein is a method that comprises applying a first voltage to a memory cell, applying again the first voltage to the memory cell when the memory cell have not been shifted to an erased condition, and applying a second voltage to the memory cell when the memory cell have not still been shifted to an erased condition, the second voltage being higher than the first voltage.
摘要翻译：本文公开了一种方法，其包括向存储器单元施加第一电压，当存储器单元未被移位到擦除状态时再次将第一电压施加到存储器单元，以及当存储器向存储器单元施加第二电压时，单元还没有被移动到擦除状态，第二电压高于第一电压。

4. 发明授权

US07249215B2 System for configuring parameters for a flash memory 有权
公开(公告)号：US07249215B2
公开(公告)日：2007-07-24
申请号：US11635315
申请日：2006-12-07
申请人： Stefano Surico , Simone Bartoli , Mirella Marsella , Giorgio Bosisio
发明人： Stefano Surico , Simone Bartoli , Mirella Marsella , Giorgio Bosisio
IPC分类号： G06F12/00
CPC分类号： G11C16/20 , G11C16/04 , G11C29/02 , G11C29/021 , G11C29/028 , G11C2029/4402
摘要： System for configuring parameters used in flash memory devices. A load instruction and associated address are retrieved from a memory, and the address is used to select a configuration register storing a configuration value. The configuration value is loaded to an associated dedicated register to configure a parameter of the flash memory in a flash memory operation.

5. 发明授权

US07551498B2 Implementation of column redundancy for a flash memory with a high write parallelism 有权
标题翻译：实现具有高写入并行性的闪存的列冗余
公开(公告)号：US07551498B2
公开(公告)日：2009-06-23
申请号：US11611452
申请日：2006-12-15
申请人： Simone Bartoli , Stefano Surico , Andrea Sacco , Maria Mostola
发明人： Simone Bartoli , Stefano Surico , Andrea Sacco , Maria Mostola
IPC分类号： G11C7/00
CPC分类号： G11C29/82 , G11C29/806 , G11C29/846
摘要： A redundant memory array has r columns of redundant memory cells, r redundant senses, and a redundant column decoder. Redundant address registers store addresses of defective regular memory cells. Redundant latches are provided in n groups of r latches. Redundancy comparison logic compares addresses of defective regular memory cells with an external input address. If the comparison is true, what is provided is: a DISABLE_LOAD signal to disable the regular senses for one of the n groups of m columns, an ENABLE_LATCH signal to one of the n groups of m columns to disables corresponding regular senses, and one or r REDO signals to a respective one of the r redundant latches in one of the n groups that is disabled. The selected one of the redundant latches activates one of the r redundant senses to access a redundant column.
摘要翻译：冗余存储器阵列具有r列的冗余存储器单元，r冗余感测器和冗余列解码器。冗余地址寄存器存储有缺陷的常规存储单元的地址。在n组r个锁存器中提供冗余锁存器。冗余比较逻辑将缺陷常规存储单元的地址与外部输入地址进行比较。如果比较是真的，提供的是：DISABLE_LOAD信号，用于禁用n列m列中的一个的常规感测，将一个ENABLE_LATCH信号分配给m列的n组中的一组，以禁用相应的常规感官，以及其中之一 r REDO信号到禁用的n个组之一的r个冗余锁存器中的相应一个。所选的一个冗余锁存器激活r个冗余感测之一以访问冗余列。

6. 发明申请

US20080144379A1 IMPLEMENTATION OF COLUMN REDUNDANCY FOR A FLASH MEMORY WITH A HIGH WRITE PARALLELISM 有权
标题翻译：实现具有高写并发性的闪存存储器的冗余冗余
公开(公告)号：US20080144379A1
公开(公告)日：2008-06-19
申请号：US11611452
申请日：2006-12-15
申请人： Simone Bartoli , Stefano Surico , Andrea Sacco , Maria Mostola
发明人： Simone Bartoli , Stefano Surico , Andrea Sacco , Maria Mostola
IPC分类号： G11C16/06
CPC分类号： G11C29/82 , G11C29/806 , G11C29/846
摘要： A redundant memory array has r columns of redundant memory cells, r redundant senses, and a redundant column decoder. Redundant address registers store addresses of defective regular memory cells. Redundant latches are provided in n groups of r latches. Redundancy comparison logic compares addresses of defective regular memory cells with an external input address. If the comparison is true, what is provided is: a DISABLE_LOAD signal to disable the regular senses for one of the n groups of m columns, an ENABLE_LATCH signal to one of the n groups of m columns to disables corresponding regular senses, and one or r REDO signals to a respective one of the r redundant latches in one of the n groups that is disabled. The selected one of the redundant latches activates one of the r redundant senses to access a redundant column.
摘要翻译：冗余存储器阵列具有r列的冗余存储器单元，r冗余感测器和冗余列解码器。冗余地址寄存器存储有缺陷的常规存储单元的地址。在n组r个锁存器中提供冗余锁存器。冗余比较逻辑将缺陷常规存储单元的地址与外部输入地址进行比较。如果比较是真的，提供的是：DISABLE_LOAD信号，用于禁用n列m列中的一个的常规感测，将一个ENABLE_LATCH信号分配给m列的n组中的一组，以禁用相应的常规感官，以及其中之一 r REDO信号到禁用的n个组之一的r个冗余锁存器中的相应一个。所选的一个冗余锁存器激活r个冗余感测之一以访问冗余列。

7. 发明申请

US20060077714A1 Method and system for a programming approach for a nonvolatile electronic device 有权
标题翻译：用于非易失性电子设备的编程方法的方法和系统
公开(公告)号：US20060077714A1
公开(公告)日：2006-04-13
申请号：US11128939
申请日：2005-05-12
申请人： Stefano Surico , Simone Bartoli , Fabio Tassan Caser , Monica Marziani
发明人： Stefano Surico , Simone Bartoli , Fabio Tassan Caser , Monica Marziani
IPC分类号： G11C16/06
CPC分类号： G11C11/5628 , G11C16/3468 , G11C16/3481 , G11C2211/5621 , G11C2211/5634
摘要： Aspects for programming a nonvolatile electronic device include performing an initial verify step of a programming algorithm with an initial type of reference voltage value, and performing one or more subsequent verify steps in the programming algorithm with a second type of reference voltage value. Further included is utilizing a read reference voltage for the initial verify step, wherein desired programming is ensured for a cell that falls out of ideal distribution.
摘要翻译：用于编程非易失性电子设备的方面包括使用初始类型的参考电压值执行编程算法的初始验证步骤，以及使用第二类型的参考电压值来执行编程算法中的一个或多个后续验证步骤。进一步包括利用读取参考电压进行初始验证步骤，其中为理想分布的单元确保期望的编程。

8. 发明授权

US07769943B2 Flexible, low cost apparatus and method to introduce and check algorithm modifications in a non-volatile memory 有权
标题翻译：灵活，低成本的装置和方法来引入和检查非易失性存储器中的算法修改
公开(公告)号：US07769943B2
公开(公告)日：2010-08-03
申请号：US11696288
申请日：2007-04-04
申请人： Stefano Surico , Stefano Sivero , Simone Bartoli , Marco Passerini
发明人： Stefano Surico , Stefano Sivero , Simone Bartoli , Marco Passerini
IPC分类号： G06F12/00
CPC分类号： G11C16/10
摘要： A flash memory includes input/output buffers, a memory array having memory cells coupled to the input/output buffers, and row and column decoders, and a voltage-generator circuit coupled to the row and column decoders. A microcontroller is coupled to the command user interface. Switch-instruction circuitry selectively provides instructions to the microcontroller from the read-only memory and from off chip through on-board t-latches coupled to the input/output buffers under control of a command user interface.
摘要翻译：闪速存储器包括输入/输出缓冲器，具有耦合到输入/输出缓冲器的存储器单元的存储器阵列以及行和列解码器，以及耦合到行和列解码器的电压发生器电路。微控制器耦合到命令用户界面。开关指令电路在命令用户界面的控制下，从只读存储器和从芯片到板上t锁存器选择性地向微控制器提供指令，耦合到输入/输出缓冲器。

9. 发明授权

US07345921B2 Method and system for a programming approach for a nonvolatile electronic device 有权
标题翻译：用于非易失性电子设备的编程方法的方法和系统
公开(公告)号：US07345921B2
公开(公告)日：2008-03-18
申请号：US11128939
申请日：2005-05-12
申请人： Stefano Surico , Simone Bartoli , Fabio Tassan Caser , Monica Marziani
发明人： Stefano Surico , Simone Bartoli , Fabio Tassan Caser , Monica Marziani
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： G11C11/5628 , G11C16/3468 , G11C16/3481 , G11C2211/5621 , G11C2211/5634
摘要： Aspects for programming a nonvolatile electronic device include performing an initial verify step of a programming algorithm with an initial type of reference voltage value, and performing one or more subsequent verify steps in the programming algorithm with a second type of reference voltage value. Further included is utilizing a read reference voltage for the initial verify step, wherein desired programming is ensured for a cell that falls out of ideal distribution.
摘要翻译：用于编程非易失性电子设备的方面包括使用初始类型的参考电压值执行编程算法的初始验证步骤，以及使用第二类型的参考电压值来执行编程算法中的一个或多个后续验证步骤。进一步包括利用读取参考电压进行初始验证步骤，其中为理想分布的单元确保期望的编程。

10. 发明授权

US07302518B2 Method and system for managing a suspend request in a flash memory 有权
标题翻译：用于管理闪存中的挂起请求的方法和系统
公开(公告)号：US07302518B2
公开(公告)日：2007-11-27
申请号：US11145457
申请日：2005-06-02
申请人： Stefano Surico , Simone Bartoli , Monica Marziani , Luca Figini
发明人： Stefano Surico , Simone Bartoli , Monica Marziani , Luca Figini
IPC分类号： G06F12/00
CPC分类号： G06F12/0246
摘要： System and method for the managing of suspend requests in flash memory devices. The system includes a microcontroller performing a modify operation on a flash memory array, a memory coupled to the microcontroller and storing suspend sequence code for causing a suspension of the modify operation when executed by the microcontroller, and suspend circuitry that receives a suspend request from a user to suspend the modify operation and starts the execution of the suspend sequence code.
摘要翻译：用于管理闪存设备中的挂起请求的系统和方法。该系统包括微控制器，对闪速存储器阵列执行修改操作，耦合到微控制器的存储器和存储用于在由微控制器执行时引起修改操作暂停的暂停序列代码，以及从微控制器接收暂停请求的暂停电路用户暂停修改操作并开始执行挂起序列代码。

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