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11. 发明授权

US08114736B2 Integrated circuit system with memory system 有权
标题翻译：具有存储系统的集成电路系统
公开(公告)号：US08114736B2
公开(公告)日：2012-02-14
申请号：US11958254
申请日：2007-12-17
申请人： Simon Siu-Sing Chan , Hidehiko Shiraiwa , Kuo-Tung Chang , Angela T. Hui
发明人： Simon Siu-Sing Chan , Hidehiko Shiraiwa , Kuo-Tung Chang , Angela T. Hui
IPC分类号： H01L21/336 , H01L29/788
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/115 , H01L27/11521
摘要： A method for forming an integrated circuit system is provided including forming a memory section having a spacer with a substrate, forming an outer doped region of the memory section in the substrate, forming a barrier metal layer over the spacer, and forming a metal plug over the outer doped region and the barrier metal layer.
摘要翻译：提供了一种用于形成集成电路系统的方法，包括形成具有衬底的间隔物的存储部分，在衬底中形成存储部分的外部掺杂区域，在间隔物上形成阻挡金属层，并形成金属插塞外部掺杂区域和阻挡金属层。

12. 发明申请

US20080150011A1 INTEGRATED CIRCUIT SYSTEM WITH MEMORY SYSTEM 审中-公开
标题翻译：具有存储器系统的集成电路系统
公开(公告)号：US20080150011A1
公开(公告)日：2008-06-26
申请号：US11958646
申请日：2007-12-18
申请人： Simon Siu-Sing Chan , Lei Xue , YouSeok Suh , Amol Ramesh Joshi , Hidehiko Shiraiwa , Harpreet Sachar , Kuo-Tung Chang , Connie Pin Chin Wang , Paul R. Besser , Shenqing Fang , Meng Ding , Takashi Orimoto , Wei Zheng , Fred TK Cheung
发明人： Simon Siu-Sing Chan , Lei Xue , YouSeok Suh , Amol Ramesh Joshi , Hidehiko Shiraiwa , Harpreet Sachar , Kuo-Tung Chang , Connie Pin Chin Wang , Paul R. Besser , Shenqing Fang , Meng Ding , Takashi Orimoto , Wei Zheng , Fred TK Cheung
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11573
摘要： A method for forming an integrated circuit system is provided including forming a substrate having a core region and a periphery region, forming a charge storage stack over the substrate in the core region, forming a gate stack with a stack header having a metal portion over the substrate in the periphery region, and forming a memory system with the stack header over the charge storage stack.
摘要翻译：提供一种用于形成集成电路系统的方法，包括形成具有芯区域和周边区域的衬底，在芯区域中的衬底上形成电荷存储堆叠，形成具有堆叠集管的栅极堆叠，堆叠集束具有金属部分衬底，并且在电荷存储堆叠上形成具有堆叠头的存储器系统。

13. 发明授权

US06537866B1 Method of forming narrow insulating spacers for use in reducing minimum component size 有权
标题翻译：形成用于减小最小部件尺寸的窄绝缘间隔件的方法
公开(公告)号：US06537866B1
公开(公告)日：2003-03-25
申请号：US09691643
申请日：2000-10-18
申请人： Jeffrey A. Shields , Tuan D. Pham , Jusuke Ogura , Bharath Rangarajan , Simon Siu-Sing Chan
发明人： Jeffrey A. Shields , Tuan D. Pham , Jusuke Ogura , Bharath Rangarajan , Simon Siu-Sing Chan
IPC分类号： H01L21338
CPC分类号： H01L29/66583 , H01L21/0331 , H01L21/0338 , H01L21/28123 , H01L21/31144 , H01L21/76802 , H01L21/76885
摘要： A method for forming insulating spacers for separating conducting layers in semiconductor wafer fabrication. The spacers are formed by removing portions of a protective photoresist layer through photolithography, and then through etching of exposed portions of the insulating layer. The spacers allow for fabrication of components that are smaller in size than are obtainable through conventional photolithography methods.
摘要翻译：一种在半导体晶片制造中形成用于分离导电层的绝缘间隔物的方法。通过光刻法去除保护光致抗蚀剂层的部分，然后通过蚀刻绝缘层的暴露部分来形成间隔物。间隔件允许制造尺寸小于通过常规光刻方法可获得的部件的部件。

14. 发明申请

US20090032888A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20090032888A1
公开(公告)日：2009-02-05
申请号：US12251959
申请日：2008-10-15
申请人： William G. En , Thorsten Kammler , Eric N. Paton , Paul R. Besser , Simon Siu-Sing Chan
发明人： William G. En , Thorsten Kammler , Eric N. Paton , Paul R. Besser , Simon Siu-Sing Chan
IPC分类号： H01L29/78
CPC分类号： H01L29/7834 , H01L21/28035 , H01L21/28123 , H01L29/42376 , H01L29/6656 , H01L29/6659 , H01L29/66628
摘要： A sidewall spacer structure is formed adjacent to a gate structure whereby a material forming an outer surface of the sidewall spacer structure contains nitrogen. Subsequent to its formation the sidewall spacer structure is annealed to harden the sidewall spacer structure from a subsequent cleaning process. An epitaxial layer is formed subsequent to the cleaning process.
摘要翻译：侧壁间隔结构邻近门结构形成，由此形成侧壁间隔结构的外表面的材料含有氮。在其形成之后，侧壁间隔结构被退火以使后壁清洁过程的侧壁间隔结构硬化。在清洁处理之后形成外延层。

15. 发明申请

US20080150042A1 INTEGRATED CIRCUIT SYSTEM WITH MEMORY SYSTEM 有权
标题翻译：具有存储器系统的集成电路系统
公开(公告)号：US20080150042A1
公开(公告)日：2008-06-26
申请号：US11958254
申请日：2007-12-17
申请人： Simon Siu-Sing Chan , Hidehiko Shiraiwa , Kuo-Tung Chang , Angela T. Hui
发明人： Simon Siu-Sing Chan , Hidehiko Shiraiwa , Kuo-Tung Chang , Angela T. Hui
IPC分类号： H01L23/48 , H01L21/44
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/115 , H01L27/11521
摘要： A method for forming an integrated circuit system is provided including forming a memory section having a spacer with a substrate, forming an outer doped region of the memory section in the substrate, forming a barrier metal layer over the spacer, and forming a metal plug over the outer doped region and the barrier metal layer.
摘要翻译：提供了一种用于形成集成电路系统的方法，包括形成具有衬底的间隔物的存储部分，在衬底中形成存储部分的外部掺杂区域，在间隔物上形成阻挡金属层，并形成金属插塞外部掺杂区域和阻挡金属层。

16. 发明授权

US06964875B1 Array of gate dielectric structures to measure gate dielectric thickness and parasitic capacitance 失效
标题翻译：用于测量栅介质厚度和寄生电容的栅介质结构阵列
公开(公告)号：US06964875B1
公开(公告)日：2005-11-15
申请号：US10962582
申请日：2004-10-13
申请人： William G. En , Mark W. Michael , Hai Hong Wang , Simon Siu-Sing Chan
发明人： William G. En , Mark W. Michael , Hai Hong Wang , Simon Siu-Sing Chan
IPC分类号： H01L21/66 , H01L21/8234 , H01L23/544 , H01L27/08 , H01L29/76 , H01L31/119
CPC分类号： H01L22/34 , H01L21/823437 , H01L27/0811 , H01L2924/0002 , H01L2924/00
摘要： Accurate determination of gate dielectric thickness is required to produce high-reliability and high-performance ultra-thin gate dielectric semiconductor devices. Large area gate dielectric capacitors with ultra-thin gate dielectric layers suffer from high gate leakage, which prevents the accurate measurement of gate dielectric thickness. Accurate measurement of gate dielectric thickness of smaller area gate dielectric capacitors is hindered by the relatively large parasitic capacitance of the smaller area capacitors. The formation of first and second dummy structures on a wafer allow the accurate determination of gate dielectric thickness. First and second dummy structures are formed that are substantially similar to the gate dielectric capacitors except that the first dummy structures are formed without the second electrode of the capacitor and the second dummy structures are formed without the first electrode of the capacitor structure. The capacitance, and therefore thickness, of the gate dielectric capacitor is determined by subtracting the parasitic capacitances measured at the first and second dummy structures.
摘要翻译：制造高可靠性和高性能超薄栅极电介质半导体器件需要精确确定栅极电介质厚度。具有超薄栅极介电层的大面积栅极介质电容器具有高栅极泄漏，这阻止了栅极电介质厚度的精确测量。较小面积的电介质电容器的栅极电介质厚度的精确测量受到较小面积电容器的相对大的寄生电容的阻碍。在晶片上形成第一和第二虚拟结构允许准确地确定栅极电介质厚度。形成基本上类似于栅极介电电容器的第一和第二虚拟结构，除了第一虚拟结构形成而没有电容器的第二电极，并且第二虚拟结构形成而没有电容器结构的第一电极。通过减去在第一和第二虚拟结构处测量的寄生电容来确定栅极介电电容器的电容，并因此确定厚度。

17. 发明申请

US20080153224A1 INTEGRATED CIRCUIT SYSTEM WITH MEMORY SYSTEM 审中-公开
标题翻译：具有存储器系统的集成电路系统
公开(公告)号：US20080153224A1
公开(公告)日：2008-06-26
申请号：US11735229
申请日：2007-04-13
申请人： Connie Pin Chin Wang , Simon Siu-Sing Chan , Angela T. Hui , Paul R. Besser , Shenqing Fang
发明人： Connie Pin Chin Wang , Simon Siu-Sing Chan , Angela T. Hui , Paul R. Besser , Shenqing Fang
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L27/115
摘要： An integrated circuit system is provided including forming a memory section having a spacer with a substrate, forming an outer doped region of the memory section in the substrate, forming a contact on the outer doped region, thinning the contact for forming a thinned contact, and forming a metal plug on the thinned contact.
摘要翻译：提供了一种集成电路系统，包括形成具有衬底的间隔物的存储部分，在衬底中形成存储部分的外部掺杂区域，在外部掺杂区域上形成接触，减少接触以形成变薄的接触，以及在变薄的触点上形成金属插头。

18. 发明授权

US06737337B1 Method of preventing dopant depletion in surface semiconductor layer of semiconductor-on-insulator (SOI) device 有权
标题翻译：防止绝缘体上半导体（SOI）器件的表面半导体层中的掺杂剂消耗的方法
公开(公告)号：US06737337B1
公开(公告)日：2004-05-18
申请号：US10134972
申请日：2002-04-29
申请人： Simon Siu-Sing Chan , Qi Xiang
发明人： Simon Siu-Sing Chan , Qi Xiang
IPC分类号： H01L2130
CPC分类号： H01L21/76254
摘要： A method of manufacturing a semiconductor device includes forming a buried insulator layer of a semiconductor-on-insulator (SOI) wafer with a dopant material, such as boron, therein. The insulator material with the dopant material may be formed by a number of methods, for example by thermal oxidation of a semiconductor wafer in the presence of an atmosphere containing the dopant material, by co-deposition of the insulator material and the dopant material, or by co-implantation of an insulator material and the dopant material. The dopant material may be the same as a dopant material in at least a region (e.g., a source, drain, or channel region) of a semiconductor material layer which overlies the insulator layer. The dopant material in the buried insulator layer may advantageously reduce the tendency of dopant material to migrate from the overlying material to the insulator layer, such as during manufacturing operations involving heating.
摘要翻译：一种制造半导体器件的方法包括在其中用诸如硼的掺杂剂材料形成绝缘体上半导体（SOI）晶片的掩埋绝缘体层。具有掺杂剂材料的绝缘体材料可以通过多种方法形成，例如通过在包含掺杂剂材料的气氛存在的情况下通过半导体晶片的热氧化，通过绝缘体材料和掺杂剂材料的共沉积，或通过共注入绝缘体材料和掺杂剂材料。掺杂剂材料可以与至少覆盖绝缘体层的半导体材料层的区域（例如，源极，漏极或沟道区）中的掺杂剂材料相同。掩埋绝缘体层中的掺杂剂材料可以有利地降低掺杂剂材料从覆盖材料迁移到绝缘体层的趋势，例如在涉及加热的制造操作期间。

19. 发明授权

US08598005B2 Method and manufacture for embedded flash to achieve high quality spacers for core and high voltage devices and low temperature spacers for high performance logic devices 有权
标题翻译：用于嵌入式闪存的方法和制造，以实现用于高性能逻辑器件的核心和高电压器件以及低温间隔物的高质量间隔物
公开(公告)号：US08598005B2
公开(公告)日：2013-12-03
申请号：US13185390
申请日：2011-07-18
申请人： Simon Siu-Sing Chan , Hidehiko Shiraiwa , Chuan Lin , Lei Xue , Kenichi Ohtsuka , Angela Tai Hui
发明人： Simon Siu-Sing Chan , Hidehiko Shiraiwa , Chuan Lin , Lei Xue , Kenichi Ohtsuka , Angela Tai Hui
IPC分类号： H01L29/772
CPC分类号： H01L29/6656 , H01L21/28282 , H01L21/823418 , H01L21/823462 , H01L21/823468 , H01L27/11573 , H01L29/6653
摘要： A method and manufacture for memory device fabrication is provided. Spacer formation and junction formation is performed on both: a memory cell region in a core section of a memory device in fabrication, and a high-voltage device region in a periphery section of the memory device in fabrication. The spacer formation and junction formation on both the memory cell region and the high-voltage device region includes performing a rapid thermal anneal. After performing the spacer formation and junction formation on both the memory cell region and the high-voltage device region, spacer formation and junction formation is performed on a low-voltage device region in the periphery section.
摘要翻译：提供了一种用于存储器件制造的方法和制造。在制造中的存储器件的芯部中的存储单元区域和存储器件的外围部分中的高电压器件区域两者都执行间隔物形成和结形成。在存储单元区域和高压器件区域上的间隔物形成和结形成包括执行快速热退火。在对存储单元区域和高压器件区域进行间隔物形成和结形成之后，在周边部分的低电压器件区域上进行间隔物形成和结形成。

20. 发明申请

US20080142874A1 INTEGRATED CIRCUIT SYSTEM WITH IMPLANT OXIDE 审中-公开
标题翻译：具有氧化铟的集成电路系统
公开(公告)号：US20080142874A1
公开(公告)日：2008-06-19
申请号：US11611860
申请日：2006-12-16
申请人： Shenqing Fang , Rinji Sugino , Jayendra Bhakta , Takashi Orimoto , Hiroyuki Nansei , Yukio Hayakawa , Hidehiko Shiraiwa , Takayuki Maruyama , Kuo-Tung Chang , YouSeok Suh , Amol Ramesh Joshi , Harpreet Sachar , Simon Siu-Sing Chan
发明人： Shenqing Fang , Rinji Sugino , Jayendra Bhakta , Takashi Orimoto , Hiroyuki Nansei , Yukio Hayakawa , Hidehiko Shiraiwa , Takayuki Maruyama , Kuo-Tung Chang , YouSeok Suh , Amol Ramesh Joshi , Harpreet Sachar , Simon Siu-Sing Chan
IPC分类号： H01L29/792 , H01L21/3205
CPC分类号： H01L29/792 , H01L29/66833
摘要： A method for forming an integrated circuit system is provided including forming a substrate; forming a stack over the substrate, the stack having a sidewall and formed from a charge trap layer and a semi-conducting layer; and slot plane antenna oxidizing the stack for forming a protection enclosure having a protection layer along the sidewall.
摘要翻译：提供一种用于形成集成电路系统的方法，包括：形成衬底; 在衬底上形成堆叠，所述堆叠具有侧壁并由电荷陷阱层和半导体层形成; 以及缝隙平面天线，用于氧化该叠层以形成具有沿该侧壁的保护层的保护罩。

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