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1. 发明授权

US06964875B1 Array of gate dielectric structures to measure gate dielectric thickness and parasitic capacitance 失效
标题翻译：用于测量栅介质厚度和寄生电容的栅介质结构阵列
公开(公告)号：US06964875B1
公开(公告)日：2005-11-15
申请号：US10962582
申请日：2004-10-13
申请人： William G. En , Mark W. Michael , Hai Hong Wang , Simon Siu-Sing Chan
发明人： William G. En , Mark W. Michael , Hai Hong Wang , Simon Siu-Sing Chan
IPC分类号： H01L21/66 , H01L21/8234 , H01L23/544 , H01L27/08 , H01L29/76 , H01L31/119
CPC分类号： H01L22/34 , H01L21/823437 , H01L27/0811 , H01L2924/0002 , H01L2924/00
摘要： Accurate determination of gate dielectric thickness is required to produce high-reliability and high-performance ultra-thin gate dielectric semiconductor devices. Large area gate dielectric capacitors with ultra-thin gate dielectric layers suffer from high gate leakage, which prevents the accurate measurement of gate dielectric thickness. Accurate measurement of gate dielectric thickness of smaller area gate dielectric capacitors is hindered by the relatively large parasitic capacitance of the smaller area capacitors. The formation of first and second dummy structures on a wafer allow the accurate determination of gate dielectric thickness. First and second dummy structures are formed that are substantially similar to the gate dielectric capacitors except that the first dummy structures are formed without the second electrode of the capacitor and the second dummy structures are formed without the first electrode of the capacitor structure. The capacitance, and therefore thickness, of the gate dielectric capacitor is determined by subtracting the parasitic capacitances measured at the first and second dummy structures.
摘要翻译：制造高可靠性和高性能超薄栅极电介质半导体器件需要精确确定栅极电介质厚度。具有超薄栅极介电层的大面积栅极介质电容器具有高栅极泄漏，这阻止了栅极电介质厚度的精确测量。较小面积的电介质电容器的栅极电介质厚度的精确测量受到较小面积电容器的相对大的寄生电容的阻碍。在晶片上形成第一和第二虚拟结构允许准确地确定栅极电介质厚度。形成基本上类似于栅极介电电容器的第一和第二虚拟结构，除了第一虚拟结构形成而没有电容器的第二电极，并且第二虚拟结构形成而没有电容器结构的第一电极。通过减去在第一和第二虚拟结构处测量的寄生电容来确定栅极介电电容器的电容，并因此确定厚度。

2. 发明授权

US06841832B1 Array of gate dielectric structures to measure gate dielectric thickness and parasitic capacitance 失效
公开(公告)号：US06841832B1
公开(公告)日：2005-01-11
申请号：US10021497
申请日：2001-12-19
申请人： William G. En , Mark W. Michael , Hai Hong Wang , Simon Siu-Sing Chan
发明人： William G. En , Mark W. Michael , Hai Hong Wang , Simon Siu-Sing Chan
IPC分类号： H01L21/66 , H01L21/8234 , H01L23/544 , H01L27/08 , H01L29/76 , H01L31/119
CPC分类号： H01L22/34 , H01L21/823437 , H01L27/0811 , H01L2924/0002 , H01L2924/00
摘要： Accurate determination of gate dielectric thickness is required to produce high-reliability and high-performance ultra-thin gate dielectric semiconductor devices. Large area gate dielectric capacitors with ultra-thin gate dielectric layers suffer from high gate leakage, which prevents the accurate measurement of gate dielectric thickness. Accurate measurement of gate dielectric thickness of smaller area gate dielectric capacitors is hindered by the relatively large parasitic capacitance of the smaller area capacitors. The formation of first and second dummy structures on a wafer allow the accurate determination of gate dielectric thickness. First and second dummy structures are formed that are substantially similar to the gate dielectric capacitors except that the first dummy structures are formed without the second electrode of the capacitor and the second dummy structures are formed without the first electrode of the capacitor structure. The capacitance, and therefore thickness, of the gate dielectric capacitor is determined by subtracting the parasitic capacitances measured at the first and second dummy structures.

3. 发明授权

US07456062B1 Method of forming a semiconductor device 有权
公开(公告)号：US07456062B1
公开(公告)日：2008-11-25
申请号：US11209871
申请日：2005-08-23
申请人： William G. En , Thorsten Kammler , Eric N. Paton , Paul R. Besser , Simon Siu-Sing Chan
发明人： William G. En , Thorsten Kammler , Eric N. Paton , Paul R. Besser , Simon Siu-Sing Chan
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/3205 , H01L21/4763
CPC分类号： H01L29/7834 , H01L21/28035 , H01L21/28123 , H01L29/42376 , H01L29/6656 , H01L29/6659 , H01L29/66628
摘要： A sidewall spacer structure is formed adjacent to a gate structure whereby a material forming an outer surface of the sidewall spacer structure contains nitrogen. Subsequent to its formation the sidewall spacer structure is annealed to harden the sidewall spacer structure from a subsequent cleaning process. An epitaxial layer is formed subsequent to the cleaning process.

4. 发明申请

US20090032888A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20090032888A1
公开(公告)日：2009-02-05
申请号：US12251959
申请日：2008-10-15
申请人： William G. En , Thorsten Kammler , Eric N. Paton , Paul R. Besser , Simon Siu-Sing Chan
发明人： William G. En , Thorsten Kammler , Eric N. Paton , Paul R. Besser , Simon Siu-Sing Chan
IPC分类号： H01L29/78
CPC分类号： H01L29/7834 , H01L21/28035 , H01L21/28123 , H01L29/42376 , H01L29/6656 , H01L29/6659 , H01L29/66628
摘要： A sidewall spacer structure is formed adjacent to a gate structure whereby a material forming an outer surface of the sidewall spacer structure contains nitrogen. Subsequent to its formation the sidewall spacer structure is annealed to harden the sidewall spacer structure from a subsequent cleaning process. An epitaxial layer is formed subsequent to the cleaning process.
摘要翻译：侧壁间隔结构邻近门结构形成，由此形成侧壁间隔结构的外表面的材料含有氮。在其形成之后，侧壁间隔结构被退火以使后壁清洁过程的侧壁间隔结构硬化。在清洁处理之后形成外延层。

5. 发明授权

US06713357B1 Method to reduce parasitic capacitance of MOS transistors 有权
标题翻译：降低MOS晶体管寄生电容的方法
公开(公告)号：US06713357B1
公开(公告)日：2004-03-30
申请号：US10023348
申请日：2001-12-20
申请人： Hai Hong Wang , Mark W. Michael , Wen-Jie Qi , William G. En , John G. Pellerin
发明人： Hai Hong Wang , Mark W. Michael , Wen-Jie Qi , William G. En , John G. Pellerin
IPC分类号： H01L21336
CPC分类号： H01L29/6653 , H01L21/76834 , H01L23/3171 , H01L29/4983 , H01L29/6656 , H01L2924/0002 , H01L2924/19041 , H01L2924/00
摘要： The present invention relates to a method for fabricating MOS transistors with reduced parasitic capacitance. The present invention is based upon recognition that the parasitic capacitance of MOS transistors, such as are utilized in the manufacture of CMOS and IC devices, can be reduced by use of sidewall spacers having an optimized cross-sectional shape, in conjunction with an overlying insulator layer comprised of a low-k dielectric material.
摘要翻译：本发明涉及制造具有减小的寄生电容的MOS晶体管的方法。本发明基于通过使用具有优化的横截面形状的侧壁间隔件与上覆绝缘体（例如CMOS）和IC器件的制造中的MOS晶体管的寄生电容相结合的方式，层由低k电介质材料组成。

6. 发明授权

US06867130B1 Enhanced silicidation of polysilicon gate electrodes 有权
标题翻译：增强多晶硅栅电极的硅化
公开(公告)号：US06867130B1
公开(公告)日：2005-03-15
申请号：US10445936
申请日：2003-05-28
申请人： Olov B. Karlsson , Simon S. Chan , William G. En , Mark W. Michael
发明人： Olov B. Karlsson , Simon S. Chan , William G. En , Mark W. Michael
IPC分类号： H01L21/28 , H01L21/285 , H01L21/336 , H01L21/44 , H01L21/4763 , H01L29/423 , H01L29/78
CPC分类号： H01L29/66507 , H01L21/28114 , H01L21/28518 , H01L29/42376 , H01L29/6659 , H01L29/7833
摘要： Semiconductor devices exhibiting reduced gate resistance and reduced silicide spiking in source/drain regions are fabricated by forming thin metal silicide layers on the gate electrode and source/drain regions and then selectively resilicidizing the gate electrodes. Embodiments include forming the thin metal silicide layers on the polysilicon gate electrodes and source/drain regions, depositing a dielectric gap filling layer, as by high density plasma deposition, etching back to selectively expose the silicidized polysilicon gate electrodes and resilicidizing the polysilicon gate electrodes to increase the thickness of the metal silicide layers thereon. Embodiments further include resilicidizing the polysilicon gate electrodes including a portion of the upper side surfaces forming mushroom shaped metal silicide layers.
摘要翻译：通过在栅极电极和源极/漏极区域上形成薄金属硅化物层，然后选择性地使栅电极重新硅化，来制造在源极/漏极区域中显示出降低的栅极电阻和减少的硅化物尖峰的半导体器件。实施例包括在多晶硅栅极电极和源极/漏极区域上形成薄金属硅化物层，通过高密度等离子体沉积沉积介电间隙填充层，回蚀刻以选择性地暴露硅化多晶硅栅电极并使多晶硅栅电极重新硅化增加其上的金属硅化物层的厚度。实施例还包括重新硅化多晶硅栅电极，其包括形成蘑菇状金属硅化物层的上侧表面的一部分。

7. 发明授权

US06764917B1 SOI device with different silicon thicknesses 失效
标题翻译：具有不同硅厚度的SOI器件
公开(公告)号：US06764917B1
公开(公告)日：2004-07-20
申请号：US10023350
申请日：2001-12-20
申请人： Darin A. Chan , William G. En , John G. Pellerin , Mark W. Michael
发明人： Darin A. Chan , William G. En , John G. Pellerin , Mark W. Michael
IPC分类号： H01L2176
CPC分类号： H01L21/84 , H01L27/1203
摘要： A method of manufacturing a semiconductor device includes providing a silicon semiconductor layer over an insulating layer, and partially removing a first portion of the silicon layer. The silicon layer includes the first portion and a second portion, and a thickness of the second portion is greater than a thickness of the first portion. Initially, the first and second portions of the silicon layer initially can have the same thickness. A semiconductor device is also disclosed.
摘要翻译：制造半导体器件的方法包括在绝缘层上提供硅半导体层，并部分地去除硅层的第一部分。硅层包括第一部分和第二部分，第二部分的厚度大于第一部分的厚度。最初，硅层的第一和第二部分最初可以具有相同的厚度。还公开了一种半导体器件。

8. 发明授权

US06780776B1 Nitride offset spacer to minimize silicon recess by using poly reoxidation layer as etch stop layer 有权
标题翻译：氮化物偏移间隔物，通过使用多重再氧化层作为蚀刻停止层来最小化硅凹槽
公开(公告)号：US06780776B1
公开(公告)日：2004-08-24
申请号：US10023328
申请日：2001-12-20
申请人： Wen-Jie Qi , John G. Pellerin , William G. En , Mark W. Michael , Darin A. Chan
发明人： Wen-Jie Qi , John G. Pellerin , William G. En , Mark W. Michael , Darin A. Chan
IPC分类号： H01L21302
CPC分类号： H01L29/6659 , H01L21/28247 , H01L21/31116 , H01L21/3185 , H01L29/6656
摘要： A method of forming a semiconductor device provides a gate electrode on a substrate and forms a polysilicon reoxidation layer over the substrate and the gate electrode. A nitride layer is deposited over the polysilicon reoxidation layer and anisotropically etched The etching stops on the polysilicon reoxidation layer, with nitride offset spacers being formed on the gate electrode. The use of the polysilicon reoxidation layer as an etch stop layer prevents the gouging of the silicon substrate underneath the nitride layer, while allowing the offset spacers to be formed.
摘要翻译：形成半导体器件的方法在衬底上提供栅电极，并在衬底和栅电极上形成多晶硅再氧化层。氮化物层沉积在多晶硅再氧化层上并各向异性蚀刻。多晶硅再氧化层上的蚀刻停止，在栅电极上形成氮化物偏移间隔物。使用多晶硅再氧化层作为蚀刻停止层防止在氮化物层下方的硅衬底的气蚀，同时允许形成偏移间隔物。

9. 发明申请

US20080206963A1 Cleaving process to fabricate multilayered substrates using low implantation doses 审中-公开
公开(公告)号：US20080206963A1
公开(公告)日：2008-08-28
申请号：US12148318
申请日：2008-04-18
申请人： Francois J. Henley , Michael A. Bryan , William G. En
发明人： Francois J. Henley , Michael A. Bryan , William G. En
IPC分类号： H01L21/304
CPC分类号： H01L21/26506 , H01L21/2658 , H01L21/76251 , H01L21/76254
摘要： A method of forming substrates, e.g., silicon on insulator, silicon on silicon. The method includes providing a donor substrate, e.g., silicon wafer. The method also includes forming a cleave layer on the donor substrate that contains the cleave plane, the plane of eventual separation. In a specific embodiment, the cleave layer comprising silicon germanium. The method also includes forming a device layer (e.g., epitaxial silicon) on the cleave layer. The method also includes introducing particles into the cleave layer to add stress in the cleave layer. The particles within the cleave layer are then redistributed to form a high concentration region of the particles in the vicinity of the cleave plane, where the redistribution of the particles is carried out in a manner substantially free from microbubble or microcavity formation of the particles in the cleave plane. That is, the particles are generally at a low dose, which is defined herein as a lack of microbubble or microcavity formation in the cleave plane. The method also includes providing selected energy to the donor substrate to cleave the device layer from the cleave layer at the cleave plane, whereupon the selected energy is applied to create a controlled cleaving action to remove the device layer from a portion of the cleave layer in a controlled manner.

10. 发明授权

US07402207B1 Method and apparatus for controlling the thickness of a selective epitaxial growth layer 有权
标题翻译：用于控制选择性外延生长层厚度的方法和装置
公开(公告)号：US07402207B1
公开(公告)日：2008-07-22
申请号：US10839378
申请日：2004-05-05
申请人： Paul R. Besser , Eric N. Paton , William G. En
发明人： Paul R. Besser , Eric N. Paton , William G. En
IPC分类号： C30B21/04
CPC分类号： C30B25/16 , G01B11/0616 , H01L21/67167 , H01L21/67207 , H01L21/67745 , Y10T117/1004 , Y10T117/1008
摘要： Methods and systems for permitting thickness control of the selective epitaxial growth (SEG) layer in a semiconductor manufacturing process, for example raised source/drain applications in CMOS technologies, are presented. These methods and systems provide the capability to measure the thickness of an SEG film in-situ utilizing optical ellipsometry equipment during or after SEG layer growth, prior to removing the wafer from the SEG growth tool. Optical ellipsometry equipment can be integrated into the SEG platform and control software, thus providing automated process control (APC) capability for SEG thickness. The integration of the ellipsometry equipment may be varied, dependent upon the needs of the fabrication facility, e.g., integration to provide ellipsometer monitoring of a single process tool, or multiple tool monitoring, among other configurations.
摘要翻译：提出了在半导体制造工艺中允许厚度控制选择性外延生长（SEG）层的方法和系统，例如CMOS技术中的升高的源/漏应用。这些方法和系统提供了在从SEG生长工具移除晶片之前在SEG层生长期间或之后使用光学椭偏仪设备原位测量SEG膜的厚度的能力。光学椭圆测量设备可以集成到SEG平台和控制软件中，从而为SEG厚度提供自动化过程控制（APC）能力。椭圆测量设备的集成可以根据制造设施的需要而变化，例如集成以提供单个处理工具的椭偏仪监控，或者多个工具监视以及其他配置。

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