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1. 发明授权

US08114736B2 Integrated circuit system with memory system 有权
标题翻译：具有存储系统的集成电路系统
公开(公告)号：US08114736B2
公开(公告)日：2012-02-14
申请号：US11958254
申请日：2007-12-17
申请人： Simon Siu-Sing Chan , Hidehiko Shiraiwa , Kuo-Tung Chang , Angela T. Hui
发明人： Simon Siu-Sing Chan , Hidehiko Shiraiwa , Kuo-Tung Chang , Angela T. Hui
IPC分类号： H01L21/336 , H01L29/788
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/115 , H01L27/11521
摘要： A method for forming an integrated circuit system is provided including forming a memory section having a spacer with a substrate, forming an outer doped region of the memory section in the substrate, forming a barrier metal layer over the spacer, and forming a metal plug over the outer doped region and the barrier metal layer.
摘要翻译：提供了一种用于形成集成电路系统的方法，包括形成具有衬底的间隔物的存储部分，在衬底中形成存储部分的外部掺杂区域，在间隔物上形成阻挡金属层，并形成金属插塞外部掺杂区域和阻挡金属层。

2. 发明申请

US20080150042A1 INTEGRATED CIRCUIT SYSTEM WITH MEMORY SYSTEM 有权
标题翻译：具有存储器系统的集成电路系统
公开(公告)号：US20080150042A1
公开(公告)日：2008-06-26
申请号：US11958254
申请日：2007-12-17
申请人： Simon Siu-Sing Chan , Hidehiko Shiraiwa , Kuo-Tung Chang , Angela T. Hui
发明人： Simon Siu-Sing Chan , Hidehiko Shiraiwa , Kuo-Tung Chang , Angela T. Hui
IPC分类号： H01L23/48 , H01L21/44
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/115 , H01L27/11521
摘要： A method for forming an integrated circuit system is provided including forming a memory section having a spacer with a substrate, forming an outer doped region of the memory section in the substrate, forming a barrier metal layer over the spacer, and forming a metal plug over the outer doped region and the barrier metal layer.
摘要翻译：提供了一种用于形成集成电路系统的方法，包括形成具有衬底的间隔物的存储部分，在衬底中形成存储部分的外部掺杂区域，在间隔物上形成阻挡金属层，并形成金属插塞外部掺杂区域和阻挡金属层。

3. 发明申请

US20080142874A1 INTEGRATED CIRCUIT SYSTEM WITH IMPLANT OXIDE 审中-公开
标题翻译：具有氧化铟的集成电路系统
公开(公告)号：US20080142874A1
公开(公告)日：2008-06-19
申请号：US11611860
申请日：2006-12-16
申请人： Shenqing Fang , Rinji Sugino , Jayendra Bhakta , Takashi Orimoto , Hiroyuki Nansei , Yukio Hayakawa , Hidehiko Shiraiwa , Takayuki Maruyama , Kuo-Tung Chang , YouSeok Suh , Amol Ramesh Joshi , Harpreet Sachar , Simon Siu-Sing Chan
发明人： Shenqing Fang , Rinji Sugino , Jayendra Bhakta , Takashi Orimoto , Hiroyuki Nansei , Yukio Hayakawa , Hidehiko Shiraiwa , Takayuki Maruyama , Kuo-Tung Chang , YouSeok Suh , Amol Ramesh Joshi , Harpreet Sachar , Simon Siu-Sing Chan
IPC分类号： H01L29/792 , H01L21/3205
CPC分类号： H01L29/792 , H01L29/66833
摘要： A method for forming an integrated circuit system is provided including forming a substrate; forming a stack over the substrate, the stack having a sidewall and formed from a charge trap layer and a semi-conducting layer; and slot plane antenna oxidizing the stack for forming a protection enclosure having a protection layer along the sidewall.
摘要翻译：提供一种用于形成集成电路系统的方法，包括：形成衬底; 在衬底上形成堆叠，所述堆叠具有侧壁并由电荷陷阱层和半导体层形成; 以及缝隙平面天线，用于氧化该叠层以形成具有沿该侧壁的保护层的保护罩。

4. 发明申请

US20080150011A1 INTEGRATED CIRCUIT SYSTEM WITH MEMORY SYSTEM 审中-公开
标题翻译：具有存储器系统的集成电路系统
公开(公告)号：US20080150011A1
公开(公告)日：2008-06-26
申请号：US11958646
申请日：2007-12-18
申请人： Simon Siu-Sing Chan , Lei Xue , YouSeok Suh , Amol Ramesh Joshi , Hidehiko Shiraiwa , Harpreet Sachar , Kuo-Tung Chang , Connie Pin Chin Wang , Paul R. Besser , Shenqing Fang , Meng Ding , Takashi Orimoto , Wei Zheng , Fred TK Cheung
发明人： Simon Siu-Sing Chan , Lei Xue , YouSeok Suh , Amol Ramesh Joshi , Hidehiko Shiraiwa , Harpreet Sachar , Kuo-Tung Chang , Connie Pin Chin Wang , Paul R. Besser , Shenqing Fang , Meng Ding , Takashi Orimoto , Wei Zheng , Fred TK Cheung
IPC分类号： H01L27/115 , H01L21/8247
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/11573
摘要： A method for forming an integrated circuit system is provided including forming a substrate having a core region and a periphery region, forming a charge storage stack over the substrate in the core region, forming a gate stack with a stack header having a metal portion over the substrate in the periphery region, and forming a memory system with the stack header over the charge storage stack.
摘要翻译：提供一种用于形成集成电路系统的方法，包括形成具有芯区域和周边区域的衬底，在芯区域中的衬底上形成电荷存储堆叠，形成具有堆叠集管的栅极堆叠，堆叠集束具有金属部分衬底，并且在电荷存储堆叠上形成具有堆叠头的存储器系统。

5. 发明申请

US20080023751A1 INTEGRATED CIRCUIT MEMORY SYSTEM EMPLOYING SILICON RICH LAYERS 有权
标题翻译：集成电路记忆系统采用硅胶层
公开(公告)号：US20080023751A1
公开(公告)日：2008-01-31
申请号：US11461131
申请日：2006-07-31
申请人： Amol Ramesh Joshi , Harpreet Sachar , YouSeok Suh , Shenqing Fang , Chih-Yuh Yang , Lovejeet Singh , David H. Matsumoto , Hidehiko Shiraiwa , Kuo-Tung Chang , Scott A. Bell , Allison Holbrook , Satoshi Torii
发明人： Amol Ramesh Joshi , Harpreet Sachar , YouSeok Suh , Shenqing Fang , Chih-Yuh Yang , Lovejeet Singh , David H. Matsumoto , Hidehiko Shiraiwa , Kuo-Tung Chang , Scott A. Bell , Allison Holbrook , Satoshi Torii
IPC分类号： H01L29/792
CPC分类号： H01L27/11568 , H01L21/3081 , H01L21/76224 , H01L27/115 , H01L29/66833
摘要： An integrated circuit memory system that includes: providing a substrate; forming a silicon rich charge storage layer over the substrate; forming a first isolation trench through the silicon rich charge storage layer in a first direction; and forming a second isolation trench through the silicon rich charge storage layer in a second direction.
摘要翻译：一种集成电路存储器系统，包括：提供衬底; 在所述衬底上形成富硅电荷存储层; 通过富硅电荷存储层沿第一方向形成第一隔离沟槽; 以及在第二方向上通过富硅电荷存储层形成第二隔离沟槽。

6. 发明授权

US06927129B1 Narrow wide spacer 有权
标题翻译：狭窄的间距
公开(公告)号：US06927129B1
公开(公告)日：2005-08-09
申请号：US10821312
申请日：2004-04-08
申请人： Yu Sun , Kuo-Tung Chang , Angela T. Hui , Shenqing Fang
发明人： Yu Sun , Kuo-Tung Chang , Angela T. Hui , Shenqing Fang
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/105
CPC分类号： H01L29/6656 , H01L27/105 , H01L27/11526 , H01L27/11534
摘要： A method for fabricating a semiconductor device. Specifically, A method of manufacturing a semiconductor device comprising: depositing a first oxide layer over a periphery transistor comprising a gate stack, a drain side sidewall and a source side sidewall and over a core transistor comprising a gate stack, a source side sidewall and a drain side sidewall; etching the first oxide layer wherein a portion of the first oxide layer remains on the source side sidewall and on the drain side sidewall of the periphery transistor and on the source side sidewall and on the drain side sidewall of the core transistor; etching the first oxide layer from the source side sidewall of the core transistor; depositing a second oxide layer over the periphery transistor and the core transistor; and etching the second oxide layer wherein a portion of the second oxide layer remains on the first oxide layer formed on the source side sidewall and on the drain side sidewall of the periphery transistor and wherein the second oxide layer remains on the source side sidewall and on the drain side sidewall of the core transistor.
摘要翻译：一种半导体器件的制造方法。具体地说，一种制造半导体器件的方法，包括：在包括栅极堆叠，漏极侧壁和源极侧壁的外围晶体管上沉积第一氧化物层，以及包括栅极堆叠，源极侧壁和排水侧壁蚀刻第一氧化物层，其中第一氧化物层的一部分保留在外围晶体管的源极侧壁和漏极侧壁上，并且在芯晶体管的源极侧壁和漏极侧侧壁上残留; 从芯晶体管的源极侧壁蚀刻第一氧化物层; 在外围晶体管和芯晶体管上沉积第二氧化物层; 以及蚀刻所述第二氧化物层，其中所述第二氧化物层的一部分保留在形成在所述外围晶体管的源极侧壁和漏极侧壁上的第一氧化物层上，并且其中所述第二氧化物层保留在所述源侧侧壁上，芯晶体管的漏极侧壁。

7. 发明申请

US20080150000A1 MEMORY SYSTEM WITH SELECT GATE ERASE 审中-公开
标题翻译：具有选择栅格擦除的存储器系统
公开(公告)号：US20080150000A1
公开(公告)日：2008-06-26
申请号：US11614839
申请日：2006-12-21
申请人： YouSeok Suh , Hidehiko Shiraiwa , Kuo-Tung Chang , Lei Xue , Meng Ding , Amol Ramesh Joshi , Shenqing Fang
发明人： YouSeok Suh , Hidehiko Shiraiwa , Kuo-Tung Chang , Lei Xue , Meng Ding , Amol Ramesh Joshi , Shenqing Fang
IPC分类号： H01L29/792 , H01L21/28
CPC分类号： H01L29/792 , H01L29/40117
摘要： A memory system includes a substrate, forming a first insulator over the substrate, forming a charge trap layer, having a composition for setting a predetermined electrical charge level, over the first insulator, and forming a second insulator over the charge trap layer.
摘要翻译：存储器系统包括：衬底，在衬底上形成第一绝缘体，在第一绝缘体上形成具有用于设定预定电荷水平的组成的电荷陷阱层，以及在电荷陷阱层上形成第二绝缘体。

8. 发明授权

US08642441B1 Self-aligned STI with single poly for manufacturing a flash memory device 有权
标题翻译：自对准STI与单个poly制造闪存设备
公开(公告)号：US08642441B1
公开(公告)日：2014-02-04
申请号：US11639667
申请日：2006-12-15
申请人： Tim Thurgate , Shenqing Fang , Kuo-Tung Chang , YouSeok Suh , Meng Ding , Hidehiko Shiraiwa , Amol Joshi , Harpreet Sachar , David Matsumoto , Lovejeet Singh , Chih-Yuh Yang
发明人： Tim Thurgate , Shenqing Fang , Kuo-Tung Chang , YouSeok Suh , Meng Ding , Hidehiko Shiraiwa , Amol Joshi , Harpreet Sachar , David Matsumoto , Lovejeet Singh , Chih-Yuh Yang
IPC分类号： H01L21/76
CPC分类号： H01L27/11563 , H01L21/28282 , H01L21/76232 , H01L21/823481 , H01L27/11568 , H01L29/66833
摘要： A method for fabricating a memory device with a self-aligned trap layer and rounded active region corners is disclosed. In the present invention, an STI process is performed before any of the charge-trapping and top-level layers are formed. Immediately after the STI process, the sharp corners of the active regions are exposed. Because these sharp corners are exposed at this time, they are available to be rounded through any number of known rounding techniques. Rounding the corners improves the performance characteristics of the memory device. Subsequent to the rounding process, the charge-trapping structure and other layers can be formed by a self-aligned process.
摘要翻译：公开了一种用于制造具有自对准陷阱层和圆形有源区域拐角的存储器件的方法。在本发明中，在形成电荷捕获层和顶层之前进行STI工艺。 STI过程之后立即暴露有源区域的尖角。因为这些尖角在这个时候被曝光，所以它们可以通过任何数量的已知的四舍五入技术进行四舍五入。四舍五入改善了存储设备的性能特征。在舍入处理之后，电荷捕获结构和其它层可以通过自对准工艺形成。

9. 发明授权

US08143661B2 Memory cell system with charge trap 有权
标题翻译：带电荷陷阱的记忆体系统
公开(公告)号：US08143661B2
公开(公告)日：2012-03-27
申请号：US11539984
申请日：2006-10-10
申请人： Shenqing Fang , Rinji Sugino , Jayendra Bhakta , Takashi Orimoto , Hiroyuki Nansei , Yukio Hayakawa , Takayuki Maruyama , Hidehiko Shiraiwa , Kuo-Tung Chang , Lei Xue , Meng Ding , Amol Ramesh Joshi , YouSeok Suh , Harpreet Sachar
发明人： Shenqing Fang , Rinji Sugino , Jayendra Bhakta , Takashi Orimoto , Hiroyuki Nansei , Yukio Hayakawa , Takayuki Maruyama , Hidehiko Shiraiwa , Kuo-Tung Chang , Lei Xue , Meng Ding , Amol Ramesh Joshi , YouSeok Suh , Harpreet Sachar
IPC分类号： H01L29/792
CPC分类号： H01L29/792 , H01L21/28273 , H01L27/115 , H01L27/11568
摘要： A memory cell system is provided including a first insulator layer over a semiconductor substrate, a charge trap layer over the first insulator layer, and slot where the charge trap layer includes a second insulator layer having the characteristic of being grown.
摘要翻译：提供一种存储单元系统，包括半导体衬底上的第一绝缘体层，第一绝缘体层上的电荷陷阱层和电荷陷阱层包括具有生长特性的第二绝缘体层的槽。

10. 发明授权

US07675104B2 Integrated circuit memory system employing silicon rich layers 有权
标题翻译：集成电路存储系统采用富硅层
公开(公告)号：US07675104B2
公开(公告)日：2010-03-09
申请号：US11461131
申请日：2006-07-31
申请人： Amol Ramesh Joshi , Harpreet Sachar , YouSeok Suh , Shenqing Fang , Chih-Yuh Yang , Lovejeet Singh , David H. Matsumoto , Hidehiko Shiraiwa , Kuo-Tung Chang , Scott A. Bell , Allison Holbrook , Satoshi Torii
发明人： Amol Ramesh Joshi , Harpreet Sachar , YouSeok Suh , Shenqing Fang , Chih-Yuh Yang , Lovejeet Singh , David H. Matsumoto , Hidehiko Shiraiwa , Kuo-Tung Chang , Scott A. Bell , Allison Holbrook , Satoshi Torii
IPC分类号： H01L21/8247
CPC分类号： H01L27/11568 , H01L21/3081 , H01L21/76224 , H01L27/115 , H01L29/66833
摘要： An integrated circuit memory system that includes: providing a substrate; forming a silicon rich charge storage layer over the substrate; forming a first isolation trench through the silicon rich charge storage layer in a first direction; and forming a second isolation trench through the silicon rich charge storage layer in a second direction.
摘要翻译：一种集成电路存储器系统，包括：提供衬底; 在所述衬底上形成富硅电荷存储层; 通过富硅电荷存储层沿第一方向形成第一隔离沟槽; 以及在第二方向上通过富硅电荷存储层形成第二隔离沟槽。

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