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11. 发明授权

US07624369B2 Closed-loop design for manufacturability process 失效
标题翻译：可制造性过程的闭环设计
公开(公告)号：US07624369B2
公开(公告)日：2009-11-24
申请号：US11554904
申请日：2006-10-31
申请人： Ioana Graur , Geng Han , Scott M. Mansfiled , Lars W. Liebmann
发明人： Ioana Graur , Geng Han , Scott M. Mansfiled , Lars W. Liebmann
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A method of designing an integrated circuit is provided in which the design layout is optimized using a process model until the design constraints are satisfied by the image contours simulated by the process model. The process model used in the design phase need not be as accurate as the lithographic model used in preparing the lithographic mask layout during data prep. The resulting image contours are then included with the modified, optimized design layout to the data prep process, in which the mask layout is optimized using the lithographic process model, for example, including RET and OPC. The mask layout optimization matches the images simulated by the lithographic process model with the image contours generated during the design phase, which ensures that the design and manufacturability constraints specified by the designer are satisfied by the optimized mask layout.
摘要翻译：提供一种设计集成电路的方法，其中使用过程模型优化设计布局，直到由过程模型模拟的图像轮廓满足设计约束。在设计阶段使用的过程模型不需要与在数据准备期间制备光刻掩模布局时使用的光刻模型一样精确。然后将所得到的图像轮廓与经修改的优化的设计布局一起包括在数据准备过程中，其中使用光刻过程模型（例如包括RET和OPC）优化掩模布局。掩模布局优化将由光刻过程模型模拟的图像与在设计阶段生成的图像轮廓相匹配，从而确保设计人员指定的设计和可制造性约束被优化的掩模布局所满足。

12. 发明授权

US07475380B2 Generating mask patterns for alternating phase-shift mask lithography 失效
标题翻译：生成用于交替相移掩模光刻的掩模图案
公开(公告)号：US07475380B2
公开(公告)日：2009-01-06
申请号：US11318893
申请日：2005-12-27
申请人： Lars W. Liebmann , Scott J. Bukofsky , Ioana Graur
发明人： Lars W. Liebmann , Scott J. Bukofsky , Ioana Graur
IPC分类号： G06F17/50 , G03F9/00
CPC分类号： G03F1/30 , G03F1/70
摘要： A system, method and recording medium are provided for generating patterns of a paired set of a block mask and a phase shift mask from a data set defining a circuit layout to be provided on a substrate. A circuit layout is inputted and critical segments of the circuit layout are identified. Then, based on the identified critical segments, block mask patterns are generated and legalized for inclusion in a block mask. Thereafter, based on the identified critical segments and the block mask patterns, phase mask patterns are generated, legalized and colored to define a phase shift mask for use in a dual exposure method with the block mask for patterning the identified critical segments of the circuit layout.
摘要翻译：提供一种系统，方法和记录介质，用于从定义要提供在基板上的电路布局的数据集中产生一组块掩模和相移掩模的成对集合的模式。输入电路布局并识别电路布局的关键段。然后，基于所识别的关键段，块掩模图案被生成并合法化以包含在块掩码中。此后，基于所识别的临界段和块掩模图案，生成相位掩模图案，合法化和着色以限定用于双曝光方法的相移掩模，其中块掩模用于图案化所识别的电路布局的关键段。

13. 发明申请

US20080134130A1 LOCAL COLORING FOR HIERARCHICAL OPC 失效
标题翻译：用于分层OPC的本地着色
公开(公告)号：US20080134130A1
公开(公告)日：2008-06-05
申请号：US11564957
申请日：2006-11-30
申请人： Zachary Baum , Ioana Graur , Lars W. Liebmann , Scott M. Mansfield
发明人： Zachary Baum , Ioana Graur , Lars W. Liebmann , Scott M. Mansfield
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A method for designing a mask for fabricating an integrated circuit is provided wherein a mask layout that requires coloring, such as for alternating phase shift, double-exposure and double-exposure-etch masks, is organized into uncolored hierarchical design units. Prior to modification by OPC, each hierarchical design unit is locally colored. OPC is then performed on the locally colored hierarchical design unit. The local coloring information for the hierarchically arranged OPC-modified design unit may be discarded. After OPC modification, the uncolored OPC-modified design units may be placed within the mask layout, and the flattened data may be colored. Thus, turnaround time for mask design is significantly improved since the numerically intensive OPC is performed on the hierarchical data, avoiding the need to perform OPC on flattened data, whereas the less intensive global coloring is performed on flattened data.
摘要翻译：提供了一种用于设计用于制造集成电路的掩模的方法，其中需要诸如用于交替相移，双曝光和双曝光蚀刻掩模的着色的掩模布局被组织成无色层级设计单元。在OPC修改之前，每个分层设计单元都是局部有色的。然后在本地着色的分层设计单元上执行OPC。可以丢弃用于分层布置的OPC修改的设计单元的局部着色信息。在OPC修改之后，未着色的OPC修改的设计单元可以放置在掩模布局内，并且扁平化的数据可能被着色。因此，掩模设计的周转时间显着提高，因为对分层数据执行数字密集型OPC，避免了对平坦化数据执行OPC的需要，而对扁平化数据执行的密集型全局着色较少。

14. 发明授权

US06993741B2 Generating mask patterns for alternating phase-shift mask lithography 失效
标题翻译：生成用于交替相移掩模光刻的掩模图案
公开(公告)号：US06993741B2
公开(公告)日：2006-01-31
申请号：US10604373
申请日：2003-07-15
申请人： Lars W. Liebmann , Scott J. Bukofsky , Ioana Graur
发明人： Lars W. Liebmann , Scott J. Bukofsky , Ioana Graur
IPC分类号： G06F17/50 , G03C1/00 , G03F5/00
CPC分类号： G03F1/30 , G03F1/70
摘要： A method of generating patterns of a pair of photomasks from a data set defining a circuit layout to be provided on a substrate includes identifying critical segments of the circuit layout to be provided on the substrate. Block mask patterns are generated and then legalized based on the identified critical segments. Thereafter, phase mask patterns are generated, legalized and colored. The legalized block mask patterns and the legalized phase mask patterns that have been colored define features of a block mask and an alternating phase shift mask, respectively, for use in a dual exposure method for patterning features in a resist layer of a substrate.
摘要翻译：从定义要提供在衬底上的电路布局的数据集中产生一对光掩模的图案的方法包括识别要在衬底上提供的电路布局的关键段。生成块掩模模式，然后根据所识别的关键段进行合法化。此后，生成相位掩模图案，合法化和着色。已经着色的合法化块掩模图案和合法化的相位掩模图案分别定义了块掩模和交替相移掩模的特征，用于在用于图案化衬底的抗蚀剂层中的特征的双曝光方法中使用。

15. 发明申请

US20080127029A1 CLOSED-LOOP DESIGN FOR MANUFACTURABILITY PROCESS 失效
标题翻译：闭环设计用于制造工艺
公开(公告)号：US20080127029A1
公开(公告)日：2008-05-29
申请号：US11554904
申请日：2006-10-31
申请人： Ioana Graur , Geng Han , Scott M. Mansfield , Lars W. Liebmann
发明人： Ioana Graur , Geng Han , Scott M. Mansfield , Lars W. Liebmann
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A method of designing an integrated circuit is provided in which the design layout is optimized using a process model until the design constraints are satisfied by the image contours simulated by the process model. The process model used in the design phase need not be as accurate as the lithographic model used in preparing the lithographic mask layout during data prep. The resulting image contours are then included with the modified, optimized design layout to the data prep process, in which the mask layout is optimized using the lithographic process model, for example, including RET and OPC. The mask layout optimization matches the images simulated by the lithographic process model with the image contours generated during the design phase, which ensures that the design and manufacturability constraints specified by the designer are satisfied by the optimized mask layout.
摘要翻译：提供一种设计集成电路的方法，其中使用过程模型优化设计布局，直到由过程模型模拟的图像轮廓满足设计约束。在设计阶段使用的过程模型不需要与在数据准备期间制备光刻掩模布局时使用的光刻模型一样精确。然后将所得到的图像轮廓与经修改的优化的设计布局一起包括在数据准备过程中，其中使用光刻过程模型（例如包括RET和OPC）优化掩模布局。掩模布局优化将由光刻过程模型模拟的图像与在设计阶段生成的图像轮廓相匹配，从而确保设计人员指定的设计和可制造性约束被优化的掩模布局所满足。

16. 发明授权

US07266798B2 Designer's intent tolerance bands for proximity correction and checking 失效
标题翻译：设计师的意图容差带用于近距离校正和检查
公开(公告)号：US07266798B2
公开(公告)日：2007-09-04
申请号：US11163264
申请日：2005-10-12
申请人： Scott M. Mansfield , Lars W. Liebmann , Azalia Krasnoperova , Ioana Graur
发明人： Scott M. Mansfield , Lars W. Liebmann , Azalia Krasnoperova , Ioana Graur
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5081 , G03F1/36 , G06F2217/12 , Y02P90/265
摘要： A method of conveying the designer's intended electrical characteristics for a semiconductor design is provided by forming tolerance bands for a design layer of interest that take into consideration constraints from design layers that interact with and influence the features on the design layer of interest. The method determines regions, i.e. tolerance bands, within which the printed edges of features of the layer of interest will print within a predetermined criterion, and satisfy a variety of constraints, including, but not limited to, electrical, overlay and manufacturability constraints arising from the influence of features on other layers. The method may be implemented in a computer program product for execution on a computer system. The resulting tolerance bands can be used to efficiently convey the designer's intent to a lithographer, an OPC engineer or a mask manufacturer or tool.
摘要翻译：通过为感兴趣的设计层形成公差带来提供设计者用于半导体设计的预期电气特性的方法，其考虑到与感兴趣的设计层上的特征相互作用并影响其特征的设计层的约束。该方法确定区域，即公差带，其中感兴趣层的特征的打印边缘将在预定标准内打印，并且满足各种约束，包括但不限于电气，重叠和可制造性约束特征对其他层的影响。该方法可以在用于在计算机系统上执行的计算机程序产品中实现。所得到的公差带可用于有效传达设计人员对平版印刷机，OPC工程师或掩模制造商或工具的意图。

17. 发明授权

US07175942B2 Method of conflict avoidance in fabrication of gate-shrink alternating phase shifting masks 失效
标题翻译：在制造栅极 - 收缩交变相移掩模时避免冲突的方法
公开(公告)号：US07175942B2
公开(公告)日：2007-02-13
申请号：US10708055
申请日：2004-02-05
申请人： Lars W. Liebmann , Ioana Graur
发明人： Lars W. Liebmann , Ioana Graur
IPC分类号： G03F1/00 , G06F17/50
CPC分类号： G03F1/30
摘要： A method of designing a layout of an alternating phase shifting mask for projecting an image of an integrated circuit design having a plurality of features to be projected using alternating phase shifting segments, including a gate-shrink region of a transistor having a critical width along a length thereof that extends beyond a diffusion region. The method also provides alternating phase shift design rules based on alternating phase shift design parameters comprising minimum phase width, minimum phase-to-phase spacing, and minimum extension of critical width beyond another feature. The method then includes identifying portions of the integrated circuit layout having a critical width feature that violate the alternating phase shift design rules, and reducing the length that the critical width gate-shrink region feature extends beyond the other diffusion region feature to the minimum extension. An alternating phase shifting mask layout is then generated in conformance with the alternating phase shift design rules.
摘要翻译：一种设计交替相移掩模的布局的方法，用于使用交变相移段来投影具有要投影的多个特征的集成电路设计的图像，所述交变相移段包括沿着沿着具有临界宽度的晶体管的栅极收缩区域其长度延伸超过扩散区域。该方法还提供基于交替相移设计参数的交替相移设计规则，其包括最小相位宽度，最小相间间隔以及临界宽度超出另一特征的最小延伸。该方法然后包括识别具有违反交替相移设计规则的临界宽度特征的集成电路布局的部分，并且减小临界宽度栅 - 收缩区域特征延伸超出另一扩散区域特征到最小延伸的长度。然后根据交变相移设计规则生成交替的相移掩模布局。

18. 发明授权

US06964032B2 Pitch-based subresolution assist feature design 失效
标题翻译：基于间距的分解辅助功能设计
公开(公告)号：US06964032B2
公开(公告)日：2005-11-08
申请号：US10378579
申请日：2003-02-28
申请人： Lars W. Liebmann , Allen H. Gabor , Ronald L. Gordon , Carlos A. Fonseca , Martin Burkhardt
发明人： Lars W. Liebmann , Allen H. Gabor , Ronald L. Gordon , Carlos A. Fonseca , Martin Burkhardt
IPC分类号： G03F1/00 , G06F17/50 , H01L21/027
CPC分类号： G03F7/70441 , G03F1/36 , G03F7/70125 , G06F17/5068 , G06F2217/12
摘要： A method of designing a mask for imaging an integrated circuit (IC) design layout is provided to efficiently configure subresolution assist features (SRAFs) corresponding to an optimally configured annular illumination source of a lithographic projection system. A critical pitch is identified for the IC design, and optimal inner and outer radial coordinates of an annular illumination source are determined so that the resulting image projected through the mask will be optimized for the full range of pitches in the design layout. A relationship is provided for determining an optimal inner radius and outer radius for the annular illumination source. The number and placement of SRAFs are added to the mask design so that the resulting range of pitches substantially correspond to the critical pitch. The method of configuring SRAFs so that the image will have optimal characteristics, such as good contrast and good depth of focus, is fast.
摘要翻译：提供了一种设计用于对集成电路（IC）设计布局进行成像的掩模的方法，以有效地配置对应于光刻投影系统的最佳配置的环形照明源的分解辅助特征（SRAF）。确定IC设计的关键音调，并且确定环形照明光源的最佳内外径向坐标，以便通过掩模投射的所得图像将针对设计布局中的全部音高进行优化。提供了用于确定环形照明源的最佳内半径和外半径的关系。将SRAF的数量和位置添加到掩模设计中，使得所得到的间距范围基本上对应于临界间距。配置SRAF的方法是使图像具有最佳特征，如良好的对比度和良好的聚焦深度。

19. 发明授权

US06824932B2 Self-aligned alternating phase shift mask patterning process 有权
标题翻译：自对准交替相移掩模图案化工艺
公开(公告)号：US06824932B2
公开(公告)日：2004-11-30
申请号：US10164242
申请日：2002-06-05
申请人： Scott J. Bukofsky , Carlos A. Fonseca , Michael S. Hibbs , Lars W. Liebmann
发明人： Scott J. Bukofsky , Carlos A. Fonseca , Michael S. Hibbs , Lars W. Liebmann
IPC分类号： G03F900
CPC分类号： G03F1/30 , G03F7/0035 , G03F7/2022
摘要： A method and apparatus for making phase shift masks are provided wherein an anti-reflective coating used on an opaque pattern layer of the mask fully covers the opaque pattern layer and has not been etched in the etching process to form the phase shift mask. A two-exposure method to form the phase shift mask is used wherein a photoresist having a defined dose-to-clear level is coated on the surface of the mask and the lower surface of the mask is exposed to a blanket exposure in an energy amount less than the dose-to-clear level. The open areas of the upper surface of the mask to be etched are exposed to an energy dose in an amount less than the dose-to-clear level, with the sum of the amounts of the lower surface energy and upper surface energy being at least the dose-to-clear level. The method and apparatus minimizes and/or avoids etching of the anti-reflective coating.
摘要翻译：提供了一种用于制造相移掩模的方法和装置，其中在掩模的不透明图案层上使用的抗反射涂层完全覆盖不透明图案层，并且在蚀刻工艺中没有被蚀刻以形成相移掩模。使用形成相移掩模的双曝光方法，其中具有确定的剂量至清晰度的光致抗蚀剂被涂覆在掩模的表面上，并且掩模的下表面以能量的量曝光小于剂量到清除水平。要蚀刻的掩模的上表面的开放区域暴露于小于剂量至清除水平的量的能量剂量，其中下表面能和上表面能的量的总和至少为剂量到清晰度。该方法和装置使抗反射涂层的蚀刻最小化和/或避免。

20. 发明授权

US08473885B2 Physical design system and method 失效
公开(公告)号：US08473885B2
公开(公告)日：2013-06-25
申请号：US13413759
申请日：2012-03-07
申请人： John M. Cohn , James A. Culp , Ulrich A. Finkler , Fook-Luen Heng , Mark A. Lavin , Jin Fuw Lee , Lars W. Liebmann , Gregory A. Northrop , Nakgeuon Seong , Rama N. Singh , Leon Stok , Pieter J. Woeltgens
发明人： John M. Cohn , James A. Culp , Ulrich A. Finkler , Fook-Luen Heng , Mark A. Lavin , Jin Fuw Lee , Lars W. Liebmann , Gregory A. Northrop , Nakgeuon Seong , Rama N. Singh , Leon Stok , Pieter J. Woeltgens
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G06F17/5009 , G06F17/5072
摘要： A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit generates a target layout from the checked design. A data prep unit prepares the target layout for mask making. A pattern caching unit selectively replaces portions of the design with previously cached results for improved design efficiency.

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