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1. 发明授权

US07135255B2 Layout impact reduction with angled phase shapes 失效
标题翻译：具有角度相位形状的布局冲击减少
公开(公告)号：US07135255B2
公开(公告)日：2006-11-14
申请号：US10249317
申请日：2003-03-31
申请人： Scott J. Bukofsky , John K. DeBrosse , Marco Hug , Lars W. Liebmann , Daniel J. Nickel , Juergen Preuninger
发明人： Scott J. Bukofsky , John K. DeBrosse , Marco Hug , Lars W. Liebmann , Daniel J. Nickel , Juergen Preuninger
IPC分类号： G01F9/00
CPC分类号： G03F1/30
摘要： A phase shift mask shape that reduces line-end shortening at the critical feature without changing layout size increases required of requisite phase shift rules. The phase feature is given an angled extension, which includes the lithographic shortening value. This allows the critical shape to be designed much closer to the reference layer then it could without the angled extension feature. Phase mask extension features beyond a given device segment are significantly reduced by lengthening the feature along an uncritical portion; moving the feature reference point to the device layer; and flattening the phase extension feature into an L-shape or T-shape along the uncritical parts of a device segment. Applying these design rules allows a draw of the gate conductor under current conditions and puts phase shapes inside without extending the gate conductor dimensions to the next feature.
摘要翻译：减少关键特征而不改变布局尺寸的线端缩短的相移掩模形状增加了所需的相移规则。相位特征给出一个有角度的延伸，其包括光刻缩短值。这允许将临界形状设计得更接近参考层，然后它可以没有成角度的延伸特征。通过沿着非临界部分延长特征，显着减少了给定装置段之外的相位掩模延伸特征; 将特征参考点移动到设备层; 并且将相延伸特征沿着装置段的非关键部分平坦化为L形或T形。应用这些设计规则允许在当前条件下绘制栅极导体，并将相位形状置于内部，而不会将栅极导体尺寸延伸到下一个特征。

2. 发明授权

US07354779B2 Topography compensated film application methods 有权
标题翻译：地形补偿膜应用方法
公开(公告)号：US07354779B2
公开(公告)日：2008-04-08
申请号：US11276707
申请日：2006-03-10
申请人： Colin J. Brodsky , Scott J. Bukofsky , Allen H. Gabor
发明人： Colin J. Brodsky , Scott J. Bukofsky , Allen H. Gabor
IPC分类号： G01R31/26 , H01L21/66
CPC分类号： H01L21/0271 , H01L21/0276
摘要： Methods for applying topographically compensated film in a semiconductor wafer fabrication process are disclosed. The processes include premapping a surface of a wafer so as to determine the local topography (e.g., z-height) of the wafer and then applying a variable depth of a film to the wafer, such that the variable depth is modulated based on the local topography of the wafer. The resultant topography of the applied film and wafer is substantially planar (e.g., within approximately 100 nm) across the wafer.
摘要翻译：公开了在半导体晶片制造工艺中应用地形学补偿膜的方法。这些过程包括预先处理晶片的表面，以便确定晶片的局部形貌（例如，z-高度），然后将薄膜的可变深度施加到晶片，使得可变深度基于本地晶圆的形貌。所施加的膜和晶片的所得形貌在晶片上基本上是平面的（例如在大约100nm内）。

3. 发明授权

US06451508B1 Plural interleaved exposure process for increased feature aspect ratio in dense arrays 失效
标题翻译：多个交错曝光过程，用于增加密集阵列中的特征长宽比
公开(公告)号：US06451508B1
公开(公告)日：2002-09-17
申请号：US09561472
申请日：2000-04-28
申请人： Scott J. Bukofsky , Gerhard Kunkel , Alan C. Thomas
发明人： Scott J. Bukofsky , Gerhard Kunkel , Alan C. Thomas
IPC分类号： G03F720
CPC分类号： G03F7/70466 , G03F1/70
摘要： A method for exposing a workpiece in a dual exposure step-and-repeat process starts by forming a design for a reticle mask. Deconstruct the design for the reticle mask by removing a set(s) of the features that are juxtaposed. Form unexposed resist on the workpiece. Load the workpiece and the reticle mask into the stepper. Expose the workpiece through the reticle mask. Reposition the workpiece by a nanostep. Then expose the workpiece through the reticle mask after the repositioning. Test whether the plural exposure process is finished. If the result of the test is NO the process loops back to repeat some of the above steps. Otherwise the process has been completed. An overlay mark is produced by plural exposures of a single mark. A dead zone is provided surrounding an array region in which printing occurs subsequent to exposure in an original exposure. Stepper-framing-blades are moved over the dead zone to prevent additional exposures after an initial exposure. Alternatively, the workpiece can be fully exposed first by stepping a series of full steps, then going back to the starting position, making a nanostep to reset the starting position and re-exposing from the reset starting position in the same way with full steps from the nanostepped position.
摘要翻译：用于在双重曝光步骤和重复过程中曝光工件的方法通过形成掩模版掩模的设计而开始。通过删除并置的一些特征来解构掩模版掩模的设计。在工件上形成未曝光的抗蚀剂。将工件和掩模版掩模装入步进器。通过掩模掩模将工件暴露。用纳秒级重新定位工件。然后在重新定位后将工件暴露在掩模版掩模之外。测试多次曝光过程是否完成。如果测试结果为“否”，则过程循环返回以重复上述步骤。否则该过程已经完成。通过单个标记的多次曝光产生重叠标记。围绕阵列区域提供死区，其中在原始曝光中曝光之后发生印刷。步进框架刀片在死区移动，以防止在初始曝光后的额外曝光。或者，可以通过步进一系列完整的步骤，然后返回到起始位置，首先完全暴露工件，从而使得纳秒能够以相同的方式从复位起始位置复位起始位置并再次曝光纳米级位置。

4. 发明授权

US07475380B2 Generating mask patterns for alternating phase-shift mask lithography 失效
标题翻译：生成用于交替相移掩模光刻的掩模图案
公开(公告)号：US07475380B2
公开(公告)日：2009-01-06
申请号：US11318893
申请日：2005-12-27
申请人： Lars W. Liebmann , Scott J. Bukofsky , Ioana Graur
发明人： Lars W. Liebmann , Scott J. Bukofsky , Ioana Graur
IPC分类号： G06F17/50 , G03F9/00
CPC分类号： G03F1/30 , G03F1/70
摘要： A system, method and recording medium are provided for generating patterns of a paired set of a block mask and a phase shift mask from a data set defining a circuit layout to be provided on a substrate. A circuit layout is inputted and critical segments of the circuit layout are identified. Then, based on the identified critical segments, block mask patterns are generated and legalized for inclusion in a block mask. Thereafter, based on the identified critical segments and the block mask patterns, phase mask patterns are generated, legalized and colored to define a phase shift mask for use in a dual exposure method with the block mask for patterning the identified critical segments of the circuit layout.
摘要翻译：提供一种系统，方法和记录介质，用于从定义要提供在基板上的电路布局的数据集中产生一组块掩模和相移掩模的成对集合的模式。输入电路布局并识别电路布局的关键段。然后，基于所识别的关键段，块掩模图案被生成并合法化以包含在块掩码中。此后，基于所识别的临界段和块掩模图案，生成相位掩模图案，合法化和着色以限定用于双曝光方法的相移掩模，其中块掩模用于图案化所识别的电路布局的关键段。

5. 发明授权

US07229936B2 Method to reduce photoresist pattern collapse by controlled surface microroughening 有权
标题翻译：通过控制表面微透镜减少光致抗蚀剂图案崩溃的方法
公开(公告)号：US07229936B2
公开(公告)日：2007-06-12
申请号：US10709406
申请日：2004-05-03
申请人： Colin J. Brodsky , Scott J. Bukofsky , Dario L. Goldfarb , Scott D. Halle
发明人： Colin J. Brodsky , Scott J. Bukofsky , Dario L. Goldfarb , Scott D. Halle
IPC分类号： H01L21/31
CPC分类号： G03F7/091 , H01L21/0276 , H01L21/31127 , H01L21/31133 , H01L21/31138 , H01L21/312
摘要： A method is provided for preparing a substrate for photolithographic patterning. The method includes providing a substrate having at least an exposed rough surface layer including a polymeric material. The rough surface layer has surface features characterized by feature step height varying between about two percent and twenty percent of the minimum photolithographic half-pitch. A layer of photoresist material is then provided over the exposed rough surface layer and patterned.
摘要翻译：提供了一种制备用于光刻图案的衬底的方法。该方法包括提供具有至少暴露的包含聚合材料的粗糙表面层的基底。粗糙表面层具有表征特征，其特征在于最小光刻半间距的约百分之二到百分之二的特征步长。然后在暴露的粗糙表面层上提供一层光致抗蚀剂材料并图案化。

6. 发明授权

US06824932B2 Self-aligned alternating phase shift mask patterning process 有权
标题翻译：自对准交替相移掩模图案化工艺
公开(公告)号：US06824932B2
公开(公告)日：2004-11-30
申请号：US10164242
申请日：2002-06-05
申请人： Scott J. Bukofsky , Carlos A. Fonseca , Michael S. Hibbs , Lars W. Liebmann
发明人： Scott J. Bukofsky , Carlos A. Fonseca , Michael S. Hibbs , Lars W. Liebmann
IPC分类号： G03F900
CPC分类号： G03F1/30 , G03F7/0035 , G03F7/2022
摘要： A method and apparatus for making phase shift masks are provided wherein an anti-reflective coating used on an opaque pattern layer of the mask fully covers the opaque pattern layer and has not been etched in the etching process to form the phase shift mask. A two-exposure method to form the phase shift mask is used wherein a photoresist having a defined dose-to-clear level is coated on the surface of the mask and the lower surface of the mask is exposed to a blanket exposure in an energy amount less than the dose-to-clear level. The open areas of the upper surface of the mask to be etched are exposed to an energy dose in an amount less than the dose-to-clear level, with the sum of the amounts of the lower surface energy and upper surface energy being at least the dose-to-clear level. The method and apparatus minimizes and/or avoids etching of the anti-reflective coating.
摘要翻译：提供了一种用于制造相移掩模的方法和装置，其中在掩模的不透明图案层上使用的抗反射涂层完全覆盖不透明图案层，并且在蚀刻工艺中没有被蚀刻以形成相移掩模。使用形成相移掩模的双曝光方法，其中具有确定的剂量至清晰度的光致抗蚀剂被涂覆在掩模的表面上，并且掩模的下表面以能量的量曝光小于剂量到清除水平。要蚀刻的掩模的上表面的开放区域暴露于小于剂量至清除水平的量的能量剂量，其中下表面能和上表面能的量的总和至少为剂量到清晰度。该方法和装置使抗反射涂层的蚀刻最小化和/或避免。

7. 发明授权

US06451490B1 Method to overcome image shortening by use of sub-resolution reticle features 失效
标题翻译：通过使用分辨率分辨率特征克服图像缩短的方法
公开(公告)号：US06451490B1
公开(公告)日：2002-09-17
申请号：US09709091
申请日：2000-11-08
申请人： William H. Advocate , Scott J. Bukofsky , Christopher Adam Feild , Donald J. Samuels
发明人： William H. Advocate , Scott J. Bukofsky , Christopher Adam Feild , Donald J. Samuels
IPC分类号： G03F900
CPC分类号： G03F1/36 , G03F1/30 , G03F1/32 , G03F7/70433
摘要： Image shortening in a photolithographic process is substantially reduced by using sub-resolution reticle features to alter the aerial image in the shortened regions. The use of such sub-resolution reticle features is simple to implement in a design system, and allows for increased feature aspect ratio as well as overlap to other critical features.
摘要翻译：通过使用子分辨率掩模特征来改变缩短区域中的空间图像，光刻工艺中的图像缩短显着降低。在设计系统中使用这样的分辨率分辨率特征是简单的，并且允许增加的特征宽高比以及与其它关键特征重叠。

8. 发明授权

US06327023B1 Optimization of reticle rotation for critical dimension and overlay improvement 失效
标题翻译：关键尺寸和覆盖改进的掩模旋转优化
公开(公告)号：US06327023B1
公开(公告)日：2001-12-04
申请号：US09471427
申请日：1999-12-23
申请人： Scott J. Bukofsky , Christopher J. Progler
发明人： Scott J. Bukofsky , Christopher J. Progler
IPC分类号： G03B2742
CPC分类号： G03F7/705 , G03F7/70358 , G03F7/70425 , G03F7/70433 , G03F7/706
摘要： A scanning method capable of reducing across chip linewidth variation and image placement error is disclosed, the method including a step whereby a reticle having a plurality of lines is scanned in a direction perpendicular to the lines. The scanning method includes a radiation source provided with an aperture with a slot. In this case, it is preferable that the radiation source keeps the rectangular slot in the direction that minimizes pattern distortions.
摘要翻译：公开了一种能够减少跨越芯片线宽变化和图像放置误差的扫描方法，该方法包括一个步骤，由此在垂直于线的方向上扫描具有多条线的掩模版。扫描方法包括设置有具有狭槽的孔的辐射源。在这种情况下，优选的是，辐射源将矩形槽保持在使图案失真最小化的方向上。

9. 发明授权

US07239371B2 Density-aware dynamic leveling in scanning exposure systems 失效
标题翻译：扫描曝光系统中的密度感知动态调平
公开(公告)号：US07239371B2
公开(公告)日：2007-07-03
申请号：US11163409
申请日：2005-10-18
申请人： Bernhard R. Liegl , Colin J. Brodsky , Scott J. Bukofsky , Steven J. Holmes
发明人： Bernhard R. Liegl , Colin J. Brodsky , Scott J. Bukofsky , Steven J. Holmes
IPC分类号： G03B27/52 , G03B27/42 , G03B27/32
CPC分类号： G03F9/7034 , G03F9/7026
摘要： A method and apparatus are provided for improving the leveling and, consequently, the focusing of a substrate such as a wafer during the photolithography imaging procedure of a semiconductor manufacturing process. The invention performs a pre-scan of the wafer's topography and assigns importance values to different regions of the wafer surface. Exposure focus instructions are calculated based on the topography and importance values of the different regions and the wafer is then scanned and imaged based on the calculated exposure focus instructions.
摘要翻译：提供了一种方法和装置，用于在半导体制造工艺的光刻成像过程期间改进调平，并因此改善诸如晶片的基板的聚焦。本发明对晶片的形貌进行预扫描，并将重要性值分配给晶片表面的不同区域。基于不同区域的形貌和重要度值计算曝光焦点指令，然后基于计算出的曝光聚焦指令对晶片进行扫描和成像。

10. 发明授权

US06993741B2 Generating mask patterns for alternating phase-shift mask lithography 失效
标题翻译：生成用于交替相移掩模光刻的掩模图案
公开(公告)号：US06993741B2
公开(公告)日：2006-01-31
申请号：US10604373
申请日：2003-07-15
申请人： Lars W. Liebmann , Scott J. Bukofsky , Ioana Graur
发明人： Lars W. Liebmann , Scott J. Bukofsky , Ioana Graur
IPC分类号： G06F17/50 , G03C1/00 , G03F5/00
CPC分类号： G03F1/30 , G03F1/70
摘要： A method of generating patterns of a pair of photomasks from a data set defining a circuit layout to be provided on a substrate includes identifying critical segments of the circuit layout to be provided on the substrate. Block mask patterns are generated and then legalized based on the identified critical segments. Thereafter, phase mask patterns are generated, legalized and colored. The legalized block mask patterns and the legalized phase mask patterns that have been colored define features of a block mask and an alternating phase shift mask, respectively, for use in a dual exposure method for patterning features in a resist layer of a substrate.
摘要翻译：从定义要提供在衬底上的电路布局的数据集中产生一对光掩模的图案的方法包括识别要在衬底上提供的电路布局的关键段。生成块掩模模式，然后根据所识别的关键段进行合法化。此后，生成相位掩模图案，合法化和着色。已经着色的合法化块掩模图案和合法化的相位掩模图案分别定义了块掩模和交替相移掩模的特征，用于在用于图案化衬底的抗蚀剂层中的特征的双曝光方法中使用。

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