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1. 发明授权

US07624369B2 Closed-loop design for manufacturability process 失效
标题翻译：可制造性过程的闭环设计
公开(公告)号：US07624369B2
公开(公告)日：2009-11-24
申请号：US11554904
申请日：2006-10-31
申请人： Ioana Graur , Geng Han , Scott M. Mansfiled , Lars W. Liebmann
发明人： Ioana Graur , Geng Han , Scott M. Mansfiled , Lars W. Liebmann
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A method of designing an integrated circuit is provided in which the design layout is optimized using a process model until the design constraints are satisfied by the image contours simulated by the process model. The process model used in the design phase need not be as accurate as the lithographic model used in preparing the lithographic mask layout during data prep. The resulting image contours are then included with the modified, optimized design layout to the data prep process, in which the mask layout is optimized using the lithographic process model, for example, including RET and OPC. The mask layout optimization matches the images simulated by the lithographic process model with the image contours generated during the design phase, which ensures that the design and manufacturability constraints specified by the designer are satisfied by the optimized mask layout.
摘要翻译：提供一种设计集成电路的方法，其中使用过程模型优化设计布局，直到由过程模型模拟的图像轮廓满足设计约束。在设计阶段使用的过程模型不需要与在数据准备期间制备光刻掩模布局时使用的光刻模型一样精确。然后将所得到的图像轮廓与经修改的优化的设计布局一起包括在数据准备过程中，其中使用光刻过程模型（例如包括RET和OPC）优化掩模布局。掩模布局优化将由光刻过程模型模拟的图像与在设计阶段生成的图像轮廓相匹配，从而确保设计人员指定的设计和可制造性约束被优化的掩模布局所满足。

2. 发明申请

US20080127029A1 CLOSED-LOOP DESIGN FOR MANUFACTURABILITY PROCESS 失效
标题翻译：闭环设计用于制造工艺
公开(公告)号：US20080127029A1
公开(公告)日：2008-05-29
申请号：US11554904
申请日：2006-10-31
申请人： Ioana Graur , Geng Han , Scott M. Mansfield , Lars W. Liebmann
发明人： Ioana Graur , Geng Han , Scott M. Mansfield , Lars W. Liebmann
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A method of designing an integrated circuit is provided in which the design layout is optimized using a process model until the design constraints are satisfied by the image contours simulated by the process model. The process model used in the design phase need not be as accurate as the lithographic model used in preparing the lithographic mask layout during data prep. The resulting image contours are then included with the modified, optimized design layout to the data prep process, in which the mask layout is optimized using the lithographic process model, for example, including RET and OPC. The mask layout optimization matches the images simulated by the lithographic process model with the image contours generated during the design phase, which ensures that the design and manufacturability constraints specified by the designer are satisfied by the optimized mask layout.
摘要翻译：提供一种设计集成电路的方法，其中使用过程模型优化设计布局，直到由过程模型模拟的图像轮廓满足设计约束。在设计阶段使用的过程模型不需要与在数据准备期间制备光刻掩模布局时使用的光刻模型一样精确。然后将所得到的图像轮廓与经修改的优化的设计布局一起包括在数据准备过程中，其中使用光刻过程模型（例如包括RET和OPC）优化掩模布局。掩模布局优化将由光刻过程模型模拟的图像与在设计阶段生成的图像轮廓相匹配，从而确保设计人员指定的设计和可制造性约束被优化的掩模布局所满足。

3. 发明授权

US07607114B2 Designer's intent tolerance bands for proximity correction and checking 失效
标题翻译：设计师的意图容差带用于近距离校正和检查
公开(公告)号：US07607114B2
公开(公告)日：2009-10-20
申请号：US11778302
申请日：2007-07-16
申请人： Scott M. Mansfield , Lars W. Liebmann , Azalia Krasnoperova , Ioana Graur
发明人： Scott M. Mansfield , Lars W. Liebmann , Azalia Krasnoperova , Ioana Graur
IPC分类号： G06F17/50 , G06F9/45 , G06F9/455
CPC分类号： G06F17/5081 , G03F1/36 , G06F2217/12 , Y02P90/265
摘要： A method of conveying the designer's intended electrical characteristics for a semiconductor design is provided by forming tolerance bands for a design layer of interest that take into consideration constraints from design layers that interact with and influence the features on the design layer of interest. The method determines regions, i.e. tolerance bands, within which the printed edges of features of the layer of interest will print within a predetermined criterion, and satisfy a variety of constraints, including, but not limited to, electrical, overlay and manufacturability constraints arising from the influence of features on other layers. The method may be implemented in a computer program product for execution on a computer system. The resulting tolerance bands can be used to efficiently convey the designer's intent to a lithographer, an OPC engineer or a mask manufacturer or tool.
摘要翻译：通过为感兴趣的设计层形成公差带来提供设计者用于半导体设计的预期电气特性的方法，其考虑到与感兴趣的设计层上的特征相互作用并影响其特征的设计层的约束。该方法确定区域，即公差带，其中感兴趣层的特征的打印边缘将在预定标准内打印，并且满足各种约束，包括但不限于电气，重叠和可制造性约束特征对其他层的影响。该方法可以在用于在计算机系统上执行的计算机程序产品中实现。所得到的公差带可用于有效传达设计人员对平版印刷机，OPC工程师或掩模制造商或工具的意图。

4. 发明授权

US07650587B2 Local coloring for hierarchical OPC 失效
标题翻译：分层OPC的局部着色
公开(公告)号：US07650587B2
公开(公告)日：2010-01-19
申请号：US11564957
申请日：2006-11-30
申请人： Zachary Baum , Ioana Graur , Lars W. Liebmann , Scott M. Mansfield
发明人： Zachary Baum , Ioana Graur , Lars W. Liebmann , Scott M. Mansfield
IPC分类号： G06F17/50
CPC分类号： G03F1/36
摘要： A method for designing a mask for fabricating an integrated circuit is provided wherein a mask layout that requires coloring, such as for alternating phase shift, double-exposure and double-exposure-etch masks, is organized into uncolored hierarchical design units. Prior to modification by OPC, each hierarchical design unit is locally colored. OPC is then performed on the locally colored hierarchical design unit. The local coloring information for the hierarchically arranged OPC-modified design unit may be discarded. After OPC modification, the uncolored OPC-modified design units may be placed within the mask layout, and the flattened data may be colored. Thus, turnaround time for mask design is significantly improved since the numerically intensive OPC is performed on the hierarchical data, avoiding the need to perform OPC on flattened data, whereas the less intensive global coloring is performed on flattened data.
摘要翻译：提供了一种用于设计用于制造集成电路的掩模的方法，其中需要诸如用于交替相移，双曝光和双曝光蚀刻掩模的着色的掩模布局被组织成无色层级设计单元。在OPC修改之前，每个分层设计单元都是局部有色的。然后在本地着色的分层设计单元上执行OPC。可以丢弃用于分层布置的OPC修改的设计单元的局部着色信息。在OPC修改之后，未着色的OPC修改的设计单元可以放置在掩模布局内，并且扁平化的数据可能被着色。因此，掩模设计的周转时间显着提高，因为对分层数据执行数字密集的OPC，避免了对平坦化数据执行OPC的需要，而对扁平化数据执行的密集型全局着色较少。

5. 发明授权

US06795961B2 Priority coloring for VLSI designs 失效
标题翻译： VLSI设计的优先着色
公开(公告)号：US06795961B2
公开(公告)日：2004-09-21
申请号：US10430148
申请日：2003-05-06
申请人： Lars W. Liebmann , Carlos A. Fonseca , Ioana Graur , Young O. Kim
发明人： Lars W. Liebmann , Carlos A. Fonseca , Ioana Graur , Young O. Kim
IPC分类号： G06F1750
CPC分类号： G03F1/30
摘要： A method and computer program product is described for optimizing the design of a circuit layout that assigns binary properties to the design elements according to a hierarchy of rules. For example, the design of an alternating phase shifted mask (altPSM) is optimized first according to rules that assign phase shapes that maximize image quality for critical circuit elements, and then further optimized to minimize mask manufacturability problems without significantly increasing the complexity of the design process flow. Further optimization of the design according to additional rules can be performed in a sequentially decreasing priority order. As the priority of rules decrease, some violation of lower priority rules may be acceptable, as long as higher priority rules are not violated.
摘要翻译：描述了一种方法和计算机程序产品，用于优化根据规则层级将二进制属性分配给设计元素的电路布局的设计。例如，交替相移掩模（altPSM）的设计首先根据规定分配相位形状的规则进行优化，该相位形状使关键电路元件的图像质量最大化，然后进一步优化以最小化掩模可制造性问题，而不会显着增加设计的复杂性工艺流程。根据附加规则进一步优化设计可以按顺序降低的优先顺序执行。由于规则的优先级减少，只要优先级较高的规则不被侵犯，某些违反较低优先权规则就可以接受。

6. 发明授权

US07687207B2 System for coloring a partially colored design in an alternating phase shift mask 失效
标题翻译：用于在交替相移掩模中着色部分着色设计的系统
公开(公告)号：US07687207B2
公开(公告)日：2010-03-30
申请号：US12121371
申请日：2008-05-15
申请人： Ioana Graur , Young O. Kim , Mark A. Lavin , Lars W. Liebmann
发明人： Ioana Graur , Young O. Kim , Mark A. Lavin , Lars W. Liebmann
IPC分类号： G03F1/00
CPC分类号： G03F1/30
摘要： A method of designing an alternating phase shifting mask for projecting an image of an integrated circuit design. Phase units are binary colorable within each unit of the hierarchical circuit design, e.g., cell, an array, a net, or array of nets and/or cells, the phase shapes. The assignment of phases or colors within a hierarchical unit will be correctly binary colored to satisfy the lithographic, manufacturability and other design rules, referred to collectively as coloring rules. During assembly with other units, the coloring of phases in a hierarchical unit may change (e.g., be reversed or flipped), but the correct binary colorability of a hierarchical unit is preserved, which simplifies assembly of the integrated circuit layout.
摘要翻译：一种设计用于投影集成电路设计的图像的交替相移掩模的方法。相位单元在分层电路设计的每个单元内，例如单元，阵列，网络或网络和/或单元阵列，可以是相位形状的二进制可着色。分层单元内的相位或颜色的分配将被正确地二进制着色以满足平版印刷，可制造性和其他设计规则，统称为着色规则。在与其他单元的组装期间，层级单元中的相位的着色可能改变（例如，被颠倒或翻转），但是保留了分层单元的正确的二值可着色性，这简化了集成电路布局的组装。

7. 发明授权

US07475380B2 Generating mask patterns for alternating phase-shift mask lithography 失效
标题翻译：生成用于交替相移掩模光刻的掩模图案
公开(公告)号：US07475380B2
公开(公告)日：2009-01-06
申请号：US11318893
申请日：2005-12-27
申请人： Lars W. Liebmann , Scott J. Bukofsky , Ioana Graur
发明人： Lars W. Liebmann , Scott J. Bukofsky , Ioana Graur
IPC分类号： G06F17/50 , G03F9/00
CPC分类号： G03F1/30 , G03F1/70
摘要： A system, method and recording medium are provided for generating patterns of a paired set of a block mask and a phase shift mask from a data set defining a circuit layout to be provided on a substrate. A circuit layout is inputted and critical segments of the circuit layout are identified. Then, based on the identified critical segments, block mask patterns are generated and legalized for inclusion in a block mask. Thereafter, based on the identified critical segments and the block mask patterns, phase mask patterns are generated, legalized and colored to define a phase shift mask for use in a dual exposure method with the block mask for patterning the identified critical segments of the circuit layout.
摘要翻译：提供一种系统，方法和记录介质，用于从定义要提供在基板上的电路布局的数据集中产生一组块掩模和相移掩模的成对集合的模式。输入电路布局并识别电路布局的关键段。然后，基于所识别的关键段，块掩模图案被生成并合法化以包含在块掩码中。此后，基于所识别的临界段和块掩模图案，生成相位掩模图案，合法化和着色以限定用于双曝光方法的相移掩模，其中块掩模用于图案化所识别的电路布局的关键段。

8. 发明授权

US07378195B2 System for coloring a partially colored design in an alternating phase shift mask 有权
标题翻译：用于在交替相移掩模中着色部分着色设计的系统
公开(公告)号：US07378195B2
公开(公告)日：2008-05-27
申请号：US10710224
申请日：2004-06-28
申请人： Ioana Graur , Young O. Kim , Mark A. Lavin , Lars W. Liebmann
发明人： Ioana Graur , Young O. Kim , Mark A. Lavin , Lars W. Liebmann
IPC分类号： G03F1/00
CPC分类号： G03F1/30
摘要： A method of designing an alternating phase shifting mask for projecting an image of an integrated circuit design. Phase units are binary colorable within each unit of the hierarchical circuit design, e.g., cell, an array, a net, or array of nets and/or cells, the phase shapes. The assignment of phases or colors within a hierarchical unit will be correctly binary colored to satisfy the lithographic, manufacturability and other design rules, referred to collectively as coloring rules. During assembly with other units, the coloring of phases in a hierarchical unit may change (e.g., be reversed or flipped), but the correct binary colorability of a hierarchical unit is preserved, which simplifies assembly of the integrated circuit layout.
摘要翻译：一种设计用于投影集成电路设计的图像的交替相移掩模的方法。相位单元在分层电路设计的每个单元内，例如单元，阵列，网络或网络和/或单元阵列，可以是相位形状的二进制可着色。分层单元内的相位或颜色的分配将被正确地二进制着色以满足平版印刷，可制造性和其他设计规则，统称为着色规则。在与其他单元的组装期间，层级单元中的相位的着色可能改变（例如，被颠倒或翻转），但是保留了分层单元的正确的二值可着色性，这简化了集成电路布局的组装。

9. 发明授权

US06927005B2 Alternating phase shift mask design with optimized phase shapes 有权
标题翻译：交替相移掩模设计，具有优化的相位形状
公开(公告)号：US06927005B2
公开(公告)日：2005-08-09
申请号：US10801880
申请日：2004-03-16
申请人： Lars W. Liebmann , Carlos A. Fonseca , Ioana Graur , Mark A. Lavin
发明人： Lars W. Liebmann , Carlos A. Fonseca , Ioana Graur , Mark A. Lavin
IPC分类号： G01F9/00 , G03C5/00 , G03F1/30 , G03F9/00 , G06F17/50
CPC分类号： G03F1/30
摘要： A method is described for designing an alternating phase shifted mask (altPSM) by optimally selecting the width of phase shapes. The selection of optimal phase shape widths is achieved by providing a lithography metric that describes the relationship between phase shape width and the target image dimension such that the metric, such as process window or across chip linewidth variation (ACLV), is optimized. In a preferred embodiment, ACLV is computed by Monte Carlo simulation by providing a set of error distributions for lithographic parameters such as focus, dose, lens aberrations, and the like. Alternatively, a lookup table of optimal phase widths associated with target image dimensions may be provided. The resulting altPSM is characterized by phase shapes having widths that vary according to the widths of the target image dimensions.
摘要翻译：描述了通过最佳地选择相位宽度的宽度来设计交替相移掩模（altPSM）的方法。通过提供描绘相位形状宽度和目标图像尺寸之间的关系的光刻度量来实现最佳相位形状宽度的选择，使得诸如处理窗口或跨芯片线宽变化（ACLV）的度量被优化。在优选实施例中，通过提供一组用于光刻参数（例如焦点，剂量，透镜像差等）的误差分布，通过蒙特卡罗模拟计算ACLV。或者，可以提供与目标图像尺寸相关联的最佳相位宽度的查找表。所得到的altPSM的特征在于具有根据目标图像尺寸的宽度而变化的宽度的相位形状。

10. 发明授权

US06757886B2 Alternating phase shift mask design with optimized phase shapes 有权
标题翻译：交替相移掩模设计，具有优化的相位形状
公开(公告)号：US06757886B2
公开(公告)日：2004-06-29
申请号：US10014707
申请日：2001-11-13
申请人： Lars W. Liebmann , Carlos A. Fonseca , Ioana Graur , Mark A. Lavin
发明人： Lars W. Liebmann , Carlos A. Fonseca , Ioana Graur , Mark A. Lavin
IPC分类号： G06F1750
CPC分类号： G03F1/30
摘要： A method is described for designing an alternating phase shifted mask (altPSM) by optimally selecting the width of phase shapes. The selection of optimal phase shape widths is achieved by providing a lithography metric that describes the relationship between phase shape width and the target image dimension such that the metric, such as process window or across chip linewidth variation (ACLV), is optimized. In a preferred embodiment, ACLV is computed by Monte Carlo simulation by providing a set of error distributions for lithographic parameters such as focus, dose, lens aberrations, and the like. Alternatively, a lookup table of optimal phase widths associated with target image dimensions may be provided. The resulting altPSM is characterized by phase shapes having widths that vary according to the widths of the target image dimensions.
摘要翻译：描述了通过最佳地选择相位宽度的宽度来设计交替相移掩模（altPSM）的方法。通过提供描绘相位形状宽度和目标图像尺寸之间的关系的光刻度量来实现最佳相位形状宽度的选择，使得诸如处理窗口或跨芯片线宽变化（ACLV）的度量被优化。在优选实施例中，通过提供一组用于光刻参数（例如焦点，剂量，透镜像差等）的误差分布，通过蒙特卡罗模拟计算ACLV。或者，可以提供与目标图像尺寸相关联的最佳相位宽度的查找表。所得到的altPSM的特征在于具有根据目标图像尺寸的宽度而变化的宽度的相位形状。

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