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11. 发明授权

US06211098B1 Wet oxidation method for forming silicon oxide dielectric layer 有权
标题翻译：用于形成氧化硅介电层的湿式氧化法
公开(公告)号：US06211098B1
公开(公告)日：2001-04-03
申请号：US09252337
申请日：1999-02-18
申请人： Jih-Churng Twu , Syun-Ming Jang , Chen-Hua Yu
发明人： Jih-Churng Twu , Syun-Ming Jang , Chen-Hua Yu
IPC分类号： H01L2126
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L29/517 , H01L29/518
摘要： A method for forming a silicon oxide gate oxide dielectric layer upon a silicon semiconductor substrate employed within a microelectronics fabrication. There is provided a silicon semiconductor substrate. There is then formed upon the silicon semiconductor substrate, empolying thermal annealing of the silicon semiconductor substrate at an elevated temperature in a gas mixture of oxygen, hydrogen and a diluent gas, a silicon oxide gate oxide dielectric layer with enhanced dielectric properties and more precise control of the silicon oxide dielectric layer thickness.
摘要翻译：一种在微电子学制造中使用的硅半导体衬底上形成氧化硅栅极氧化物电介质层的方法。提供硅半导体衬底。然后形成在硅半导体衬底上，在氧气，氢气和稀释气体的气体混合物中，在升高的温度下对硅半导体衬底进行热退火，具有增强介电特性和更精确控制的氧化硅栅氧化物介电层的氧化硅介电层厚度。

12. 发明授权

US06589356B1 Method for cleaning a silicon-based substrate without NH4OH vapor damage 有权
标题翻译：无NH4OH蒸汽损坏的硅基衬底的清洗方法
公开(公告)号：US06589356B1
公开(公告)日：2003-07-08
申请号：US09676746
申请日：2000-09-29
申请人： Juin-Jie Chang , Jih-Churng Twu , Rong-Hui Kao
发明人： Juin-Jie Chang , Jih-Churng Twu , Rong-Hui Kao
IPC分类号： C23G102
CPC分类号： H01L21/02046 , H01L21/02052
摘要： A method for cleaning a silicon-based substrate in an ammonia-containing solution without incurring any damages to the silicon surface by NH4OH vapor is described. The method can be conducted by first providing a silicon-based substrate that has a silicon surface, then forming a silicon oxide layer of very small thickness, i.e. less than 10 Å, on the silicon surface. The silicon-based substrate can then be cleaned in an ammonia-containing solution without incurring any surface damage to the silicon, i.e. such as the formation of silicon holes. The present invention novel method can be carried out by either adding an additional oxidation tank before the SC-1 cleaning tank, or adding an oxidant to a quick dump rinse tank prior to the SC-1 cleaning process.
摘要翻译：描述了一种在含氨溶液中清洗硅基底物而不会由NH 4 OH蒸气对硅表面造成任何损害的方法。该方法可以通过首先提供具有硅表面的硅基衬底，然后在硅表面上形成非常小的厚度（即，小于）的氧化硅层来进行。然后可以在含氨溶液中清洗硅基基材，而不会对硅造成任何表面损伤，例如形成硅孔。本发明的新方法可以通过在SC-1清洗槽之前添加另外的氧化槽，或在SC-1清洗过程之前向快速倾倒冲洗槽中加入氧化剂来进行。

13. 发明授权

US06500753B2 Method to reduce the damages of copper lines 有权
标题翻译：减少铜线损坏的方法
公开(公告)号：US06500753B2
公开(公告)日：2002-12-31
申请号：US09838209
申请日：2001-04-20
申请人： Syun-Ming Jang , Ying-Ho Chen , Jih-Churng Twu , Chen-Hua Yu
发明人： Syun-Ming Jang , Ying-Ho Chen , Jih-Churng Twu , Chen-Hua Yu
IPC分类号： H01L218238
CPC分类号： H01L21/7684 , H01L21/76838 , H01L23/53228 , H01L2924/0002 , H01L2924/00
摘要： The invention teaches the addition of copper lines, these copper lines to be added to isolated copper lines or to selected copper lines within a collection of copper lines. The invention also teaches the addition of copper end caps to isolated copper lines or to selected copper lines within a collection of copper lines. The invention further teaches the widening of copper lines for isolated copper lines or selected copper lines within a collection of copper lines.
摘要翻译：本发明教导了铜线的添加，这些铜线被添加到隔离铜线或铜线集合内的选定铜线。本发明还教导了将铜端盖添加到铜线集合中的隔离铜线或铜线。本发明进一步教导了铜线集合中用于隔离铜线或选定铜线的铜线的扩大。

14. 发明授权

US06358119B1 Way to remove CU line damage after CU CMP 有权
标题翻译：在CU CMP之后删除CU线损坏的方法
公开(公告)号：US06358119B1
公开(公告)日：2002-03-19
申请号：US09336808
申请日：1999-06-21
申请人： Tsu Shih , Jih-Churng Twu , Ying-Ho Chen , Syun-Ming Jang
发明人： Tsu Shih , Jih-Churng Twu , Ying-Ho Chen , Syun-Ming Jang
IPC分类号： B24B100
CPC分类号： B24B37/12 , B24B37/015 , B24B55/02
摘要： The invention provides a method and an apparatus that prevent the accumulation of copper ions during CMP of copper lines by performing the CMP process at low temperatures and by maintaining this low temperature during the CMP process by adding a slurry that functions as a corrosion inhibitor.
摘要翻译：本发明提供了一种方法和装置，其通过在低温下进行CMP工艺，并且通过添加用作腐蚀抑制剂的浆料在CMP工艺期间保持该低温来防止铜线的CMP中的铜离子的累积。

15. 发明授权

US6153526A Method to remove residue in wolfram CMP 有权
标题翻译：去除残留物的方法
公开(公告)号：US6153526A
公开(公告)日：2000-11-28
申请号：US320758
申请日：1999-05-27
申请人： Tsu Shih , Jih-Churng Twu
发明人： Tsu Shih , Jih-Churng Twu
IPC分类号： H01L21/3105 , H01L21/321 , H01L21/00
CPC分类号： H01L21/31053 , H01L21/3212
摘要： A new method for removing particle residue from the surface of semiconductor wafers that contain wolfram plugs. A series of polishing and buffing steps is performed; the first of this is a wolfram CMP using a hard polishing pad. An oxide buffing operation is further performed on the wafer surface; a soft pad is used for this buffing operation. The buffing operation is followed by a wolfram CMP that is applied for a short period of time using a soft polishing pad thereby removing the protruding top of the wolfram plug and the oxide particles from the vicinity of the wolfram plugs.
摘要翻译：一种从包含钨丝塞的半导体晶片表面去除颗粒残留物的新方法。进行一系列抛光和抛光步骤; 第一个是使用硬抛光垫的钨粉CMP。在晶片表面上进一步进行氧化物抛光操作; 一个软垫用于这种抛光操作。抛光操作之后是使用软抛光垫施加短时间的钨粉CMP，从而从钨粉塞附近除去钨骨塞的突出顶部和氧化物颗粒。

16. 发明授权

US06924215B2 Method of monitoring high tilt angle of medium current implant 失效
标题翻译：监测中等电流植入物高倾角的方法
公开(公告)号：US06924215B2
公开(公告)日：2005-08-02
申请号：US10157558
申请日：2002-05-29
申请人： Hung-Ta Huang , Hsueh-Li Sun , Juinn-Jie Chang , Stanley Huang , Jih-Churng Twu , Tom Tseng
发明人： Hung-Ta Huang , Hsueh-Li Sun , Juinn-Jie Chang , Stanley Huang , Jih-Churng Twu , Tom Tseng
IPC分类号： H01J37/304 , H01L21/66 , H01L21/336 , H01L21/265 , H01L21/331 , H01L21/36 , H01L21/425
CPC分类号： H01L22/20 , H01J37/3045 , H01J2237/31701
摘要： A method of monitoring and adjusting the position of a wafer with respect to an ion beam including setting the position of a wafer holder so that a wafer to be held therein is positioned at a tilt angle of 45 degrees and a twist angle of 45 degrees with respect to the path of an ion beam; positioning a n-type wafer without screen oxide in the wafer holder; implanting boron species into a region of the wafer at 160 KeV and a dose level of 5.0×1013 atoms/cm2; periodically measuring the sheet resistivity of a implanted wafer and readjusting the wafer tilt angle when the sheet resistivity is greater than 30 ohms/square.
摘要翻译：一种监测和调整晶片相对于离子束的位置的方法，包括设置晶片保持器的位置，使得待保持在其中的晶片位于45度的倾斜角度和45度的扭转角度，相对于离子束的路径; 将没有荧光体氧化物的n型晶片定位在晶片保持器中; 在160KeV下将硼物质注入晶片的区域，并且剂量水平为5.0×10 3原子/ cm 2; 周期性地测量植入晶片的片电阻率，并且当片电阻率大于30欧姆/平方时重新调整晶片倾斜角。

17. 发明授权

US06753249B1 Multilayer interface in copper CMP for low K dielectric 有权
标题翻译：用于低K电介质的铜CMP中的多层界面
公开(公告)号：US06753249B1
公开(公告)日：2004-06-22
申请号：US09759908
申请日：2001-01-16
申请人： Ying-Ho Chen , Jih-Churng Twu , Weng Chang
发明人： Ying-Ho Chen , Jih-Churng Twu , Weng Chang
IPC分类号： H01L214763
CPC分类号： H01L21/7684
摘要： An improved and new process, used for the elimination of copper line damage, copper defects, non-uniformity improvement, with low dishing and erosion, in damacene processing, is disclosed. This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to the elimination of copper line damage for damascene processing, by depositing a multilayer interface material, consisting of a mechanically hard film and a soft film, over a low dielectric constant, interlevel metal dielectric (IMD), and subsequently chemical mechanical polishing (CMP) back the excess material to planarize the surface.
摘要翻译：公开了一种改进的新工艺，用于消除铜线损伤，铜缺陷，不均匀性改进，具有较低的凹陷和侵蚀。本发明涉及一种用于半导体集成电路器件的制造方法，更具体地说，涉及通过在低温下沉积由机械硬膜和软膜组成的多层界面材料来消除镶嵌加工中的铜线损伤介电常数，层间金属电介质（IMD）和随后的化学机械抛光（CMP）回退多余的材料以使表面平坦化。

18. 发明授权

US06642128B1 Method for high temperature oxidations to prevent oxide edge peeling 有权
标题翻译：高温氧化防止氧化皮边缘剥落的方法
公开(公告)号：US06642128B1
公开(公告)日：2003-11-04
申请号：US10140396
申请日：2002-05-06
申请人： Ching-Shan Lu , Kuo-Bin Huang , Jih-Churng Twu
发明人： Ching-Shan Lu , Kuo-Bin Huang , Jih-Churng Twu
IPC分类号： H01L21322
CPC分类号： H01L21/76224
摘要： A method for preventing oxide layer peeling in a high temperature annealing process including providing a plurality of spaced apart stacked semiconductor wafers for carrying out a high temperature annealing process including ambient nitrogen gas the plurality of spaced apart stacked semiconductor wafers stacked such that a process surface including an oxide layer of at least one semiconductor wafer is adjacent to a backside surface of another semiconductor wafer said backside surface having a layer of silicon nitride formed thereon prior to carrying out the high temperature annealing process; and, carrying out the high temperature annealing process.
摘要翻译：一种用于防止在高温退火过程中氧化层剥离的方法，包括提供多个间隔堆叠的半导体晶片，用于执行包括环境氮气的高温退火工艺，所述多个间隔堆叠的半导体晶片被堆叠，使得处理表面包括在进行高温退火处理之前，至少一个半导体晶片的氧化物层与另一半导体晶片的背面相邻，所述背面具有形成在其上的氮化硅层; 并进行高温退火处理。

19. 发明授权

US06228760B1 Use of PE-SiON or PE-OXIDE for contact or via photo and for defect reduction with oxide and W chemical-mechanical polish 有权
标题翻译：使用PE-SiON或PE-OXIDE进行接触或通过照相和氧化物和W化学机械抛光的缺陷还原
公开(公告)号：US06228760B1
公开(公告)日：2001-05-08
申请号：US09263563
申请日：1999-03-08
申请人： Chen-Hua Yu , Syun-Ming Jang , Tsu Shih , Anthony Yen , Jih-Churng Twu
发明人： Chen-Hua Yu , Syun-Ming Jang , Tsu Shih , Anthony Yen , Jih-Churng Twu
IPC分类号： H01L214763
CPC分类号： H01L21/0276 , H01L21/31144 , H01L21/3144 , H01L21/3145 , H01L21/7684 , Y10S438/97
摘要： A method forming a protective (SiON or PE-Ox) dielectric anti-reflective coating (DARC) over a di electric layer after a chemical-mechanical polish dielectric layer planarization process and before a chemical-mechanical polish of a conductive layer used in a contact or via plug formation. A dielectric layer is chemical-mechanical polished thereby creating microscratches in the dielectric layer. The invention's protective SiON or PE-OX DARC layer is formed over the dielectric layer whereby the protective SiON or PE-OX DARC layer fills in the microscratches. A first opening is etched in he protective layer and the dielectric layer. A conductive layer is formed over the protective layer and fills the first opening. The conductive layer is chemical-mechanical polished to remove the conductive layer from over the protective layer and to form an interconnect filling the first opening. The protective SiON or PE-OX DARC layer is used as a CMP stop thereby preventing microscratches in the dielectric layer.
摘要翻译：在化学机械抛光介电层平坦化工艺之后和用于接触的导电层的化学机械抛光之前，在二电层上形成保护性（SiON或PE-Ox）电介质抗反射涂层（DARC）的方法或通过插塞形成。电介质层被化学机械抛光，从而在电介质层中形成微细结构。本发明的保护性SiON或PE-OX DARC层形成在电介质层上，由此保护性SiON或PE-OX DARC层填充在微细凹槽中。在其保护层和电介质层中蚀刻第一开口。导电层形成在保护层上并填充第一开口。导电层被化学机械抛光以从保护层上方移除导电层并形成填充第一开口的互连。使用保护性SiON或PE-OX DARC层作为CMP阻挡层，从而防止电介质层中的微细纹。

20. 发明授权

US06197669B1 Reduction of surface defects on amorphous silicon grown by a low-temperature, high pressure LPCVD process 有权
标题翻译：通过低温，高压LPCVD工艺生长的非晶硅上减少表面缺陷
公开(公告)号：US06197669B1
公开(公告)日：2001-03-06
申请号：US09292361
申请日：1999-04-15
申请人： Jih-Churng Twu , Syun-Ming Jang , Chen-Hua Yu
发明人： Jih-Churng Twu , Syun-Ming Jang , Chen-Hua Yu
IPC分类号： H01L213205
CPC分类号： C23C16/24 , H01L21/02381 , H01L21/02532 , H01L21/02576 , H01L21/02579 , H01L21/0262
摘要： A method is provided for depositing an amorphous silicon thin film on a substrate. The method is carried out in a reactor chamber and can be a LPCVD, PECVD or RTCVD process. The method comprises introducing a gas species into the reactor chamber for a time sufficient to dehydrate the substrate and to form a thin layer of silicon on the substrate. Following formation of the thin layer of silicon, a dopant gas is introduced into the reactor chamber to form the doped silicon thin film. The temperature and pressure within the chamber is set to minimize formation of surface irregularities or pits within the thin amorphous silicon layer.
摘要翻译：提供了一种在衬底上沉积非晶硅薄膜的方法。该方法在反应器室中进行，并且可以是LPCVD，PECVD或RTCVD工艺。该方法包括将气体物质引入反应器室中足以使基底脱水并在基底上形成薄的硅层的时间。在形成薄层的硅之后，将掺杂剂气体引入反应器室以形成掺杂的硅薄膜。室内的温度和压力被设定为使薄的非晶硅层内的表面凹凸或凹坑的形成最小化。

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