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1. 发明授权

US06500753B2 Method to reduce the damages of copper lines 有权
标题翻译：减少铜线损坏的方法
公开(公告)号：US06500753B2
公开(公告)日：2002-12-31
申请号：US09838209
申请日：2001-04-20
申请人： Syun-Ming Jang , Ying-Ho Chen , Jih-Churng Twu , Chen-Hua Yu
发明人： Syun-Ming Jang , Ying-Ho Chen , Jih-Churng Twu , Chen-Hua Yu
IPC分类号： H01L218238
CPC分类号： H01L21/7684 , H01L21/76838 , H01L23/53228 , H01L2924/0002 , H01L2924/00
摘要： The invention teaches the addition of copper lines, these copper lines to be added to isolated copper lines or to selected copper lines within a collection of copper lines. The invention also teaches the addition of copper end caps to isolated copper lines or to selected copper lines within a collection of copper lines. The invention further teaches the widening of copper lines for isolated copper lines or selected copper lines within a collection of copper lines.
摘要翻译：本发明教导了铜线的添加，这些铜线被添加到隔离铜线或铜线集合内的选定铜线。本发明还教导了将铜端盖添加到铜线集合中的隔离铜线或铜线。本发明进一步教导了铜线集合中用于隔离铜线或选定铜线的铜线的扩大。

2. 发明授权

US06211098B1 Wet oxidation method for forming silicon oxide dielectric layer 有权
标题翻译：用于形成氧化硅介电层的湿式氧化法
公开(公告)号：US06211098B1
公开(公告)日：2001-04-03
申请号：US09252337
申请日：1999-02-18
申请人： Jih-Churng Twu , Syun-Ming Jang , Chen-Hua Yu
发明人： Jih-Churng Twu , Syun-Ming Jang , Chen-Hua Yu
IPC分类号： H01L2126
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L29/517 , H01L29/518
摘要： A method for forming a silicon oxide gate oxide dielectric layer upon a silicon semiconductor substrate employed within a microelectronics fabrication. There is provided a silicon semiconductor substrate. There is then formed upon the silicon semiconductor substrate, empolying thermal annealing of the silicon semiconductor substrate at an elevated temperature in a gas mixture of oxygen, hydrogen and a diluent gas, a silicon oxide gate oxide dielectric layer with enhanced dielectric properties and more precise control of the silicon oxide dielectric layer thickness.
摘要翻译：一种在微电子学制造中使用的硅半导体衬底上形成氧化硅栅极氧化物电介质层的方法。提供硅半导体衬底。然后形成在硅半导体衬底上，在氧气，氢气和稀释气体的气体混合物中，在升高的温度下对硅半导体衬底进行热退火，具有增强介电特性和更精确控制的氧化硅栅氧化物介电层的氧化硅介电层厚度。

3. 发明授权

US06228760B1 Use of PE-SiON or PE-OXIDE for contact or via photo and for defect reduction with oxide and W chemical-mechanical polish 有权
标题翻译：使用PE-SiON或PE-OXIDE进行接触或通过照相和氧化物和W化学机械抛光的缺陷还原
公开(公告)号：US06228760B1
公开(公告)日：2001-05-08
申请号：US09263563
申请日：1999-03-08
申请人： Chen-Hua Yu , Syun-Ming Jang , Tsu Shih , Anthony Yen , Jih-Churng Twu
发明人： Chen-Hua Yu , Syun-Ming Jang , Tsu Shih , Anthony Yen , Jih-Churng Twu
IPC分类号： H01L214763
CPC分类号： H01L21/0276 , H01L21/31144 , H01L21/3144 , H01L21/3145 , H01L21/7684 , Y10S438/97
摘要： A method forming a protective (SiON or PE-Ox) dielectric anti-reflective coating (DARC) over a di electric layer after a chemical-mechanical polish dielectric layer planarization process and before a chemical-mechanical polish of a conductive layer used in a contact or via plug formation. A dielectric layer is chemical-mechanical polished thereby creating microscratches in the dielectric layer. The invention's protective SiON or PE-OX DARC layer is formed over the dielectric layer whereby the protective SiON or PE-OX DARC layer fills in the microscratches. A first opening is etched in he protective layer and the dielectric layer. A conductive layer is formed over the protective layer and fills the first opening. The conductive layer is chemical-mechanical polished to remove the conductive layer from over the protective layer and to form an interconnect filling the first opening. The protective SiON or PE-OX DARC layer is used as a CMP stop thereby preventing microscratches in the dielectric layer.
摘要翻译：在化学机械抛光介电层平坦化工艺之后和用于接触的导电层的化学机械抛光之前，在二电层上形成保护性（SiON或PE-Ox）电介质抗反射涂层（DARC）的方法或通过插塞形成。电介质层被化学机械抛光，从而在电介质层中形成微细结构。本发明的保护性SiON或PE-OX DARC层形成在电介质层上，由此保护性SiON或PE-OX DARC层填充在微细凹槽中。在其保护层和电介质层中蚀刻第一开口。导电层形成在保护层上并填充第一开口。导电层被化学机械抛光以从保护层上方移除导电层并形成填充第一开口的互连。使用保护性SiON或PE-OX DARC层作为CMP阻挡层，从而防止电介质层中的微细纹。

4. 发明授权

US06197669B1 Reduction of surface defects on amorphous silicon grown by a low-temperature, high pressure LPCVD process 有权
标题翻译：通过低温，高压LPCVD工艺生长的非晶硅上减少表面缺陷
公开(公告)号：US06197669B1
公开(公告)日：2001-03-06
申请号：US09292361
申请日：1999-04-15
申请人： Jih-Churng Twu , Syun-Ming Jang , Chen-Hua Yu
发明人： Jih-Churng Twu , Syun-Ming Jang , Chen-Hua Yu
IPC分类号： H01L213205
CPC分类号： C23C16/24 , H01L21/02381 , H01L21/02532 , H01L21/02576 , H01L21/02579 , H01L21/0262
摘要： A method is provided for depositing an amorphous silicon thin film on a substrate. The method is carried out in a reactor chamber and can be a LPCVD, PECVD or RTCVD process. The method comprises introducing a gas species into the reactor chamber for a time sufficient to dehydrate the substrate and to form a thin layer of silicon on the substrate. Following formation of the thin layer of silicon, a dopant gas is introduced into the reactor chamber to form the doped silicon thin film. The temperature and pressure within the chamber is set to minimize formation of surface irregularities or pits within the thin amorphous silicon layer.
摘要翻译：提供了一种在衬底上沉积非晶硅薄膜的方法。该方法在反应器室中进行，并且可以是LPCVD，PECVD或RTCVD工艺。该方法包括将气体物质引入反应器室中足以使基底脱水并在基底上形成薄的硅层的时间。在形成薄层的硅之后，将掺杂剂气体引入反应器室以形成掺杂的硅薄膜。室内的温度和压力被设定为使薄的非晶硅层内的表面凹凸或凹坑的形成最小化。

5. 发明授权

US06706577B1 Formation of dual gate oxide by two-step wet oxidation 失效
标题翻译：通过两步湿氧化形成双栅氧化物
公开(公告)号：US06706577B1
公开(公告)日：2004-03-16
申请号：US09298879
申请日：1999-04-26
申请人： Jih-Churng Twu , Syun-Ming Jang , Chen-Hua Yu
发明人： Jih-Churng Twu , Syun-Ming Jang , Chen-Hua Yu
IPC分类号： H01L218238
CPC分类号： H01L21/823857 , H01L27/10894
摘要： A method of simultaneously forming differential gate oxide for both high and low voltage transistors using a two-step wet oxidation process is described. A semiconductor substrate is provided wherein active areas of the substrate are isolated from other active areas and wherein there is at least one low voltage area in which a low voltage transistor will be formed and at least one high voltage area in which a high voltage transistor will be formed. The surface of the semiconductor substrate is wet oxidized to form a first layer of gate oxide on the surface of the semiconductor substrate in the active areas. The low voltage active area is covered with a mask. The surface of the semiconductor substrate is wet oxidized again where it is not covered by the mask to form a second layer of gate oxide under the first gate oxide layer in the high voltage active area. The mask is removed. A layer of polysilicon is deposited overlying the first gate oxide layer in the low voltage active area and overlying the second gate oxide layer in the high voltage active area and patterned to form gate electrodes for the low voltage and high voltage transistors in the fabrication of an integrated circuit.
摘要翻译：描述了使用两步湿氧化工艺同时形成用于高压和低压晶体管的差分栅极氧化物的方法。提供一种半导体衬底，其中衬底的有源区域与其他有源区域隔离，并且其中存在将形成低压晶体管的至少一个低电压区域和至少一个高电压区域，其中高压晶体管将形成。半导体衬底的表面被湿式氧化以在有源区域中在半导体衬底的表面上形成第一层栅极氧化物层。低电压有源区域用掩模覆盖。半导体衬底的表面被再次湿式氧化，其中未被掩模覆盖，以在高电压有源区的第一栅氧化层下形成第二层栅氧化层。去除面具。一层多晶硅被沉积在低电压有源区中的第一栅极氧化物层上并覆盖在高电压有源区中的第二栅极氧化物层上并被图案化以在制造中形成低电压和高压晶体管的栅电极集成电路。

6. 发明授权

US06239023B1 Method to reduce the damages of copper lines 有权
公开(公告)号：US06239023B1
公开(公告)日：2001-05-29
申请号：US09320757
申请日：1999-05-27
申请人： Syun-Ming Jang , Ying-Ho Chen , Jih-Churng Twu , Chen-Hua Yu
发明人： Syun-Ming Jang , Ying-Ho Chen , Jih-Churng Twu , Chen-Hua Yu
IPC分类号： H01L214763
CPC分类号： H01L21/7684 , H01L21/76838 , H01L23/53228 , H01L2924/0002 , H01L2924/00
摘要： The invention teaches the addition of copper lines, these copper lines to be added to isolated copper lines or to selected copper lines within a collection of copper lines. The invention also teaches the addition of copper end caps to isolated copper lines or to selected copper lines within a collection of copper lines. The invention further teaches the widening of copper lines for isolated copper lines or selected copper lines within a collection of copper lines.

7. 发明授权

US06358119B1 Way to remove CU line damage after CU CMP 有权
标题翻译：在CU CMP之后删除CU线损坏的方法
公开(公告)号：US06358119B1
公开(公告)日：2002-03-19
申请号：US09336808
申请日：1999-06-21
申请人： Tsu Shih , Jih-Churng Twu , Ying-Ho Chen , Syun-Ming Jang
发明人： Tsu Shih , Jih-Churng Twu , Ying-Ho Chen , Syun-Ming Jang
IPC分类号： B24B100
CPC分类号： B24B37/12 , B24B37/015 , B24B55/02
摘要： The invention provides a method and an apparatus that prevent the accumulation of copper ions during CMP of copper lines by performing the CMP process at low temperatures and by maintaining this low temperature during the CMP process by adding a slurry that functions as a corrosion inhibitor.
摘要翻译：本发明提供了一种方法和装置，其通过在低温下进行CMP工艺，并且通过添加用作腐蚀抑制剂的浆料在CMP工艺期间保持该低温来防止铜线的CMP中的铜离子的累积。

8. 发明授权

US06376377B1 Post chemical mechanical polish (CMP) planarizing substrate cleaning method employing enhanced substrate hydrophilicity 有权
标题翻译：后化学机械抛光（CMP）平面化基板清洗方法采用增强的基板亲水性
公开(公告)号：US06376377B1
公开(公告)日：2002-04-23
申请号：US09541487
申请日：2000-04-03
申请人： Weng Chang , Ying-Ho Chen , Jih-Churng Twu , Syun-Ming Jang
发明人： Weng Chang , Ying-Ho Chen , Jih-Churng Twu , Syun-Ming Jang
IPC分类号： H01L21302
CPC分类号： H01L21/76826 , H01L21/02074 , H01L21/3212 , H01L21/76801 , H01L21/76807 , H01L21/76825 , H01L21/76888
摘要： Within a method for removing from over a substrate a chemical mechanical polish (CMP) residue layer there is first provided a substrate. There is then formed over the substrate: (1) a chemical mechanical polish (CMP) substrate layer having an aperture formed therein; (2) a chemical mechanical polish (CMP) planarized patterned layer formed within the aperture within the chemical mechanical polish (CMP) substrate layer; and (3) a chemical mechanical polish (CMP) residue layer formed upon at least one of the chemical mechanical polish substrate layer and the chemical mechanical polish (CMP) planarized patterned layer, where at least one of the chemical mechanical polish (CMP) substrate layer and the chemical mechanical polish (CMP) planarized patterned layer has a first aqueous contact angle. There is then treated the at least one of the chemical mechanical polish (CMP) substrate layer and the chemical mechanical polish (CMP) planarized patterned layer having the first aqueous contact angle to provide at least one of a hydrophilic chemical mechanical polish (CMP) substrate layer and a hydrophilic chemical mechanical polish (CMP) planarized patterned layer having a second aqueous contact angle less than the first aqueous contact angle. Finally, there is then removed the chemical mechanical polish (CMP) residue layer from the at least one of the hydrophilic chemical mechanical polish (CMP) substrate layer and the hydrophilic chemical mechanical polish (CMP) planarized patterned layer with an aqueous cleaner composition.
摘要翻译：在用于从衬底上除去化学机械抛光（CMP）残留层的方法中，首先提供衬底。然后在衬底上形成：（1）其中形成有孔的化学机械抛光（CMP）衬底层; （2）化学机械抛光（CMP）平面化图案层，其形成在化学机械抛光（CMP）衬底层内的孔内; 化学机械抛光（CMP）残留层形成在至少一个化学机械抛光衬底层和化学机械抛光（CMP）平面化图案层上，其中化学机械抛光（CMP）衬底层和化学机械抛光（CMP）平面化图案层具有第一水接触角。然后，处理具有第一水接触角的化学机械抛光（CMP）衬底层和化学机械抛光（CMP）平坦化图案化层中的至少一个以提供亲水化学机械抛光（CMP）衬底中的至少一个层和亲水化学机械抛光（CMP）平面化图案层，其具有小于第一水接触角的第二水接触角。最后，用水性清洁剂组合物从亲水化学机械抛光（CMP）衬底层和亲水化学机械抛光（CMP）平坦化图案化层中的至少一个去除化学机械抛光（CMP）残留层。

9. 发明授权

US06589872B1 Use of low-high slurry flow to eliminate copper line damages 有权
标题翻译：使用低 - 高泥浆流量来消除铜线损坏
公开(公告)号：US06589872B1
公开(公告)日：2003-07-08
申请号：US09304302
申请日：1999-05-03
申请人： Jih-Churng Twu , Ying-Ho Chen , Tsu Shih , Syun-Ming Jang
发明人： Jih-Churng Twu , Ying-Ho Chen , Tsu Shih , Syun-Ming Jang
IPC分类号： H01K2120
CPC分类号： B24B37/042 , B24B49/00 , B24B57/02
摘要： The invention teaches a new method of applying slurry during the process of chemical mechanical polishing of copper surfaces. By varying the rate of slurry deposition, starting out with a low rate of slurry flow that is increased as the polishing process proceeds, the invention obtains good planarity for copper surfaces while saving on the amount of slurry that is being used for the copper surface polishing process.
摘要翻译：本发明教导了在铜表面的化学机械抛光过程中施加浆料的新方法。通过改变浆料沉积速率，随着抛光工艺的进行，随着浆料流动速度的降低而开始，本发明对于铜表面获得了良好的平面性，同时节省了用于铜表面抛光的浆料量处理。

10. 发明授权

US06429118B1 Elimination of electrochemical deposition copper line damage for damascene processing 有权
标题翻译：消除电化学沉积铜线损坏镶嵌加工
公开(公告)号：US06429118B1
公开(公告)日：2002-08-06
申请号：US09664414
申请日：2000-09-18
申请人： Ying-Ho Chen , Syun-Ming Jang , Jih-Churng Twu , Tsu Shih
发明人： Ying-Ho Chen , Syun-Ming Jang , Jih-Churng Twu , Tsu Shih
IPC分类号： H01L213213
CPC分类号： H01L21/76802 , H01L21/2855 , H01L21/7684 , H01L21/76877
摘要： An improved and new process, used for the elimination of copper line damage in damacene processing, is disclosed. By depositing copper by physical vapor deposition (PVD), sputtering, preferably by an ion metal plasma (IMP) scheme or chemical vapor deposition (CVD), the deposited copper fills pinholes or intra-cracks (micro-cracks), caused by poor gap filling of purely electrochemical deposition of copper plating. By this process or method, chemical attack on copper lines, by chemicals in the subsequent chemical mechanical polish (CMP) back and post-cleaning steps, is prevented.
摘要翻译：公开了一种改进和新的方法，用于消除碲化氢处理中的铜线损伤。通过物理气相沉积（PVD），优选通过离子金属等离子体（IMP）方案或化学气相沉积（CVD）沉积铜，沉积的铜填充由差的间隙引起的针孔或裂纹（微裂纹）填充电镀纯电化学沉积。通过该方法或方法，可以防止化学品在后续的化学机械抛光（CMP）背面和后清洗步骤中对铜线进行化学侵蚀。

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