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11. 发明授权

US07057938B2 Nonvolatile memory cell and operating method 有权
标题翻译：非易失性存储单元和操作方法
公开(公告)号：US07057938B2
公开(公告)日：2006-06-06
申请号：US10756777
申请日：2004-01-14
申请人： Chih Chieh Yeh , Hung Yueh Chen , Yi Ying Liao , Wen Jer Tsai , Tao Cheng Lu
发明人： Chih Chieh Yeh , Hung Yueh Chen , Yi Ying Liao , Wen Jer Tsai , Tao Cheng Lu
IPC分类号： G11C16/00
CPC分类号： G11C16/10 , G11C16/0475 , H01L21/28282 , H01L29/66833 , H01L29/792 , H01L29/7923
摘要： One embodiment of the present invention provides a system having a nonvolatile memory comprising a p type semiconductor substrate, an oxide layer over the p type semiconductor substrate, a nitride layer over the oxide layer, an additional oxide layer over the nitride layer, a gate over the additional oxide layer, two N+ junctions in the p type semiconductor layer, a source and drain respectively formed in the two N+ junctions, a first bit and a second bit in the nonvolatile memory, and accordingly at least two states of operation (i.e., erase and program) therefor. That is, one bit in the nonvolatile memory can either be in an erase state or program state. For erasing a bit, electrons are injected at the gate of the nonvolatile memory. For programming a bit, electric holes are injected or electrons are reduced for that bit. The present invention also provides a method for sensing and reading at least one bit in a nonvolatile memory comprising applying a bias voltage to the memory, detecting a threshold voltage or read current, comparing the threshold voltage with a reference voltage or comparing the read current with a reference current, and identifying the at least one bit as erased or programmed.
摘要翻译：本发明的一个实施例提供一种具有非易失性存储器的系统，其包括ap型半导体衬底，p型半导体衬底上的氧化物层，氧化物层上方的氮化物层，氮化物层上的附加氧化物层，分别形成在两个N +结中的源极和漏极，非易失性存储器中的第一位和第二位，以及相应地至少两个操作状态（即擦除）的附加氧化物层，p型半导体层中的两个N +结，和程序）。也就是说，非易失性存储器中的一位可以处于擦除状态或程序状态。为了擦除一点，电子注入非易失性存储器的栅极。为了编程一点，注入电孔或减少电子的位。本发明还提供了一种用于感测和读取非易失性存储器中的至少一个位的方法，包括向存储器施加偏置电压，检测阈值电压或读取电流，将阈值电压与参考电压进行比较，或将读取的电流与参考电流，并将所述至少一个位识别为擦除或编程。

12. 发明授权

US06215697B1 Multi-level memory cell device and method for self-converged programming 有权
标题翻译：用于自融合编程的多级存储单元器件和方法
公开(公告)号：US06215697B1
公开(公告)日：2001-04-10
申请号：US09231044
申请日：1999-01-14
申请人： Tao Cheng Lu , Der Shin Shyu , Shi Xian Chen , Wen Jer Tsai , Mam Tsung Wang
发明人： Tao Cheng Lu , Der Shin Shyu , Shi Xian Chen , Wen Jer Tsai , Mam Tsung Wang
IPC分类号： G11C1604
CPC分类号： G11C16/10 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C2211/5625 , G11C2211/5634
摘要： A multi-level memory cell device and method for self-converged programming which includes a memory cell switchably coupled to a non-programmable reference cell (or dummy cell), the cells arranged in respective arrays. A current source voltage between the source node and ground of the cells is relational to the threshold voltage, so as the threshold voltage is increased, the current source voltage decreases. The threshold voltage of the dummy cell is set by a stable voltage source. The memory cell is programmed and the current source voltage of the memory cell is compared to the current source voltage of the reference cell and therefore the difference in the voltages can be used to sense convergence of the programmed cell with a target threshold level set on the reference cell. A controller is also included between the reference cell and memory cell for adjusting the threshold voltage of the dummy cell according to the gate coupling ratio of the floating gate memory cell. The controller is also used to adjust voltages for both programming and read operations. The voltage difference resulting from the sources of the memory cell and reference cell is used to provide program control signals and thereby cease programming of the memory cell when convergence has been reached.
摘要翻译：一种用于自融合编程的多级存储单元设备和方法，其包括可切换地耦合到非可编程参考单元（或虚拟单元）的存储单元，所述单元布置在相应阵列中。电池的源节点和地之间的电流源电压与阈值电压相关，因此阈值电压增加，电流源电压降低。虚拟单元的阈值电压由稳定的电压源设定。对存储单元进行编程，并将存储单元的电流源电压与参考单元的电流源电压进行比较，因此可以使用电压差来检测编程单元的收敛与在参考细胞。参考单元和存储单元之间还包括控制器，用于根据浮动栅极存储单元的栅极耦合比来调整虚设单元的阈值电压。控制器也用于调节编程和读取操作的电压。由存储器单元和参考单元的源产生的电压差用于提供程序控制信号，从而在已经达到收敛时停止存储单元的编程。

13. 发明授权

US07187590B2 Method and system for self-convergent erase in charge trapping memory cells 有权
标题翻译：电荷捕获存储器单元中自会聚擦除的方法和系统
公开(公告)号：US07187590B2
公开(公告)日：2007-03-06
申请号：US10876255
申请日：2004-06-24
申请人： Nian-Kai Zous , Wen-Jer Tsai , Hung-Yueh Chen , Tao Cheng Lu
发明人： Nian-Kai Zous , Wen-Jer Tsai , Hung-Yueh Chen , Tao Cheng Lu
IPC分类号： G11C16/04
CPC分类号： G11C16/0466 , H01L29/7885 , H01L29/792
摘要： A process and a memory architecture for operating a charge trapping memory cell is provided. The method for operating the memory cell includes establishing a high threshold state in the memory cell by injecting negative charge into the charge trapping structure to set a high state threshold. The method includes using a self-converging biasing procedure to establish a low threshold state for the memory cell by reducing the negative charge in the charge trapping structure to set the threshold voltage for the cell to a low threshold state. The negative charge is reduced in the memory cell by applying a bias procedure including at least one bias pulse. The bias pulse balances charge flow into and out of the charge trapping layer to achieve self-convergence on a desired threshold level. Thereby, an over-erase condition is avoided.
摘要翻译：提供了用于操作电荷捕获存储器单元的过程和存储器架构。用于操作存储单元的方法包括通过将负电荷注入到电荷俘获结构中来建立高的阈值状态，以设置高状态阈值。该方法包括使用自会聚偏移过程来通过减少电荷俘获结构中的负电荷来为存储器单元建立低阈值状态，以将电池的阈值电压设置为低阈值状态。通过施加包括至少一个偏置脉冲的偏置过程，在存储单元中负电荷减小。偏置脉冲平衡进入和离开电荷捕获层的电荷流，以在期望的阈值水平上实现自会聚。从而避免了过度擦除的情况。

14. 发明授权

US06181604B2 Method for fast programming of EPROMS and multi-level flash EPROMS 有权
标题翻译： EPROMS和多级闪存EPROMS的快速编程方法
公开(公告)号：US06181604B2
公开(公告)日：2001-01-30
申请号：US09359073
申请日：1999-07-22
申请人： Tao Cheng Lu , Wen Jer Tsai , Mam Tsung Wang , Chin Hsi Lin , Ful Long Ni
发明人： Tao Cheng Lu , Wen Jer Tsai , Mam Tsung Wang , Chin Hsi Lin , Ful Long Ni
IPC分类号： G11C1606
CPC分类号： G11C16/3427 , G11C11/5621 , G11C11/5628 , G11C16/0491 , G11C16/10 , G11C16/3418 , G11C2211/5621
摘要： A method for programming a semiconductor memory device, such as an EPROM or a Flash EPROM, which combines the advantages of ramping down a source voltage with the advantages associated with increasing a gate voltage. A programming period is divided into a program disturbance inhibited period and a program period. The programming period is further divided into sub-program periods, with each sub-program period having a program disturbance and a program period. A wordline WL voltage may increase with each sub-program period to improve the programming speed. Also, the program disturbance period may only be performed for the first sub-program period. Each sub-program period may also include a verify period, in order to implement a program and verify technique suitable for programming multi-level Flash EPROMS.
摘要翻译：一种用于编程诸如EPROM或闪存EPROM的半导体存储器件的方法，其结合了降低源电压的优点和与增加栅极电压相关联的优点。编程周期分为程序禁止干扰期和程序周期。编程周期进一步分为子程序周期，每个子程序周期都有程序干扰和程序周期。字线WL电压可能随着每个子程序周期而增加，以提高编程速度。此外，程序干扰周期可以仅在第一子程序周期执行。每个子程序周期还可以包括验证周期，以便实现适合于编程多级闪存EPROMS的程序和验证技术。

15. 发明授权

US06834263B2 NROM structure 有权
标题翻译： NROM结构
公开(公告)号：US06834263B2
公开(公告)日：2004-12-21
申请号：US09815129
申请日：2001-03-22
申请人： Yao Wen Chang , Tao Cheng Lu , Wen Jer Tsai
发明人： Yao Wen Chang , Tao Cheng Lu , Wen Jer Tsai
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： A macro model of a programmable NROM for simulating the characters of the NROM under programming operation. Charges are stored in a portion of the nitride material layer to for a charge trapped region when the NROM is programmed. A normal MOS symbol element and a short channel MOS symbol element are respectively represent a MOS without having the charge trapped region and a MOS with a charge trapped region. Moreover, the normal MOS symbol element is series with the short channel MOS symbol element, wherein a source of the short channel MOS symbol element is coupled with a drain of the normal MOS symbol element.
摘要翻译：可编程NROM的宏模型，用于在编程操作下模拟NROM的字符。当NROM被编程时，电荷被存储在氮化物材料层的一部分中以用于电荷俘获区域。正常MOS符号元件和短沟道MOS符号元件分别表示不具有电荷俘获区域的MOS和具有电荷俘获区域的MOS。此外，正常MOS符号元件与短沟道MOS符号元件串联，其中短沟道MOS符号元件的源极与正常MOS符号元件的漏极耦合。

16. 发明授权

US06320786B1 Method of controlling multi-state NROM 有权
标题翻译：控制多状态NROM的方法
公开(公告)号：US06320786B1
公开(公告)日：2001-11-20
申请号：US09777229
申请日：2001-02-05
申请人： Yao Wen Chang , Wen Jer Tsai , Tao Cheng Lu
发明人： Yao Wen Chang , Wen Jer Tsai , Tao Cheng Lu
IPC分类号： G11C1604
CPC分类号： G11C11/5671 , G11C16/0466
摘要： A method of controlling the multi-state NROM. A program is executed to inject electric charges that are trapped inside a nitride layer of the NROM. The amount of electric charges trapped inside the nitride layer is controlled so that the memory cell can have different threshold voltages. To read from the memory cell, a first variable voltage is applied to the gate electrode. According to the range of a second variable voltage applied to the drain terminal, three different potential levels, from the smallest to the largest, including a first potential level, a second potential level and a third potential level are set. The second input voltage is adjusted to the first potential level. When a high current is sensed, a first storage state is assumed. If little current is detected, the second input voltage is adjusted to the second potential level. When a high current is sensed, a second storage state is assumed. On the other hand, if little current is detected, the second input voltage is adjusted to the third potential level. Similarly, if a high current is sensed, a third storage state is assumed. Conversely, when little current is detected, a fourth storage state is assumed.
摘要翻译：一种控制多状态NROM的方法。执行程序以注入被俘获在NROM的氮化物层内部的电荷。控制在氮化物层内捕获的电荷量，使得存储单元可以具有不同的阈值电压。为了从存储单元读取，向栅电极施加第一可变电压。根据施加到漏极端子的第二可变电压的范围，设置包括第一电位电平，第二电位电平和第三电位电平的从最小到最大的三个不同的电位电平。将第二输入电压调整到第一电位电平。当检测到高电流时，假设第一存储状态。如果检测到小的电流，则将第二输入电压调整到第二电位电平。当感测到高电流时，假设第二存储状态。另一方面，如果检测到小的电流，则将第二输入电压调整到第三电位电平。类似地，如果感测到高电流，则假设第三存储状态。相反，当检测到少量电流时，假设第四存储状态。

17. 发明授权

US07180123B2 Method for programming programmable eraseless memory 有权
标题翻译：编程可编程擦除存储器的方法
公开(公告)号：US07180123B2
公开(公告)日：2007-02-20
申请号：US10642249
申请日：2003-08-15
申请人： Chih Chieh Yeh , Han Chao Lai , Wen Her Tsai , Tao Cheng Lu , Chih Yuan Lu
发明人： Chih Chieh Yeh , Han Chao Lai , Wen Her Tsai , Tao Cheng Lu , Chih Yuan Lu
IPC分类号： H01L29/76
CPC分类号： G11C11/5692 , G11C17/14 , G11C2211/5634 , H01L23/5252 , H01L27/101 , H01L2924/0002 , H01L2924/00
摘要： A method for programming a memory cell is based on applying stress to a memory cell, comprising a first electrode, a second electrode and an inter-electrode layer, to induce a progressive change in a property of the inter-electrode layer. The method includes a verify step including generating a signal, such as a cell current, indicating the value of the property in the selected memory cell. Then, the signal is compared with a reference signal to verify programming of the desired data. Because of the progressive nature of the change, many levels of programming can be achieved. The many levels of programming can be applied for programming a single cell more than once, without an erase process, to programming multiple bits in a single cell, and to a combination of multiple bit and multiple time of programming.
摘要翻译：用于对存储单元进行编程的方法是基于向包括第一电极，第二电极和电极间层的存储单元施加应力，以引起电极间层的性能的逐渐变化。该方法包括验证步骤，包括生成指示所选择的存储单元中的属性的值的诸如单元电流的信号。然后，将信号与参考信号进行比较，以验证所需数据的编程。由于变革的渐进性，可以实现多层次的编程。多个编程级别可以应用于单个单元的编程，而不需要擦除处理，以编程单个单元中的多个位，以及多个位和多个编程时间的组合。

18. 发明授权

US06204529B1 8 bit per cell non-volatile semiconductor memory structure utilizing trench technology and dielectric floating gate 有权
标题翻译： 8位每单元非易失性半导体存储器结构利用沟槽技术和介质浮栅
公开(公告)号：US06204529B1
公开(公告)日：2001-03-20
申请号：US09384482
申请日：1999-08-27
申请人： Hsing Lan Lung , Tao Cheng Lu , Mam Tsung Wang
发明人： Hsing Lan Lung , Tao Cheng Lu , Mam Tsung Wang
IPC分类号： H01L218247
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/7923 , H01L29/7926
摘要： The present application discloses a non-volatile semiconductor memory device for storing up to eight-bits of information. The device has a semiconductor substrate of one conductivity type, a central bottom diffusion region on top of a portion of the semiconductor substrate, a second semiconductor layer on top of the bottom diffusion region, and left and right diffusion regions formed in the second semiconductor layer apart from the central bottom diffusion region thus forming a first vertical channel between the right and central bottom diffusion regions. The device further includes a trapping dielectric layer formed over exposed portions of the semiconductor substrate, left, central and right bottom diffusion regions and second semiconductor layer and a wordline formed over the trapping dielectric layer. A methods of fabricating this novel cell using trench technology is also disclosed.
摘要翻译：本申请公开了一种用于存储多达8位信息的非易失性半导体存储器件。该器件具有一个导电类型的半导体衬底，半导体衬底的一部分的顶部上的中心底部扩散区域，在底部扩散区域的顶部上的第二半导体层，以及形成在第二半导体层中的左右扩散区域除了中心底部扩散区域，从而在右侧和中央底部扩散区域之间形成第一垂直通道。该器件还包括形成在半导体衬底，左，中，右底部扩散区和第二半导体层的暴露部分之上的俘获电介质层，以及形成在俘获电介质层上的字线。还公开了使用沟槽技术制造这种新型电池的方法。

19. 发明授权

US08164112B2 Electostatic discharge protection circuit coupled on I/O pad 有权
标题翻译：静电放电保护电路耦合在I / O焊盘上
公开(公告)号：US08164112B2
公开(公告)日：2012-04-24
申请号：US09801350
申请日：2001-03-07
申请人： Chun-Hsiang Lai , Meng Huang Liu , Tao Cheng Lu
发明人： Chun-Hsiang Lai , Meng Huang Liu , Tao Cheng Lu
IPC分类号： H01L29/74 , H01L23/62 , H02H9/00
CPC分类号： H01L27/0251 , H01L29/87
摘要： An I/O pad ESD protection circuit is composed of a SCR circuit, a first diode, a second diode, and an anti-latch-up circuit. The SCR circuit has a first connection terminal and a second connection terminal, respectively coupled to the I/O pad and the ground voltage, so as to discharge the electrostatic charges. The anti-latch-up circuit has two terminals, which are respectively coupled to the voltage source and the ground voltage, and another connection terminal, used to send an anti-latch-up signal to the SCR for changing the activating rate. The latch-up phenomenon is avoided.
摘要翻译： I / O焊盘ESD保护电路由SCR电路，第一二极管，第二二极管和防闩锁电路组成。 SCR电路具有分别耦合到I / O焊盘和接地电压的第一连接端子和第二连接端子，以便放电静电电荷。防闩锁电路具有分别耦合到电压源和接地电压的两个端子，以及用于向SCR发送防闩锁信号以用于改变激活速率的另一个连接端子。避免了闩锁现象。

20. 发明授权

US06618230B2 Electrostatic discharge cell of integrated circuit 有权
公开(公告)号：US06618230B2
公开(公告)日：2003-09-09
申请号：US09909946
申请日：2001-07-23
申请人： Meng Huaug Liu , Chun-Hsiang Lai , Sing Su , Tao Cheng Lu
发明人： Meng Huaug Liu , Chun-Hsiang Lai , Sing Su , Tao Cheng Lu
IPC分类号： H02H900
CPC分类号： H01L27/0266
摘要： The present invention provides an IC ESD cell, which is applicable to multiple-power-input and mixed-voltage ICs and capable of maintaining power sequence independence of each power source. The ESD cell of the present invention comprises a voltage selector circuit, which connects two separate power sources to select the one having a higher potential as the output voltage. An NMOS is used to connect the two separate power sources. An RC circuit is connected to an output of the voltage selector circuit to distinguish ESD event from normal power source. Therefore, the channel of the NMOS will be conducted to let the ESD current be led out via a designed path, hence preventing internal circuits of an IC from damage and accomplishing the object of whole chip protection.

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